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A novel photoreceiver architecture enabling parallel processing in the electronic domain of a high-speed optical signal is demonstrated. This allows the electronics to operate at significantly lower frequency than the optical signal and hence reduce power consumption and the impact of parasitics. The photoreceiver performs optical time sampling with four integrated SiGe photodetectors connected in series by waveguide delay lines. Four variations of the optical time sampling receiver are designed and demonstrated which differ by the data rate (10 Gb/s and 20 Gb/s) and silicon delay waveguide loss (2.5 dB/cm and 0.2 dB/cm). The bit error rate performance of the photodetectors in the receiver was measured individually and reached a performance below 1 × 10−10 at an input optical power between 4.8 and 6.3 dBm through an off-chip 50 Ω load at the output. After O/E conversion, the electrical signal (one segment of 215 − 1 PRBS data) from each of the photodetector is processed without errors at a quarter of the bit rate, leading to an overall more power efficient receiver front-end.
© 2015 Optical Society of America
1. Introduction
The advent of standardized silicon photonic (SiP) process has made the fabrication of complex optical systems affordable. Therefore, new paradigms and architectures can be explored to optimize optoelectronic devices. For instance, it is now possible to perform on-chip processing in the optical domain in order to ease the performance requirements on electrical processing and hence reduce the cost and/or the power consumption of electronic circuits in telecommunication networks [1,2]. Based on this concept, we implemented a photoreceiver or optical front-end that performs optical time sampling to reduce the operating speed of its electronics components. The optical sampling allows to reduce the electronic processing speed by enabling parallel processing of the optical bit stream and thus the result is a deserialization of the data directly at the optoelectronic interface.
In optical communication links, a photodetector (PD) is a key building block in the receiver front-end. Moreover, in most commercial photoreceivers a transimpedance amplifier (TIA) is required to amplify the received electrical bits as well as to convert the photocurrent into a voltage. Germanium-based photodetectors on a Silicon-on-Insulator (SOI) substrate are promising candidates toward silicon photonic integration because of their high bandwidth (31 GHz, [3]) and possible low cost integration with electronics [4, 5]. To improve the sensitivity of Ge photoreceivers, TIAs can be wire bonded to PDs [4] (currently achieving optical sensitivity of −11.9 dBm at a 10 Gb/s data rate and −7.3 dBm at a 28 Gb/s data rate), or monolithically integrated [5] (optical sensitivity of −13.3 dBm at a 10 Gb/s data rate and −5.6 dBm at a 25 Gb/s data rate). One important limitation in photoreceivers is the bandwidth mismatch between the PD and the electronic TIA circuit. For example, whereas the bandwidth of Ge-on-SOI PD can be extended with inductive gain up to 60 GHz [6], a suitable TIA with such bandwidth remains challenging. While the low bandwidth of the TIAs helps remove some high frequency noise, if it is too low it causes intersymbol interference (ISI), which severely degrades the bit error rate (BER) performance of the receiver. Recent techniques addressing this challenge such as a double sampling method in the post processing electronic circuit of a photoreceiver achieved an optical sensitivity of −4.7 dBm at 24 Gb/s [7]. In this case a high-speed PD of 1 A/W responsivity was wirebonded to the TIA-less electronic front-end. Another interesting application is enabling high power handling capability in Ge-on-SOI PDs while maintaining their linearity. Indeed in [8], optical waveguide delay lines are used to balance the electrical phase delay of the electrode to design a Si-Ge traveling-wave PD array (Si-TWPDA). Four PDs are used to design a parallel-fed traveling-wave photodetector array, which increases the power handing capability as well as the linearity of the photoreceiver (optical input saturation power of 160 mW with a 65 mA output photocurrent). These demonstrate the benefits of developing new design methods either electronically or optically to overcome the responsivity-bandwidth trade-off of photoreceivers.
In this article, we implemented a photoreceiver that consists of a 1×4 time sampling PD array in a series architecture. The power of the incoming optical signal is distributed uniformly to each of the four PDs using directional couplers. The optical bit stream is delayed in increments of one bit period prior to each of the last three PDs using optical passive waveguide-based delays. To compensate for the incremental loss of the waveguides, directional couplers with different coupling ratios are used, such that each of the PD receives an equal amount of optical power. As such, each PD generates the same electrical bit streams but the four PDs are delayed with respect to each other. A similar approach can be found in a silicon photonics based optical equalizer demonstrated in [9], where Mach-Zehnder interferometer (MZI) based power splitters were thermally tuned to divide the optical power of the incoming signal and to set the coefficients of the equalizer or the finite impulse response (FIR) filter. The Si-Ge traveling-wave PD array (Si-TWPDA) demonstrated in [8], also optically divides the power of the incoming signal onto four channels, and, as mentioned in the above paragraph, it uses optical waveguide delay lines to balance the electrical phase delay of the electrode. However, in [8] the required delay length of the waveguides were small (in the multiples of 0.25 μm), therefore no power compensation was required to balance the delay waveguide loss. In this work, we present an analysis on the design of the coupling ratio of directional couplers such that equal power is obtained at the four photodetectors without thermal tuning when taking into account the loss from the incremental delay lines. We also show that low-loss SOI waveguides decreases variation in the required coupling ratio of the directional couplers with respect to change in the waveguide loss. This increases the tolerances on the coupling ratio of the directional couplers over variation in waveguide loss.
Next, we show that by using the correlation property between the four PD channels, it is possible to electronically process the photodetected signals at a quarter of the data rate to recover the original signal. This scheme simplifies the post processing electronic circuit design and reduces the dynamic power consumption of the electronic circuit by lowering the sampling rate of the received signal. The speed reduction factor is proportional to the number of PDs, which is only limited by the losses in the delay lines and the increased optical power splitting. Moreover, the overall insertion loss of the photoreceiver depends on the length of the optical delay waveguides, which is proportional to the duration of one bit. For example, for a 10 Gb/s photoreceiver the duration of a one bit delay is 100 ps, whereas for a 20 Gb/s photoreceiver this delay is 50 ps. Therefore, the overall insertion loss in a 10 Gb/s sampling photoreceiver will be higher compared to a 20 Gb/s sampling photoreceiver because the latter requires shorter delay waveguides. As such, we designed four variations of the optical time sampling front-end: 1) 10 Gb/s and 20 Gb/s optical time sampling front-end with typical 220 nm × 500 nm cross-section SOI waveguides (∼2.5–3 dB/cm propagation loss) and 2) 10 Gb/s and 20 Gb/s optical time sampling front-end with lower propagation loss (∼0.2 dB/cm) SOI waveguides. For all four photoreceivers we have measured BER below 10−10 for each of the four PD channels. We also propose a post-electronic front-end model to recover the original input bit stream at a quarter of the data rate. Using offline processing in MATLAB, the original 215 − 1 pseudorandom binary sequence (PRBS) input data is recovered for all of the four devices.
2. Design of the 1×4 sampling photodetector architecture
Figure 1 shows the schematic of the proposed architecture for the 20 Gb/s data rate optical front end. The layout and the number of components are the same for the four devices. A 20 Gb/s optical NRZ signal is received as the input to the grating coupler (GC). The energy of the optical signal is uniformly distributed over four output channels (Ch-1 to Ch-4) through three directional couplers (DC-1 to DC-3). To implement the one bit time delay of 50 ps, a ∼3.6 mm long silicon waveguide delay line is added between adjacent channels. The power coupling ratio of each directional coupler is adjusted by varying its coupling length (L1, L2 and L3) to compensate for the optical propagation loss in the delay lines. As mentioned in the above section, lower speed implementations (e.g., 10 Gb/s) require longer delay lines (∼7.2 mm at 10 Gb/s), and hence, suffer higher propagation losses. Figure 1 also shows the Ge-on-SOI PD schematic with its capacitance (CPD) and series resistance (RPD), as well as its on-chip biasing capacitor (CG). The biasing capacitor facilitates the application of an on-chip DC reverse bias voltage, simplifying the test circuit [10]. The PD has an 8 μm × 20 μm surface area and a 500 nm thick Ge-layer over a 19 μm × 24 μm SOI passive waveguide area. The biasing capacitors for all the four PDs have a 470 μm × 700 μm surface area. Each PD exhibits a bandwidth of ∼25 GHz with a reversed bias voltage of 4 V and a responsivity of ∼0.7 A/W. From the I–V characteristic of the PD, the measured dark current is approximately 1.5 μA with a reverse bias voltage of 4 V. By fitting the forward bias region of the I–V curve to a linear model at 0.8 volt, we estimated the PD resistance (RPD) to be approximately 110 Ω. Detailed characterization of the PD with an on-chip capacitor can be found in [11].
Fig. 1 Schematic of the sampling PD architecture for 20 Gb/s data rate, inset shows the detailed schematic of the PD layout. GC: grating coupler, DC: directional coupler, G: ground pad, S: signal pad. Different coupling lengths (L1, L2 and L3) are used in the directional couplers to maintain uniform power distribution among all the four PD channels.
2.1. Design method for the delay waveguides
To implement one bit delay using a typical single mode 220 nm × 500 nm cross-section SOI waveguide, we designed the delay lines in compact rectangular spirals to reduce the footprint. The minimum bend radius of the delay lines is 20 μm. Simulations and experimental results suggest that with a 20 μm bend radius, the mode mismatch loss is reduced below 0.015 dB [12] in a 220 nm × 500 nm cross-section SOI waveguide. In another variation, to reduce the propagation loss in the delay lines, we choose a 220 nm × 3 μm cross-section area ridge based SOI waveguide with a 90 nm slab. The low-loss SOI waveguides have higher bending losses due to their ridge-based structure; therefore where bends are required, we used the 220 nm × 500 nm cross-section SOI waveguide with a 10 μm bend radius. The two types of waveguides are connected by a 200 μm long taper such that only the fundamental mode is excited in the 220 nm × 3 μm multimode SOI waveguides [13]. Figure 2 shows the delay waveguide structure and their geometry (not to scale).
Fig. 2 Schematic of the (a) typical 220 nm × 500 nm cross-section and (b) 220 nm × 3 μm cross-section low-loss SOI waveguide, (c) low-loss SOI waveguide at the routing/bending region (top view), (d) actual layout of the rectangular shaped ∼7.2 mm long delay line with the typical 220 nm × 500 nm cross-section SOI waveguide for the 10 Gb/s optical front-end.
We performed 2D FDTD simulation to determine the group index of both types of SOI waveguides in the wavelength range from 1500 nm to 1600 nm [Fig. 3]. Figure 3 shows that the group indices for wavelengths around 1550 nm for the 220 nm × 500 nm and the 220 nm × 3 μm cross-section SOI waveguides are approximately 4.18 and 3.71, respectively. We used these values for the group indices to calculate the length of the delay waveguides to produce one bit delays in both types of the devices.
Fig. 3 Variation of the group index as a function of wavelength over the range from 1500 nm to 1600 nm for the (a) typical 220 nm × 500 nm cross-section and (b) 220 nm × 3 μm cross-section low-loss SOI waveguide, inset: shape of the fundamental mode inside each of the waveguide cross-section area.
The length of the delay waveguides and the loss per channel for the four different optical front-ends reported here are summarized in Table 1 of section 2.2.
Table 1. Projected loss in the photoreceivers
2.2. Design of the 1 × 4 optical splitter with simultaneous 1 bit optical delay
Three directional couplers with different coupling ratios compensate the loss exhibited by the delay waveguides as well as uniformly distribute the optical power over four PD channels in each sampling photoreceivers [Fig. 4]. In the following, we will demonstrate how the losses of the delay lines impact the tolerance on the coupling ratio required to implement the receiver functionality.
Fig. 4 Schematic of the passive section of the time sampling photoreceivers with the directional couplers.
Figure 4 shows the three directional couplers with their cross (r1, r2, and r3) and through (1−r1, 1−r2, and 1−r3) power coupling ratios. To achieve uniform optical power distribution (i.e., Pout,1 = Pout,2 = Pout,3 = Pout,4), it is necessary that the power coupling ratios of the directional coupler are as follow, where ‘L’ denotes the total propagation loss coefficient in a delay waveguide.
In Eq. (1), the total propagation loss coefficient in the delay waveguide can be calculated as: , where loss = 2 to 3 dB/cm for the 220 nm × 500 nm cross-section SOI waveguide [12] and loss = 0.1 to 0.2 dB/cm for the low-loss 220 nm × 3 μm cross-section SOI waveguide, and l is the length of the delay waveguide in cm. In [13], the reported propagation loss is 0.026 dB/cm for a 300 nm × 3 μm cross-section SOI waveguide. We measured higher propagation loss in the 220 nm × 3 μm cross-section SOI waveguide (0.17 dB/cm). These higher propagation losses might be caused by the tapers added to transition to narrower waveguides before and after the bends, the propagation in the narrow bended waveguides, and the different waveguide thickness (220 nm here vs 300 nm in [13]). Figure 5 shows the variation in the power coupling ratio (r) for different values of propagation losses in the typical 220 nm × 500 nm cross-section SOI waveguide. A different slope is observed for the coupling ratio r1 because the optical power is coupled from the bottom arm of the directional coupler, whereas in the other two directional couplers (r2 and r3) the optical power is launched from the upper arm [Fig. 4]. In all three directional couplers, the power coupling ratios are calculated such that uniform power distribution is achieved in both the 10 Gb/s and 20 Gb/s time sampling photoreceivers. As expected, due to the use of longer delay line in the 10 Gb/s sampling photoreceiver, the variations of the cross-coupling ratio across the couplers are larger to account for the higher propagation losses. Thus, it is important to consider the propagation losses when designing the power coupling ratio of the directional couplers. Moreover, the performance of the technology used to implement the receiver must be taken into account since in SOI waveguides, loss is affected by scattering caused by the sidewall roughness, which is a parameter dependent on the fabrication process. For this work, we choose the coupling ratio parameters assuming a waveguide propagation loss of 2.5 dB/cm for the typical 220 nm × 500 nm cross-section SOI waveguide fabricated through IME-A*STAR in Singapore.
Fig. 5 Variation in the required cross-coupling ratio for different propagation losses in 220 nm × 500 nm cross-section SOI delay waveguide for directional coupler 1 (r1), 2 (r2) and 3 (r3), respectively.
In the photoreceivers with the low-loss SOI waveguides, the changes in the required cross coupling ratio becomes less sensitive to variations in propagation losses, as shown in Fig. 6. Therefore, sampling photoreceivers with low-loss waveguides are more robust to fabrication process variations. Here, the optical power is launched from the top input arm in the three directional couplers thus all the slopes are the same. In addition to the propagation losses, we consider the bending losses and the tapered waveguide losses during the directional coupler optimization. Thus, we assumed a 0.2 dB/cm propagation loss in the one bit delay waveguides with the wider cross-section.
Fig. 6 Variation in the required cross-coupling ratio for different propagation losses in 220 nm × 3 μm cross-section SOI delay waveguide for directional coupler 1 (r1), 2 (r2) and 3 (r3), respectively.
We determine the theoretical propagation losses per channel and the power coupling ratios of the directional couplers [Figs. 5 and 6] using Eq. (1). Table 1 lists the length of the delay waveguides and the estimated propagation losses per channel for the four sampling photoreceivers presented in this article.
We use a 90 nm slab loaded ridge based SOI waveguide to implement the directional couplers. In all the directional couplers, the gap between the two waveguides in the coupling region is fixed to 200 nm and the bending radius at the beginning and the end is set to 20 μm. The method used to design the slab loaded ridge waveguide based directional couplers is detailed in [12]. Table 2 lists the coupling lengths of the directional couplers for all the sampling photoreceivers presented in this article.
Table 2. Directional coupler geometries in different time sampling photoreceivers
3. Time-sampling photoreceiver data recovery principle
From the optical front-end of the time sampling photoreceiver, four optical signals are converted into electrical signals. Due to the one bit delay lines, the four electrical signals from the PD channels are delayed from each other by one bit. After the O/E conversion, the voltage of each of the four electrical signals accumulates over every period of four bits through a capacitive load (CLOAD) in the electronic circuit front-end model [Fig. 7(a)]. The voltage signal accumulation process in the capacitive load (CLOAD) is presented in detail in section 3.1 below. After each period of four bits, the accumulated signal at point ‘A’ is sampled at 1/4th of the data rate and processed by an analogue-to-digital converter (ADC). The load capacitor (CLOAD) voltage is then reset to zero. To overcome the challenge of a high-speed reset, two capacitive loads (CLOAD) operate in switched capacitor mode [14, 15] such that over every period of four bits, one of the capacitors accumulates charges while the other one is discharged though a switch (SW). The process is shown in Fig. 7(a). When CLOAD,1 accumulates charge, switches labelled SW1, , SW2 and are in off (open), on (close), on (close) and off (open) states, respectively. In this switching state, CLOAD,2 is discharged through SW2. Over the next four bits duration, opposite switching conditions occur (i.e., SW1, , SW2 and are in on (close), off (open), off (open) and on (close) states, respectively). In this configuration, CLOAD,2 accumulates charges and CLOAD,1 is discharged through SW1. The four streams of symbols are digitally processed at 1/4th of the data rate to generate the original input bit stream. Depending on the sequence and value of the four bits, each sampled symbol can be normalized to one of five possible levels (i.e. 0, 0.25, 0.5, 0.75, 1). A 3 bit ADC can be used to pass the 5 level symbols generated from each of the PD channels simultaneously to the digital signal processing (DSP) blocks, i.e., to an adder-subtractor. Indeed, the five possible levels for symbol represent a 5-level polybinary sequence [16] that is generated at the receiver end in this work, whereas the transmitted signal is still on-off keying (OOK) data. In optical transmission networks using polybinary coding, polybinary symbols are generated either at the transmitter or receiver end, but in both cases the post-processing electronic circuit (i.e., ADC and DSP blocks) at the receiver needs to operate at the original bit rate. The post-processing electronic circuit cannot operate at the reduced symbol rate because each polybinary symbol essentially carries only one bit of information [16]. In [17], 10 Gb/s 5-level polybinary format optical signal transmission is experimentally demonstrated, where the polybinary symbols were captured using a 13 GHz digital sampling scope. In our work, the simultaneous generation of four symbols at the receiver allows the ADC and post-processing DSP blocks to operate at only 1/4th of the data rate.
Fig. 7 (a). Proposed front-end of one of the four PD with post electronic circuit model. (b) Average value of 4 bits is sampled by four samplers at 1/4th data rate and sent to the ADC and DSP blocks for post processing.
The following algorithm is implemented to recover the original bit stream. At every sample point ‘m’, which is taken over 1/4th of the data rate, each PD channel generates a 3 bits sequence with a voltage corresponding to one of the five possible normalized levels mentioned above, representing the accumulated received power over that interval. The symbols from each PD channel are aggregated into a data segment that is then processed by solving four linear equations using simple adder-subtractor blocks. Equation (2) shows the general expression of the accumulated photodetected signal from each of the four PDs at ‘m’ sampling interval, where x(M − i) is the voltage build-up across CLOAD for every input bits (or photocurrent ‘I’), ‘i’ is the bit sequence and ‘M’ is ‘4m’.
From Fig. 7(b) it is seen that the four symbol data segment (D1, D2, D3 and D4 generated from the four PDs, s = 1, 2, 3, and 4, respectively) in Eq. (2) contains information about 7 consecutive unknown input bits from x(M) to x(M − 6). However, at the first sampling point when m = 1 (or M = 4), three of the 7 input bits (x(0), x(−1), and x(−2)) are equal to zero. These three zero bits actually come from the idle time segments in the 2nd, 3rd and 4th PDs for the first four input bits due to the one bit delay lines following the 1st PD implemented in the optical front-end, which sets the initial condition of this algorithm. Therefore, from the first sampling point (m = 1 or M = 4), it is possible to deduct the initial four unknown input bits from the four symbol segment or four equations. Now, in the subsequent iterations, the three extra input bits are known from the previous iteration, and thus four new unknown input values can be found. In a digital signal processing circuit, these operations will require three adder blocks and six subtractor blocks (see Fig. 8).
Fig. 8 Block diagram of the digital signal processing method to recover the original input bit stream from the sampled signal.
From Fig. 8, it is seen that if an error occurs in the bits of the previous symbol (i.e., in x(M−4), x(M − 5) or x(M − 6)), then the error will propagate in all subsequent bits. To prevent this, the original electrical input bits (a(M)) at the transmitter should be precoded into the binary sequence (x(M)) using the same algorithm developed for polybinary signal transmission networks [16, 17]:
After the 5 level symbols generated from ADC, the original input bit streams can be recovered using modulo-2 operation on the symbols by digital signal processing blocks:
It should be mentioned that the optical and analog electronic front-end proposed in this work can be used on the 5-level symbols generated to recover the original input bits from the precoded binary streams. Precoding of the input electrical bits is done at the transmitter before optical modulation, and a modulo-2 operation on each of the symbols is performed by the DSP blocks. In this work, we validated the concept of detecting the OOK data at 1/4th data rate by processing the received data offline using the DSP blocks as shown in Fig. 8. The input bits were not precoded in this initial demonstration to simplify the transmitter implementation.
3.1. Voltage signal accumulation in the capacitive electronic circuit model
In this section, we analyze the voltage signal accumulation process in the capacitive load of the electronic front-end model. The RC bandwidth of the electronic front-end is much lower than the actual data rate of the input signal as the post processing circuit (ADC and the DSP blocks) operates at 1/4th of the input signal data rate. Therefore the values of ‘RLOAD’ and ‘CLOAD’ can be chosen such that RLOADCLOAD ≫ Tb, where Tb is the one bit period of the input signal. We have found that this also facilitates voltage build-up across the load capacitor (CLOAD) for every input bit ‘1’, whereas the accumulated voltage in ‘CLOAD’ remains stable or unchanged for the input bit ‘0’. For RLOADCLOAD ≫ Tb, the incremental voltage across ‘CLOAD’ from its initial voltage ‘V0’ can be approximated as the following:
From Eq. (5) it is seen that if ‘RLOAD’ can be chosen such that IRLOAD ≫ V0 or I ≫ V0/RLOAD then the discharge in voltage (when input bit is ‘0’) from the load capacitor (CLOAD) is negligible compared to the voltage accumulation (when input bit is ‘1’). To confirm this, we simulated the electronic front-end model with the Cadence circuit simulation software for a 20 Gb/s input data rate. For these simulations, we chose a parasitic resistance, RPD = 110 Ω, and a capacitance, CPD = 66 fF (extracted from Sentaurus device and HFSS simulations) for the designed photodetector. The values of RLOAD = 1 KΩ and CLOAD = 2 pF are chosen such that about 10 mV is accumulated across ‘CLOAD’ after one bit period for an input bit value of ‘1’ or an input photocurrent of I = 0.4 mA (considering −2.4 dBm optical input at the PD of responsivity 0.7 A/W).
Figure 9 shows the accumulated voltage across the load capacitor (CLOAD) after 4 bits for the two cases out of total 24 = 16 possible cases. From Fig. 9 it is seen that the voltage discharge from the load capacitor for one ‘0’ bit or three consecutive 0’s is less than 0.5 mV. In section 4, we will show that the original input bits can be recovered using this circuit model within these voltage discharge limits.
Fig. 9 Voltage signal accumulation across the load capacitor for two types of input bit streams (a) ‘1000’ and (b) ‘1010’.
4. Experimental demonstration and results
To verify that we achieve uniform optical power distribution over the four PD channels (Ch-1 to Ch-4), we designed passive test structures for the 10 Gb/s and 20 Gb/s optical front-ends. These test structures do not include the PDs and, therefore, allowed us to measure the average optical power over the four channels using the on-chip output grating couplers. Here, we describe the test result for the 10 Gb/s passive optical front-end, which incorporates longer delay line compared to the 20 Gb/s front-end.
A continuous wave (CW) signal with an optical power of 3 dBm is tuned over the wavelength 1535 nm to 1575 nm and connected to a polarization controller (PC). At the output of the PC, the measured optical power is around ∼ 2 dBm. Then the polarized CW optical power goes to the input grating coupler (GC) of the test device [see Fig. 4]. The output optical power is measured at each of the four output channels using an optical power meter. In addition, we recorded the optical power transmitted through a test GC pair (connected by a straight waveguide), and then used the results to normalize the output power of the test device. Figure 10(a) shows the optical transmission response of the four output channels and the GC pair. From this figure it is seen that the total coupling in and out (GC pair loss) loss is around 9.5 dB (2 dBm – (−7.5 dBm)) at a wavelength of 1550 nm. Figure 10(b) shows the normalized transmission response of the four channels, with the optical loss per channel around 10 dB near 1550 nm. The 10 dB channel loss includes the inherent 6 dB loss due to the one to four power splitting ratio from the input to the output channels. The extra 4.2 dB loss per output channels can be explained as follows. Each 100 ps delay line is ∼ 7.2 mm long. Therefore, Ch-1 has no loss (it does not include any delay waveguide in its optical path) and Ch-2 suffers (7.2/10) cm × 2.5 dB/cm = 1.8 dB loss. Then Ch-3 and Ch-4 suffer 3.6 dB and 5.4 dB loss, respectively. However, as mentioned before, the coupling ratios of the directional couplers are designed to compensate the extra delay waveguide loss suffered by Ch-2, Ch-3 and Ch-4 to ensure that all channels have an equal propagation loss. Therefore, because of the delay waveguides each channel suffers an extra loss of approximately 3.2 dB (calculated using Eq. (1)). Hence, the total loss for each channel should be 6 + 3.2 dB = 9.2 dB by design (see Table 1). This predicted value is very close to the measured results [Fig. 10(a)] that show a loss per output channel of 10 dB. The additional 0.8 dB loss can be attributed to the directional coupler and bending waveguide losses. From Fig. 10(b) it is also seen that the loss variation across the four channels is less than 0.3 dB. It should be noted that without the power compensation obtained by engineering the coupling ratio of the directional couplers the loss difference between Ch-1 and Ch-4 would increase to 5.4 dB.
Fig. 10 (a) Optical transmission response of the four output channels and grating coupler pair, (b) Normalized optical transmission response of the four output channels by grating coupler pair response.
Table 3 summarizes the experimental value of the propagation losses per channel for the four sampling photoreceivers presented in this article. From the experimental result listed in Table 3, it is seen that for each of the four optical front-ends, variation in the output optical power over the four channels is below 0.3 dB. Moreover, all the measured losses are within 1.0 dB of the projected losses listed in Table 1.
Table 3. Measured optical loss per channels in the photoreceivers
Next, we measured the bit error rate (BER) of the PD channels for all four optical front-ends. Figure 11 shows the experimental setup. A CW laser source emitting at a wavelength of 1550 nm and with an output power of 8 dBm is injected into a commercial LiNbO3 Mach-Zehnder modulator (MZM). A PRBS bit pattern of length 231 − 1 of non-return to zero (NRZ) on-off keying (OOK) electrical data generated from a pulse pattern generator is used to drive the modulator. The MZM has an insertion loss of around 7 dB. To compensate this loss an EDFA with a noise figure (NF) of 5 dB is used before the device under test (DUT).
Fig. 11 Experimental setup to measure BER and capture the PRBS data from each of the four PD channels. EDFA: Erbium doped fiber amplifier, PM: power meter, DCA: digital communication analyzer.
Figure 12 shows eye diagrams and peak-to-peak voltages recorded for every PD channels for each of the four optical front-end variations for equal received average optical power. From this figure, it is seen that the peak-to-peak output voltages of the optical front-end with low-loss delay waveguides are higher compared to the optical front-ends with typical 220 nm × 500 nm cross-section SOI waveguides.
Fig. 12 Electrical eye diagrams obtained for each of the four channels for the (a) 10 Gb/s, (b) 20 Gb/s, (c) low-loss 10 Gb/s and (d) low-loss 20 Gb/s time sampling optical front-end variations.
To measure the BER of the four PD channels of the optical front-ends, we use an off-chip post electrical amplifier to increase the peak-to-peak electrical signal voltage up to 60 mVpp such that the output signal is above the sensitivity limit of the BER tester (10 mVpp for the Anritsu MU181040A-002 error detector) for the minimum received optical power. Figure 13 shows the BER versus average received power for the 20 Gb/s optical front-end with the typical and the low-loss delay waveguides. The average optical received power was measured at the input of the optical front-end and then adjusted to take into account the 4.75 dB loss caused by one grating coupler. From this figure it is seen that the 20 Gb/s optical front-end with low loss delay waveguides has a better sensitivity (∼1.6 dB at 1 × 10−10 BER) than the 20 Gb/s optical front-end with typical 220 nm × 500 nm cross-section SOI waveguides.
Fig. 13 BER as a function of the average optical power at the input (i.e. after the grating coupler) of the 20 Gb/s time sampling optical front-end for all the 4 channels, (a) front-end with the typical 220 nm × 500 nm cross-section SOI waveguide and (d) front-end with the low-loss 220 nm × 3 μm cross-section SOI waveguide.
Next, to recover the original input bit stream at 1/4th of the data rate, we captured and stored the 1 bit delayed 215 − 1 PRBS data generated from each of the four channels, which for this demonstration are then further processed offline using the principle described in section 3 [see Fig. 7]. Here, a 215 − 1 PRBS bit stream is chosen instead of 231 − 1 PRBS such that the data can be saved within the memory limit of the DCA. Figure 14 shows a specific segment of the captured bits for all the four channels of each of the optical front-ends. From this figure it is seen that, one bit delay of ∼100 ps and ∼50 ps is obtained for the 10 Gb/s and 20 Gb/s optical front-ends with the 220 nm × 500 nm cross-section SOI waveguide. This accurate one bit time delay was expected from both components, as it is seen from the simulation result in Fig. 3 that the group index of the silicon waveguide varies by only ∼0.01 over the wavelength range from 1500 nm to 1600 nm. This variation of group index can induce only 0.24 ps delay mismatch in the 7.2 mm long one bit delay lines used in 10 Gb/s optical front ends. The low bandwidth post processing electronic circuit is transparent to this small value of time delay offset. However, in the 10 Gb/s and 20 Gb/s optical front-ends with low-loss SOI waveguides, there is a ∼7 ps and ∼3 ps offset from the exact one bit delay between two successive channels. The time delay offset occurs in the low-loss optical front-ends due to the use of waveguide tapers in the bending regions and the comparatively large wavelength dependence of the group index (group index varied by ∼0.04 over the wavelength range from 1500 nm to 1600 nm, Fig. 3(b)). It is difficult to calculate the resultant time delay because of the variation of the group index as a function of the width of the tapered waveguides (from 500 nm to 3 μm and vice versa). Using the experimental time delay values obtained with these first prototypes, in future fabrication runs the time delay offset could be eliminated. In this work, we find that in the presence of this time delay offset it is possible to recover the original bit streams by tuning the sampling time duration in the post processing electronic circuit. The captured data from the four channels shown in Fig. 14 were processed offline in MATLAB.
Fig. 14 One bit delay between the adjacent four channels for (a) 10 Gb/s, (b) 20 Gb/s, (c) low-loss 10 Gb/s and (d) low-loss 20 Gb/s time sampling optical front-end.
The captured bits are passed through a low pass filter circuit, modelled by RLOAD = 1 KΩ and CLOAD = 2 pF [see Fig. 7(a) in section 3]. The values of this resistor and capacitor were chosen such that the electronic front-end operates at 1/4th of the bandwidth of the respective data channels, as discussed in section 3.1. In this model, we are processing the data captured by the DCA, which is essentially a voltage signal detected with a 50 Ω load. In a complete implementation, the electronic front-end will receive the PD current first, which will be used to charge the capacitor (CLOAD = 2 pF) and the resultant voltage from the capacitor will be sampled by the ADC. In [18], we have demonstrated error free detection of a 20 Gb/s optical bit stream generated from the optical front-end with the typical SOI delay waveguides of 2.5 dB/cm propagation loss. In this demonstration, we choose the data captured from the 20 Gb/s front-ends with the low-loss SOI waveguide based delay lines as an example to validate the proposed concept. Figure 15 shows the cumulative voltage signal for every four bits from the charge storage mechanism of ‘CLOAD’ (voltage at point ‘A’ in Fig. 7) and the sampled voltage at every four bit time interval (voltage at point ‘B’ in Fig. 7) for the input bit stream generated from the 20 Gb/s front-end with low-loss 220 nm × 3 μm cross-section area SOI waveguide based delay line. The binary values of the input bit streams are also shown in Fig. 15 for illustration. As expected, the averaged signal at point ‘A’ increases for every input bit ‘1’ whereas it holds its previous value for every input bit ‘0’. It should be noted that for every input bit ‘0’, there is no noticeable discharge from CLOAD, as previously described in section 3.1. At every four bits interval the cumulative signal at point ‘A’ is sampled and the sampled values are processed offline in MATLAB to solve a set of four linear equations using the algorithm described in section 3. It is seen from Fig. 15 that the sampled signal values from each of the four channels (at point ‘B’ in Fig. 7) are unique, although they are derived from the same input bit streams which are delayed by one bit duration from each other. Therefore, the four sampled values at each sampling period form a set of unique symbols that can be mapped to the original input bit stream by solving the four linear equations, as stipulated in the algorithm described in section 3.
Fig. 15 Averaged and sampled signals from the input bit stream from (a) Ch-1 or PD-1, (b) Ch-2 or PD-2, (c) Ch-3 or PD-3, and (d) Ch-4 or PD-4 of the 20 Gb/s optical front-end with low-loss delay waveguide.
Figure 16 shows the regenerated original bit stream after solving the set of linear equation using the samples values at point ‘B’ in Fig. 7(a). From this figure, it is seen that all the bits in the 215 − 1 PRBS bit stream were regenerated accurately.
5. Discussion
The data rate of the optical receivers can be extended at a lower cost and with less complexity by using the methodology of the time sampling based optical front-end presented in this article. To increase the data rate of the photoreceiver, the bandwidth scalability of all the three important sections of the proposed receiver, i.e., optical front-end, analog RC front-end and post-electronic digital circuit must be considered. If higher speed PDs need to be integrated with the electronic circuit, then the wire bonding and bandwidth requirement on the electronic front-end can be relaxed by increasing the number of PD channels in the optical front-end. The optical loss per channel will increase in this case due to the large optical power-dividing ratio, whereas the delay waveguide loss will decrease due to the use of shorter one bit duration delay length waveguide at higher data rate. For example, if a 80 Gb/s data rate photoreceiver is achieved using the 60 GHz Si-Ge PD described in [6], then the same 5 Gb/s electronic front-end model presented in this article can be used, if the number of optical channels is increased from 4 to 16. However, the theoretical optical loss per channel would increase from 6.1 dB to ∼12 dB due to the 1 to 16 optical power-splitting ratio in this scenario. The analog part of the proposed electronic front-end model has a RC bandwidth of ∼80 MHz (RLOAD = 1 KΩ and CLOAD = 2 pF), which is much lower than the input signal bandwidth (∼14 GHz for 20 Gb/s data rate signal). A similar type of analog electronic front-end, which also does not require a TIA, is proposed in [7]. In this case the reported RC bandwidth of the circuit is ∼290 MHz (R = 2.2 KΩ, C = 250 fF), which is used to process a 24 Gb/s signal by using a different methodology than the one presented in that article. Therefore, in terms of bandwidth scalability of the whole receiver, the analog RC front-end does not impose any challenge. This facilitates simple and low-cost integration of optical and analog electronic front-ends by wire bonding. Incorporating tunable time-delay and/or couplers (either thermally or electrically) in the optical front-end section of the photoreceiver could make the proposed device more robust to fabrication process variations. The performance of the overall photoreceiver will improve by simultaneously tuning the optical time delay or the coupling ratio in the optical front-end and the sampling time duration in the electronic front-end. Recent progress in the silicon photonics fabrication process makes it possible to integrate thermally tunable delay-lines [19,20] and directional couplers [21] within SiP PICs. Integrating these components with the proposed photoreceiver can achieve accurate one bit time delay and proper coupling ratios in the directional couplers such that uniform output power is achieved over all the four PD channels in case of fabrication process variation.
In the electronic front-end of an optical receiver, the TIA is the most power-consuming component, and the power budget for the receiver must increase with the bandwidth of the TIA [4, 7]. Therefore, a TIA-less RC front-end, such as the one used in the proposed method, will lead to an overall more power efficient receiver architecture. In addition, since most of the post-processing is performed by a digital circuit, this receiver architecture can take advantage of the efficiency improvements offered by CMOS technology scaling [7]. The sensitivity of the electronic front-end could improve by replacing the passive RC circuit with a TIA. Nevertheless, the demonstrated optical front-end would require TIAs with a lower bandwidth than a conventional photoreceiver. Moreover, the need for TIAs with a smaller bandwidth will also reduce the integration and manufacturing cost of the receiver. However, the use of TIAs might not reduce the power budget of the receiver even with lower bandwidth of operation because the number of TIAs used in this approach scales with the speed reduction factor or number of PD channels in the optical front-end.
6. Conclusion
The error free detection of a 215 − 1 PRBS optical bit stream at 20 Gb/s data rate is demonstrated. The 20 Gb/s optical data detected by the optical front-end is processed offline by using a low bandwidth (∼80 MHz RC analog circuit and 5 Gb/s data rate post-processing digital circuit) electronic front-end model. The data reported here was obtained with an optical front-end with low-loss SOI delay waveguides but the proposed architecture is also compatible with standard SOI waveguides [18]. Simplified relation between the directional coupler power coupling ratio and fabrication dependent waveguide loss parameter is derived to achieve uniform power distribution across all the four output channels. This shows that optical front-ends with low-loss delay waveguides can be designed with relaxed coupling ratio. The experimentally demonstrated optical time sampling front-ends allow for the integration of high speed Si-Ge PDs with low cost and low-bandwidth electronic circuits. Therefore, the proposed architecture enables the utilization of the full bandwidth of high speed PDs while requiring TIAs and processing electronics that operate at significantly slower data rates. Harnessing the feasibility of one bit delay lines in optical domain leads to an overall low-power and low-cost photoreceiver architecture.
Acknowledgments
This work was supported in part by the Regroupement stratégique en microélectronique du Québec (ReSMiQ), Canadian Microelectronics Corporation (CMC) microsystems, Natural Sciences and Engineering Research Council of Canada (NSERC) and Canada Research Chair (CRC) in Photonic Interconnects program. The optical time sampling photoreceivers described in this work were fabricated by IME-A*STAR in Singapore through the services of CMC Microsystems.
The authors would like to thank Lukas Chrostowski, University of British Columbia, Vancouver, BC, Canada, Dan Deptuck, CMC microsystems, Kingston, ON, Canada and Christopher Williams, Concordia University, Montreal, QC, Canada for their useful discussions.
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