1. Introduction

Polycrystalline cadmium telluride (CdTe) solar cells have successfully entered the thin-film solar cell market because of their low production cost and high world record cell efficiency of 21.5% [1]. The CdCl₂ treatment, which usually involves deposition of a thin CdCl₂ layer followed by thermal treatment, is one of the most critical steps to achieve high-performance polycrystalline CdTe solar cells [2–5]. The CdCl₂ treatment, a so-called post-growth activation process, is known to affect both CdS and CdTe layers, where CdS which is a n-partner to CdTe acts as both window layer (E_g = 2.4 eV) and buffer for the growth of CdTe. The effects of CdCl₂ treatment— although still not fully understood—include recrystallization and grain growth, inter-mixing of the CdS and CdTe layers, enhancement of electrical properties, and passivation of grain boundaries [6–9]. Recent studies have shown that there are promising alternatives to CdCl₂, including MgCl₂, NH₄Cl, and NaCl that can overcome the toxicity and high cost of CdCl₂ [10,11]. Additionally, studies aimed at understanding the fundamental aspects of the activation process have been reported [12,13]. Li et al. reported enhancement of carrier collection at grain boundaries after CdCl₂ treatment that was caused by polarity inversion of the grain boundaries from p-type to n-type [12]. Although there has been an enormous effort to identify the scientific mechanism of the CdCl₂ treatment on the solar cell enhancement, several controversies still remain. Group VII elements, including Cl, are typical n-type dopants in a CdTe layer if Cl replaces Te. However, p-doping effects can also be realized, because shallow acceptor complexes such as (Te_i²⁻−Cl_Te⁺)⁻ and (V_Cd²⁻−Cl_Te⁺)⁻ can be generated after the CdCl₂ treatment [14].

CdTe has attracted great attention for applications such as photodetectors and x-ray detectors because of its high absorption coefficient and direct energy bandgap (~1.5 eV), which allow us to fabricate a UV-visible broadband photodetector with a thickness of a few micrometer [15,16]. Various CdTe structures, including thin films, nanoribbons, nanowires, and microwires, have been reported [15,17–19]. However, few studies about the effects of CdCl₂ treatment on the photodetecting performance of CdTe have been reported. In the work reported here, the effects of the CdCl₂ treatment on the electrical and optoelectronic properties of CdTe thin film-based photodetectors are investigated. Since grain boundaries are strongly affected by the activation process, polycrystalline CdTe thin films are a suitable structure to investigate the electronic and optoelectronic effects of the CdCl₂ treatment. Aga et al. reported that the highest photodetecting performance of CdTe-based devices was observed in materials that had the highest number of CdTe nanocrystals [15]. Higher carrier collection efficiency at the grain boundaries of CdCl₂ treated CdTe was reported compared to grain interiors [12,13,20]. The grain boundaries show less carrier collection at grain boundaries than the grains if the device does not receive the CdCl₂ treatment [12,13]. In this study reported here, patterned CdTe microstructures were selectively grown on graphene by the close-spaced-sublimation (CSS) method. Then, their electrical properties and photoresponse were systematically analyzed before and after the post-growth activation process on the CdTe thin-film/graphene field-effect transistor (FET)-type photodetectors.

2. Experimental details

Figure 1 shows a schematic of the device fabrication process. Graphene, grown by a chemical vapor deposition method on a Cu foil, was used as a seed layer for CdTe growth [Fig. 1(a)]. The transfer process for the graphene involved the following steps: coating with a poly(methyl methacrylate) (PMMA) layer, wet etching of the Cu foil, transferring the PMMA/graphene onto a SiO₂/Si substrate, and removing the PMMA layer. Then, a pattern was formed in the graphene by a standard photolithography process, including spin-coating of photoresist (PR), mask alignment, UV exposure, and development. The patterned graphene was defined by an oxygen plasma for 5 s (100 W, 20 sccm of O₂) (RIE 5000, SNTEK). Then, the remaining PR was removed with acetone. Defects in the graphene were generated by UV/ozone treatment (PSDP-UV4T, NOVASCAN) for 30 min in order to enhance its chemical reactivity. Then, CdTe was selectively grown on the patterned graphene by the CSS method in an Ar ambient for 5 min as shown in Fig. 1(b). The temperature of the CdTe powder and the substrate were 600 and 540 °C, respectively. The thickness of CdTe layer was about 4.5 μm. Transmission line measurement (TLM) patterns for (opto)electrical measurements were defined above the CdTe thin films by a photolithography process. Cu/Au (20/80 nm) and Ti/Au (20/80 nm) electrodes were deposited for source-drain and back-gate electrical contacts, respectively, as shown in Fig. 1(d). The details of the growth and fabrication processes for patterned FETs can be found elsewhere [21]. Post-growth CdCl₂ treatment was conducted after device fabrication: A CdCl₂ layer was deposited by dipping the CdTe-based FETs into a saturated solution of CdCl₂ (Sigma Aldrich Co.) in methanol (1.2 g/100 mL), followed by thermal treatment at 385 °C for 30 min [Fig. 1(c)]. Scanning electron microscopy (FE-SEM, S-4700, Hitachi) was used to examine the changes of surface morphology by the CdCl₂ treatment. The current-voltage (I-V) characteristics were obtained by using a semiconductor parameter analyzer (4155C, Agilent) connected to a probe station. The intensities of UV light were measured by a laser power meter (FieldMax II-TO, Coherent). The photodetection performance was measured using a 365-nm UV lamp (ULItec LTD.) and neutral density filters (10, 30, 50, and 70%, Optosigma).

 

Fig. 1 Schematic of the graphene-seeded fabrication procedure for the back-gated CdTe/graphene FETs: (a) graphene grown on Cu foil; (b) transfer of graphene onto a SiO₂/Si substrate and selective growth of CdTe thin films on graphene; (c) CdCl₂ activation process in furnace; (d) electrical measurement setup of the fabricated CdTe FETs.

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3. Results and discussion

SEM images of as-grown CdTe films on a graphene seed layer are shown in Fig. 2(a) and enlarged in Fig. 2(b); the presence of large grains (up to 5 μm) confirms the high quality of the polycrystalline CdTe layer. Figures 2(c) and 2(d) show the surface morphology of the CdTe after the CdCl₂ treatment. New and small surface irregularities, or “bumps,” were generated, which can be explained by strain relaxation [22,23]. The sharp edges of the grain boundaries became rounded. Also, the small gaps between CdTe grains were filled as shown in Fig. 2(d); this should improve the electrical properties of CdTe thin films because of enhancement of carrier transport through the grain boundaries [24]. No change was observed in photoluminescence spectra at room temperature and X-ray diffraction results (not shown).

 

Fig. 2 Top-view SEM images of the CdTe surface: (a, b) before CdCl₂ treatment; (c, d) after CdCl₂ treatment.

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The effects of the CdCl₂ treatment on the electrical properties were investigated by fabricating back-gated CdTe thin-film FETs. The I-V characteristics at different spacing between the TLM patterns, before and after CdCl₂ treatment, are compared in Figs. 3(a) and 3(b), respectively, where quasi-linear I-V characteristics were obtained. After post-growth CdCl₂ process, the currents increased by a factor of approximately 5, which is attributed to the passivation of the grain boundaries and the formation of shallow acceptors [14]. The relationship between the total resistance of the device (R_T) and the sheet resistance (R_Sh) can be determined by linear fitting of the following relationship: R_T = (R_Sh·L)/W + 2R_C, where L, W, and R_C are the channel length (10 μm), channel width (100 μm), and contact resistance, respectively. The average R_Sh was reduced from 1.09 × 10⁹ to 5.55 × 10⁷ Ω/sq. Also, morphological changes during the CdCl₂ treatment can be related to the enhancement of the electrical properties of the graphene-seeded CdTe thin films [24]. Improved I-V properties can be seen in the output characteristics of our CdCl₂-activated CdTe FETs with the 10 μm source-drain distance [Figs. 3(c) and 3(d)]; the source-drain currents (I_DS) decreased as the back gate-source voltage (V_GS) became more positive, which indicates p-type behavior of the semiconductor channel. Significant improvements of electrical properties are observed in the on/off ratio, field-effect mobility (μ_FE), and R_Sh after CdCl₂ treatment [Figs. 3(e) and 3(f)]. The average on/off ratio and μ_FE increased from 5.2 to 6.4 and from 0.025 to 0.20 cm² V⁻¹ s⁻¹, respectively.

 

Fig. 3 I-V characteristics from the TLM patterns: (a) before CdCl₂ treatment (inset: microscope image of TLM patterns), (b) after CdCl₂ treatment; I_DS-V_DS characteristics at varying V_GS from + 30 V to −30 V: (c) before CdCl₂ treatment, (d) after CdCl₂ treatment, (e) I_DS-V_GS characteristics and (f) summary of R_Sh, on/off ratio and field-effect carrier mobility before and after CdCl₂ treatment.

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The measurement setup for the photodetection experiments is depicted in Fig. 4(a). 365-nm UV light (3.4 eV) was used, which has a larger energy than the band gap of CdTe (~1.5 eV). The UV light was switched on and off repeatedly at 60 s intervals. A fast and reproducible photoresponse (τ_r1 = 0.79 s, τ_r2 = 11.0 s, τ_d1 = 1.34 s and τ_d2 = 17.3 s at V_GS = 0 V) was observed at various V_GS conditions [Fig. 4(b)]. The photoresponse was calculated by using the following relationship Photoresponse(%) = 100%·[I_DS(t)-I_DS(0)]/I_DS(0), where I_DS(t) and I_DS(0) are the source-drain current at a time of t, and the average dark current, respectively. The photoresponse increased as V_GS became more positive, which can be explained by the p-type behavior of the CdTe layer because the channel layer depleted under the positive gate bias, and is more sensitive to the photo-generated electron-hole pairs.

 

Fig. 4 (a) Schematic of the measurement setup for photoresponse, (b) time-resolved photoresponse at various V_GS when the UV light was repeatedly cycled on and off.

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To analyze the effects of the post-growth CdCl₂ treatment on the photoresponse of the graphene-seeded CdTe FETs, I-V curves at different light intensities were obtained [Fig. 5(a)]. Photocurrents increased with increasing light intensity because more photo-generated electron-hole pairs were created at higher light intensities. The time-dependent photoresponses are shown in Fig. 5(b). Our CdTe FETs show highly reproducible photodetection even at low light intensity (as low as 3.2 μW/cm²). In order to investigate the optoelectronic characteristics of our devices, time-resolved photoresponse curves were fitted to the following bi-exponential equation; I = I_o + C₁·e^(−t/τ1) + C₂·e^(−t/τ2) [Fig. 5(c)] [17]. The time constants for the rise and decay are denoted by τ_r and τ_d, respectively. After the post-growth CdCl₂ treatment, τ_r1 decreased from 1.23 s to 0.43 s, and τ_d1 decreased from 1.60 s to 1.06 s. However, τ_r2 increased from 13.0 s to 19.9 s, and τ_d2 increased 20.5 s to 24.4 s. We believe that the time constants (lifetime) can be improved by optimizing the device structure and the fabrication procedure. The responsivity (R) is defined as the photocurrent per unit incident light power, divided by the effective area of the device; R = I_photo/P·A, where I_photo is the photocurrent, P is the power per unit area of the incident light, and A is the effective area of the photodetector [17, 25]. R decreased with increasing light intensity because of saturation of carrier trapping and a reduction of the recombination barrier [17, 18]. The responsivity of our CdCl₂-activated CdTe structures after CdCl₂ treatment is approximately 264 A/W at a light intensity of 3.2 μW/cm². Photocurrent gain (G) is another criterion of photodetectors, which can be obtained by the following equation: G = (I_photo/q)/(P·A/h·ν) = σ/t_tran, where q is the elementary charge, hν is the photon energy, σ is the carrier lifetime, and t_tran is the transit time across the electrodes [17, 25]. The G of our CdCl₂-activated CdTe structures after CdCl₂ treatment is estimated to be 898 at a light intensity of 3.2 μW/cm². The values of R and G obtained in this work [Fig. 5(d)) are improved compared to the non-treated devices and much higher than previously reported values such as those for single-crystal CdTe nanowires (R ~80.1 A/W and G ~250) [18], kinked CdTe nanowires (R ~19.2 A/W) [26], and multi-step shaped CdTe nanowires (R ~153.7 A/W and G ~337.3) [27], except for CdTe nanobelts (R ~780 A/W and G ~2400) [17]. Enhanced photodetection characteristics such as rapid rise and decay time, and high responsivity are beneficial effects of the CdCl₂ activation process. This work is helpful to fabricated the graphene-seeded semiconductor structures and improve the optoelectronic performances of CdTe/graphene hybrid devices.

 

Fig. 5 (a) I-V characteristics (inset: an optical image of our fabricated CdTe photodetector with Cu/Au electrodes) and (b) time-dependent current characteristics under various UV light intensities, (c) close-up of the time-dependent current with experimental data and fitted curves at an intensity of 508 μW/cm², (d) responsivity as a function of light intensity (inset: photoconductive gain as a function of light intensity).

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4. Conclusion

We fabricated photosensitive CdTe/graphene hybrid FETs by using graphene seed layer. Electrical and optoelectronic properties of back-gated CdTe/graphene FETs were investigated before and after the CdCl₂ activation process. Morphological changes, such as bumps and rounded grain boundary edges, were observed after the CdCl₂ treatment. Electrical conductivity was dramatically enhanced due to the passivation of the grain boundaries and the p-doping effect. Improved electrical and photodetection properties of CdCl₂-activated CdTe films were observed, including sheet resistance, on/off ratio, field-effect carrier mobility, response time, and high responsivity; these results demonstrate the beneficial effects of CdCl₂ treatment for CdTe/graphene hybrid devices.