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Abstract
We demonstrate a fully integrated polarization-diversity 8 × 8 thermo-optic Si-wire switch that uses only a single path-independent insertion loss (PILOSS) switch matrix. All input/output ports of the PILOSS switch matrix are uniquely assigned for polarization diversity without switch duplication. To integrate polarization splitter-rotators on a chip, we propose a compact path-length-equalized polarization-diversity switch configuration. Polarization-dependent loss (PDL) and differential group delay (DGD) are minimized. The 8 × 8 switch is fabricated by the CMOS-compatible fabrication process on 300-mm diameter wafer and additional etching of upper cladding after dicing. The chip size is 7 × 10.5 mm2. A PDL of 2 dB and a DGD of 1.5 ps are achieved. The crosstalk in the worst-case scenario is −20 dB in the full C-band.
© 2017 Optical Society of America
1. Introduction
Dynamic and hierarchical optical switching has strong potential to achieve sustainable growth of traffic bandwidth in optical fiber networks, because the energy consumption of data switching is low when the data are aggregated [1]. The key device is a multiport-count strictly non-blocking optical path switch that meets the demands of cost and size. Photonic integration of the switch is likely. In particular, silicon photonics technology is expected to meet such demands of cost and size as a higher fabrication yield on a large silicon-on-insulator (SOI) wafer is achievable with a mature CMOS fabrication process. The chip size can be drastically reduced owing to the high optical confinement of Si waveguides. Recently, there have been several reports on multiport-count strictly non-blocking switches integrated on SOI wafers [2–7]. State-of-the-art silicon photonic switches based on CMOS and MEMS technologies achieve a port count of 32 × 32 [6] and 64 × 64 [7], respectively, on a small chip. However, input-polarization sensitivity is a practical issue of these silicon photonic switches.
There are two major approaches to solve this problem: one is to minimize polarization sensitivity by engineering the waveguide dimensions and the other is to employ polarization diversity. An 8 × 8 split-and-select switch with polarization-insensitive Si thick (1.5 μm) rib waveguides [8] and a silicon MEMS switch with polarization-insensitively designed MEMS-actuated couplers [9] were reported. However, the fabrication tolerance of waveguide dimension engineering is very low, particularly when Si waveguides are fabricated on submicrometer-thick SOI wafers. Nevertheless, the polarization diversity is promising in terms of fabrication yield while a pair of identical N × N switches is necessary. Recently, we have proposed a novel full-port use of a path-independent insertion loss (PILOSS) switch matrix that avoids the switch duplication in the polarization diversity. The polarization diversity with a single PILOSS switch matrix was demonstrated in a 4 × 4 Si-wire switch [10]. The 4 × 4 switch used external fiber-based polarization beam splitters (PBSs), and differential group delay (DGD) was not small enough for high-speed transmission without DGD compensation.
This paper reports a fully integrated polarization-diversity 8 × 8 Si-wire switch based on the full-port use of a PILOSS switch matrix. Polarization splitter-rotators (PSRs) [11] and a single thermo-optic 8 × 8 PILOSS switch are monolithically integrated on a chip. For the integration, we propose a compact and scalable polarization-diversity configuration where the lengths of the two diversity paths are exactly equalized on the chip. This equalization is essential for a low DGD as well as a low polarization-dependent loss (PDL). We fabricate the switch using our CMOS-compatible fabrication process on a 300 mm-diameter SOI wafer and additional etching of SiO2 cladding after dicing. The chip size is 7 × 10.5 mm2. The fiber-to-fiber DGD and PDL of the 8 × 8 switch are measured to be 1.5 ps and 2 dB, respectively. The crosstalk of the switch in the worst-case scenario is −20 dB in the full C-band. Following our first report on the fully integrated polarization-diversity switch [12], we provide here more detail on the design and performance.
2. Design and fabrication
We employ a PILOSS switch topology, which consists of 2 × 2 element switches [13]. For an N × N PILOSS switch, the element switches are arranged in an N × N square matrix. This single switch matrix operates as two synchronized N × N PILOSS switches when all switch I/Os are fully and bi-directionally used with a unique port assignment [10]. By utilizing the full-port use of the PILOSS switch matrix, polarization diversity, which conventionally requires two switch matrices, can be configured without duplicating the switch matrix. To achieve low PDL and DGD in the polarization diversity, the path length after polarization splitting must be equalized on a chip. However, the length equalization of access waveguides connecting the PBS to the PILOSS switch matrix is intricate since switch I/Os are located on both sides of the switch matrix. We propose compact and scalable arrangements of the access waveguides for the integration. Figure 1 shows the configuration of the compact path-length-equalized polarization-diversity 8 × 8 switch. The access waveguides are embedded into the PILOSS switch matrix. A path from the input port #3 to output port #6 is highlighted to show the operation. Input light is divided into orthogonal TE-like (dashed) and TM-like (solid) modes at the PBS. Only the TE-like mode is rotated to the TM-like mode with the following polarization rotator, and the light on both paths propagates through the 8 × 8 switch in the TM mode. The 8 × 8 switch was designed for the TM-mode in order to relax performance sensitivity to the gap of directional couplers used in the 2 × 2 element switch. In one of the diversity paths, the light first propagates through the switch matrix (left to right), and then it passes through the embedded access waveguides. In the other diversity path, the light propagates through the switch matrix (right to left) after passing through the access waveguides. The path lengths are precisely equalized for a low DGD as well as a low PDL. Moreover, the PBSs and polarization rotators are arranged symmetrically between the diversity paths: the TM and TE modes at the input are converted to the TE and TM modes at the output, respectively. This symmetric configuration counterbalances the residual PDL of fiber couplings.
Fig. 1 Schematic configuration of a non-duplicate polarization-diversity 8 × 8 switch with compact path-length-equalized waveguide arrangements.
We design the switch for a Si photonics fabrication platform on a 220-nm-thick SOI wafer. The cross-sectional dimension of the Si-wire waveguides is 430 × 220 nm2. The switch chip was fabricated by the combination of our CMOS-compatible process using ArF immersion lithography on a 300-mm-diameter SOI wafer and additional etching of SiO2 cladding after dicing. First, Si-wire waveguides with SiO2 cladding are fabricated, and then TiN micro-heaters and Al electric wiring are formed. Figure 2(a) shows the microscopic image of a 2 × 2 element switch, which consists of a thermooptic MZ interferometer and an intersection. The MZ interferometer is composed of two 3-dB directional couplers and two 100-μm-long microheaters on the arm waveguides. We numerically analyzed thermal diffusion of the microheater and designed the element switch such that direct thermal crosstalk between the microheaters was sufficiently suppressed. The intersection is based on adiabatic mode expansion [14]. The intersection exchanges the output ports of the MZ interferometer: the element switch is in the cross and bar states when the MZ interferometer is in the bar and cross states, respectively. When the PILOSS switch matrix is composed of the element switches, the port exchange contributes to a low crosstalk in a wider bandwidth for the following reason. The MZ interferometer has a low crosstalk in a wider bandwidth when it is in the bar state since the difference in the coupling ratios between the two 3-dB directional couplers is counterbalanced [15]. Hence, this output-port exchange improves the performance of the element switch in the ‘cross’ state. Any two paths on the PILOSS switch matrix never cross in the same propagation direction at the element switch in the bar state, and the performance of the element switch in the ‘cross’ state is only important for overall crosstalk.
Figure 2(b) shows the image of the PSRs. The PSR acts as a PBS and polarization rotator: TE-like input light is converted to that in the TM-like mode and emerges from one of the outputs, while TM-like input light is unchanged and emerges from the other output. The PSR is achieved with the combination of an asymmetric directional coupler and adiabatic taper waveguides [11]. The input TE-like (TE0) mode is coupled to the TE1 mode at the asymmetric directional coupler, and the TE1 mode is adiabatically converted to the TM-like (TM0) mode by propagating through the taper waveguide. The input TM-like (TM0) mode passes through the asymmetric coupler without coupling. To form vertical asymmetry, SiO2 upper cladding on the directional coupler is selectively removed by the combination of CHF3 dry and BHF wet etching.
Figure 3 shows a picture of the packaged non-duplicate polarization-diversity 8 × 8 switch and the microscopic image of the switch chip. The switch chip consists of 16 PSRs and an 8 × 8 PILOSS switch matrix. A path-length-equalized compact arrangement for the non-duplicate polarization diversity is employed. The chip size is 7 × 10.5 mm2. As shown in the picture, the switch chip was mounted on a chip carrier, and all 144 heater electrodes were wire-bonded to the mount. A fiber array was attached to the edge of the chip for optical inputs and outputs.
3. Results and discussion
3.1 MZ element switch and PSR
We measured the transmission characteristics of the MZ element switch with output-port exchange. Figure 4 shows the transmission spectra in the (a) cross and (b) bar states. In the cross state, the crosstalk or output at the non-target port is 30 dB lower than the transmission in the full C-band. On the other hand, in the bar state, it is approximately 20 dB in the C-band. The element switch in the cross state is only responsible for the crosstalk characteristics of the 8 × 8 switch since any two paths on the PILOSS switch matrix never cross in the same propagation direction at the element switch in the bar state.
Then, we measured the characteristics of the PSR. Figure 5 shows the transmission spectra when the inputs are in the TE-like mode (red curve) and TM-like mode (blue curve). The TE- and TM-like modes at the input are out both in the TM-like modes from the upper and lower outputs, respectively. The PDL of the PSR, which is defined as the difference between the two transmission curves, is less than 1 dB in the full C-band.
3.2 On-chip loss, PDL, DGD, and crosstalk of the 8 × 8 switch
We calibrated the non-duplicate polarization-diversity 8 × 8 switch and measured loss, PDL, and DGD. Figure 6 shows the on-chip loss of the switch at 1550 nm for all 64 paths. The on-chip loss, excluding the fiber-to-chip coupling loss of 10 dB for the input and output, is 30.9 ± 3.0 dB. The loss variation, which increases with the output port number, is caused by rotational misalignment between the fiber array and switch chip. From the measurement of test patterns, we broke down the on-chip loss of 30.9 dB as follows: 1.6 dB/cm × 1.9 cm = 3.0 dB for the access waveguides, 0.56 dB/unit × 8 = 4.5 dB for the element switches, 0.2 dB/unit × 52 = 10.4 dB for the intersections, 6.5 dB/unit × 2 = 13.0 dB for the PSRs. Accumulation of the losses of the intersections and PSRs are dominant. The intersection has been optimized for the TE mode, not for the TM mode, and further design optimization is feasible. We also expect loss reduction of the PSR by improving the design and fabrication process. The power consumption of the polarization-diversity 8 × 8 switch is approximately 0.6 W for any path connections when maximum eight paths are connected simultaneously on the switch. Figure 7 shows the (a) PDL and (b) DGD for sampled 24 paths from input ports #3, #5, and #7 to all eight output ports. The PDL, including the effect of fiber coupling, is approximately 2 dB in the C-band. The DGD is below 1.5 ps in the C-band. These low polarization sensitivities are achieved with the path-length-equalized arrangement of the non-duplicate polarization diversity. We estimate that the residual PDL is caused by characteristic variation of the PSRs and can be improved by using well-fabricated PSRs with the CMOS-compatible process.
We measured the crosstalk characteristics when all eight inputs were fully used. The crosstalk of a multi-port switch depends on the path connections. Here, we consider the worst-case scenario. The worst path connection can be discussed as is the case of a PILOSS switch without polarization diversity, because crosstalk dominantly occurs when two paths cross in the same propagation direction. The maximum number of path crossings at the element switch in the cross state and the intersection is N-3 and N-1 in an N × N PILOSS switch, respectively [16]. In the case of 8 × 8, one of the worst possible paths is (input port #, output port #) = (3, 2) when other path connections are (1, 8), (2, 6), (4, 4), (5, 3), (6, 5), (7, 1), and (8, 7). Figure 8(a) shows the path connections in the non-duplicate polarization-diversity 8 × 8 switch. The worst path of (3, 2) is indicated with blue line. The other seven paths (red paths) cross each diversity path of (3, 2) five times at the element switch in the same propagation direction (highlighted with gray color), which is considered to be the worst case in the 8 × 8 switch. We configured these path connections and measured the crosstalk of the worst path of (3, 2). Continuous wave light at the same power was launched into every input port one by one, and we measured output power at output port #2 for various wavelengths in the C-band. This measurement emulates the condition in which all the eight paths are simultaneously used with the same power levels. Figure 8(b) shows the transmission characteristics of the worst path of (3, 2) and the sum of leakages from the other seven paths at output #2. The crosstalk defined as the difference between them is approximately −20 dB in the full C-band. The bandwidth with −20 dB crosstalk is 4.5 times wider than that of our previous 8 × 8 Si-wire PILOSS switch [4], which consists of simple MZ interferometers without output-port exchange. The worst crosstalk is explained as accumulation of the crosstalk of the element switch and intersection. When the crosstalk of the element switch in the cross state and the intersection are −30 and −40 dB in the C-band, respectively, the worst crosstalk is calculated to be −19.8 dB, which agrees well with the experimental result.
Fig. 8 Crosstalk of the 8 × 8 switch in the worst-case scenario: (a) a switch state in the worst-case scenario, where path connections (input port #, output port #) are (1, 8); (2, 6); (3, 2); (4, 4); (5, 3); (6, 5); (7, 1); and (8, 7), and (b) measured crosstalk characteristics.
4. Summary
We have demonstrated a fully integrated non-duplicate polarization-diversity 8 × 8 thermo-optic Si-wire switch based on the full-port use of a PILOSS switch matrix. A novel path-length-equalized polarization-diversity configuration for the monolithic integration of a single 8 × 8 PILOSS switch and 16 PSRs was proposed and demonstrated. Not only the PDL, but also the DGD was minimized with the configuration. The PDL and DGD of the 8 × 8 switch were 2 dB and 1.5 ps, respectively. The crosstalk of the switch in the worst-case scenario was −20 dB in the full C-band.
Funding
Project for Developing Innovation Systems in Ministry of Education, Culture, Sports, Science, and Technology (MEXT), Japan, and Core Research for Evolutional Science and Technology (CREST) PMJCR15N6, Japan Science and Technology Agency (JST).
Acknowledgments
This work was supported by the Project for Developing Innovation Systems of MEXT, Japan. The development of PSRs was supported by CREST PMJCR15N6, JST. The main part of the device fabrication was performed by TIA Super Clean-Room of AIST. The authors thank K. Tashiro and T. Iitsuka for the fabrication of PSRs.
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