1. Introduction

Solid-state white lighting based on phosphor-converted blue III-nitride LEDs is among the fastest growing and highest wall-plug efficiency (WPE) white illumination technologies. The LED WPE is defined as the fraction of the input power that is converted to optical output power. State-of-the-art WPE values for commercial mid power blue LEDs are about 66% for an input current density J ≈35 A/cm² [1]. At this J, efficiency droop is a major factor limiting the efficiency. In commercial LEDs, the efficiency droop phenomenon is primarily caused by non-radiative Auger recombination, which is most probable when the active region carrier density is high [2–5].

LED manufacturers target device operation in the efficiency droop regime in a tradeoff to minimize cost by increasing the lumens produced per costly chip area. These tradeoffs and options to circumvent droop by operating blue emitters at either high or low current density have been discussed in [6,7]. As substrate, epitaxy, and fabrication costs have decreased in recent years, the thermal/mechanical/electrical components, including the heat sink, have emerged as the most expensive subsystem of most modern luminaires [1]. This trend may result in future cost optimizations that favor lower J and higher efficiency devices for illumination applications. Mid power luminaires can be realized by employing large arrays of high efficiency, low power LEDs, which has become viable for some applications. Additionally, diverse new applications are expanding for low power LEDs, such as in mobile, heads-up displays and virtual reality headsets.

In this article, we present a high efficiency design for blue LED device operation at low J ≈ 1 - 5 A/cm². This operating condition enables a re-optimization of the device design to increase the WPE by increasing its component efficiencies, especially the light extraction efficiency (LEE).

The WPE can be expressed as:

The voltage ratio V_p/V in Eq. (1) accounts for ohmic losses due to series resistance, which increase V compared to V_p. However, V also accounts for the promotion of carriers above the nominal band gap energy of the InGaN QWs due to thermal energy, which decreases V compared to V_p. Thus, it is possible for V_p/V to be greater than unity at finite lattice temperatures [8,9].

The product of IQE and LEE is the external quantum efficiency (EQE), expressed as:

The EQE is easily determined from spatially integrated electroluminescence (EL) measurements of the output power and the average photon energy. However, it is difficult to separate the IQE and LEE contributions to the EQE. The IQE can be modeled using the ABC model, but this requires knowledge of active region carrier densities during operation. Measurements based on variable-temperature luminescence intensity are useful for establishing an upper bound on the IQE, but the main assumption that the peak IQE = 100% at low temperature (e.g., ~10 K) is usually unjustified [11]. Other techniques involve calculation of the LEE and IQE by various methods, including using simple experimental structures for which the LEE can be computed analytically [12,13], or using ray tracing simulations to model more complex structures [14,15].

LEE estimates based on ray tracing simulations are very practical. Ray tracing uses the laws of geometrical optics to model the reflection, refraction, and absorption of light in large, heterogenous systems such as LED chips and packages. Ray tracing simulations, in addition to estimating the total LEE of a given structure, offer detailed insight into the loss mechanisms. A previously published LED ray tracing study identified that the main sources of loss in p-side up LEDs on patterned sapphire substrates (PSS) are the current spreading ITO layer, surface metal contacts, and rear metal reflector/heat sink [15]. We can use this knowledge to optimize designs toward higher efficiency.

In this paper, we discuss the opportunities to expand the design space for LEE optimization when operating nitride LEDs at low current density, e.g. J ≈ 1 – 5 A/cm². At this operating condition, LEDs may be designed with smaller metal contacts, thinner current spreading layer, and reduced or eliminated heat sink. Ray tracing simulations demonstrated that LEE ≈94% is viable for a low J design.

Operation at 1 – 5 A/cm² also creates opportunities to increase the other component efficiencies of the WPE: the IQE and V_p/V. The peak IQE of nitride LEDs generally lies within this J range, and thus efficiency droop losses can be minimized or eliminated. Finally, at these current densities, V is small for nitride LEDs, and it is common to observe V_p/V > 1. The gains from this term recoup some of losses from the IQE and LEE, enabling ultra-high WPE, which can theoretically [9,16,17] and experimentally [18,19] exceed 100%.

The high LEE design was realized with an experimental process and package, resulting in a best peak WPE of 78.1% for a blue (448 nm) LED, which was accompanied by V_p/V = 103%. The remaining sources of loss within the device are discussed and options are proposed for further optimization of low J devices.

2. Methods

2.1 Simulation methods

LightTools commercial ray tracing software package was used to calculate the LEE for full LED structures. Ray tracing simulations use the laws of geometrical optics to statistically simulate the behavior of light in systems with feature sizes larger than the wavelength of light in the materials.

A model of a reference PSS chip designed for mid power operation at input J ≈10 – 100 A/cm² (based on the one described in [15]) was compared to a low loss chip design for low J operation. Schematics of the two chip designs are shown in Fig. 1(a) and 1(b). The low loss LED takes advantage of the expanded design space at low J operation by reducing the thickness of the ITO current spreading layer from 250 nm to 30 nm and reducing the metal contact surface coverage by about 40%. The rounded and interdigitated contacts and rounded mesa in the low loss design shorten the distance between the p-contact and the mesa edge (< 40 μm) and make that distance more uniform across the chip to improve current spreading and avoid dim mesa corners, which have sometimes been observed experimentally for the reference chip. The low loss design also exchanged the backside silver reflector/heat sink in the reference design for a white, diffusely scattering reflector.

 

Fig. 1 Schematic of LED chip structures of (a) the reference PSS design similar to [15] and (b) the low loss PSS design for low J, using thin ITO, small contact surface areas, and a diffusely reflective header.

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Additional design improvements were made that can be applied to chips operating at any injection level. These included moving the large wire bonding pads off the mesa and away from the light-emitting area to reduce shadowing. An SiO₂ underlayer (assumed to be lossless) was placed beneath the metal pads to enhance their reflectivity. In the practical implementation of the design, the SiO₂ also prevents device shorting and assists with metal adhesion. The improved metal adhesion in turn enabled a switch to higher reflectivity Al contact metal compared to the Ti and Cr used in the reference design. The detailed device geometries and optical materials parameters used in the models are tabulated in the appendix.

Both designs were p-side-up chips on PSS with 0.1 mm² emitting area, a p-side ITO current spreading layer, and topside contacts. No light emission occurs directly beneath the n-contact as there is no hole injection there. The simulation assumed a hemispherical bump PSS at the sapphire/GaN interface. The bumps had radius r = 1.3 μm and height h = 1.3 μm with a hexagonal center-to-center spacing of 3.63 μm. The light source was modeled with a Lambertian emission pattern as a non-ray-traceable volume between the n- and p-GaN layers. Ultra-thin layers, such as the quantum wells and the electron blocking layer, were neglected, as was any refractive index difference among the undoped GaN, n-GaN and p-GaN.

2.2 Fabrication methods

This section describes the practical implementation of the low loss PSS LED design. Microfabrication masks were designed to match the mesa and contact design modeled with ray tracing simulations.

An optimal ITO layer is as thin as possible to minimize optical absorption, while still thick enough to ensure adequate current spreading. The optimal thickness depends on factors including the ITO and p-GaN conductivities, the intended operating J and temperature, and the maximum current spreading distance dictated by the contact design. A thickness series was performed to determine the minimum practical ITO thickness for room temperature operation at low J, on LEDs with the low loss design, which has a maximum p-side current spreading distance of 40 μm. Details of the optimization can be found in the appendix.

The results of the ITO thickness experiment and of the contact metal resistance and reflectivity development (also see the appendix) were used for the optimized microfabrication and packaging process. A 3-mask process was employed, beginning with a room-temperature, blanket e-beam deposition of 25 nm of ITO, which was annealed at 600 $ºC$ for 10 min in N₂/O₂ and then at 600 $ºC$ for 3 min in N₂. The mesas were fabricated with a self-aligned methane/hydrogen/argon reactive ion etch (RIE) of the ITO and a SiCl₄ RIE GaN mesa etch. The second mask defined the 300-nm SiO₂ insulating layer for the wire-bonding pads, which was fabricated by sputter deposition and liftoff. Finally, Al/Ni/Au contacts were formed with the third mask by e-beam deposition and liftoff.

The headers used for packaging the singulated LED die were dip coated in Avian B pre-mix (Avian Technologies), which is a white, BaSO₄-based, high reflectivity integrating sphere coating. Measurements with a UV/visible spectrometer confirmed a diffuse reflectivity > 98.5% at 450 nm for this material. Figure 2 shows the appearance of the headers before and after dip coating in Avian B.

 

Fig. 2 Photograph showing the difference in reflectivity between an uncoated silver header (left), versus a header dip-coated with Avian B, a diffusely reflective integrating sphere coating (right).

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The wafers were sawn, and the singulated LEDs were mounted on the headers with a small amount of Dow Corning OE6550 silicone encapsulant with refractive index 1.54. The LEDs were wirebonded using 25.4 µm diameter gold wire, and then fully encapsulated in the same OE6550 silicone.

The optimized process and package were used to fabricate samples for absolute WPE and EQE measurements using commercially supplied multi-quantum well blue-emitting (λ = 448 nm) LED epitaxial material grown on PSS. The measurements were conducted in a 500-mm diameter Instrument Systems ISP 500 integrating sphere equipped with an LED socket center post. The spectral data were collected with a calibrated Instrument Systems MAS 40 spectrometer. Measurements were performed at room temperature under DC operation.

3. Results and discussion

3.1 Ray tracing simulations

The results of the ray tracing simulations are shown in Table 1 (the dimensions and parameters used are given in Tables A1 and A2 of the appendix). The reference design gave a simulated LEE of about 79% with the dominant losses occurring in the ITO (≈7%), at the contact metals (≈6.5%) (especially at the p-metal, ≈5.5%), and at the backside silver mirror (≈3.5%). These results are similar to those previously reported for a similar structure [15]. The low loss design targeted these three highly lossy regions by thinning the ITO to 30 nm, reducing the contact surface areas, and replacing the silver mirror with a white diffuse reflector. These targeted changes were made in conjunction with general design improvements to increase the LEE. The changes resulted in a simulated LEE ≈94%. The largest improvements occurred in the targeted ITO layer, contact metals, and the silver mirror, in which losses were reduced by approximately 85%.

Table 1. Summary of the sources of optical losses in high LEE LED designs. The rightmost column calculates the relative change (Δ) in absorption in the low loss design compared with the reference design for each material in the epitaxy and package.

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The increased absorption in the n-GaN layer and the sapphire substrate is due to the larger volume of these regions in the low loss design, which has a larger overall die area (although nominally the same mesa area). The p-GaN layer, although identical in volume in the two structures, has less absorption in the low loss design because fewer rays are reflected back into the die from the topside contacts.

3.2 Integrating sphere measurements of WPE and EQE for a packaged device

Figure 3 shows the integrating sphere measurements of WPE, EQE and V_p /V of a device processed and packaged with the low loss design, using a commercial blue-emitting multi-quantum well (MQW) epitaxial wafer. The emitting area was 0.1 mm². The sample reached a peak EQE of 75.8% at 5.5 A/cm² and 2.71 V. The peak WPE was 78.1% at 3.45 A/cm² and 2.68 V. For a peak emission wavelength of 448.4 nm, this corresponds to a room temperature V_p/V = 103%. At this operating point, the LED produced 7.2 mW of power (7.2 W/cm² of output power density given the 0.1 mm² chip size).

 

Fig. 3 WPE, EQE, and V_p/Vas a function of current density (plotted on a logarithmic scale) for the low loss design, which was processed and packaged on blue-emitting MQW commercial epitaxial material. The peak WPE exceeds 78% at room temperature and is accompanied by V_p/V = 103%.

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LEDs can turn on at operating voltages below the photon voltage (V < V_p) due to the lattice thermal reservoir at finite ambient temperature, which provides the additional energy to promote carriers to the QW energy levels [8,9]. In commercial nitride LEDs, the voltage often remains below the bandgap value until current densities in the range of 3 – 12 A/cm² [20]. This allows for a peak WPE that exceeds the peak EQE, or in other words, where the voltage term recoups some losses in the EQE. Furthermore, at these operating conditions, LEDs still produce a useful amount of optical power as this example demonstrates.

The remaining EQE inefficiency in this device is split between the IQE and LEE. A different blue commercial MQW material grown on PSS that was evaluated during this study produced nearly as high of an EQE = 74.5% using the same process and package described here. Temperature-dependent EL measurements of this material showed a 9% reduction in peak intensity over a modest temperature range: 0 °C - 30 °C (see appendix), indicating relatively low IQE of the material. It is roughly estimated that the IQE of the best material that we used during this study was in the low 80% and that the actual LEE was within a few percent of simulated LEE in the low 90% range.

4. Conclusion

Only a few reports of > 80% WPE have been published for industry LEDs in the violet to blue wavelength range [21–23]. The best WPE achieved in this work was 78.1% using commercial blue MQW material and a low loss process and package designed for low J, low power operation. This design focused on improvements to the LEE, resulting in LEE ≈94% in detailed ray tracing simulations. Thermal pumping of the carriers was also readily observed at low J operation, resulting in the photon voltage exceeding the injected carrier voltage, V_p/V > 1 and enabling some of the EQE losses to be recouped. This is manifested in a peak WPE exceeding the peak EQE.

Further optimizations of the package design and materials may help to increase the LEE to the practical limit, including use of higher reflectivity metals, transparent (header-free) packages [24] and higher transparency ITO sources. Even more aggressive contact designs and packages can be envisioned to push the limits of the LEE.

More opportunities also exist in epitaxial material optimizations for low J operation. These may include removing heterostructures originally designed to mitigate efficiency droop (multiple QWs) or prevent carrier overflow (electron blocking layer). If these changes can be produced while maintaining exceptional material quality and injection efficiency (IQE > 90%), then ultra-high WPE becomes available, including the standing possibility of $\ge$ a 100% WPE blue LED.

Appendix

A.1 Simulation dimensions and materials parameters

Details of the LED design and simulation parameters are given in Table 2 and Table 3.

Table 2. Dimensions used in simulations for the reference (based on [15]) and low loss LED Designs. The layer dimensions are given by the surface area SA and thickness t, unless otherwise notated as values of the radius r, height h or fractional surface area coverage fsa. The fsa refers to the surface area coverage of the metal contacts divided by the mesa area of the chip.

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Table 3. Optical materials parameters used in the ray tracing simulations of the reference and low loss LED chip designs. Reflectivity values refer to the GaN/metal or GaN/dielectric interface.

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In the low loss chip simulation, interference effects in the ITO layer are neglected due to the small index contrast between ITO and GaN and thickness much smaller than λ/4n. Note that although the p-GaN layer is also thin, it is index-matched to the adjacent thick n-GaN and UID GaN layers so the effective feature size is the aggregate of those index-matched layers.

The fractional surface areas of the wire bonding pads are included for the p-metal and n-metal for the reference design, but not for the low loss design, in which the pads are far from the light emission area and are also optically isolated by a reflective SiO₂ underlayer.

A.2 Experimental optimization of the ITO thickness

The experimental ITO thickness series was performed on a c-plane LED wafer grown at UCSB on PSS. The sample was grown by MOCVD with 1 μm UID GaN buffer, 3 μm n-GaN, and a 30-period InGaN/GaN superlattice underlying a six-period MQW. The active region was followed by an AlGaN electron blocking layer (EBL), and 230 nm p-GaN, and capped with a p++ contact layer. The sample emitted light at 440 nm.

The wafer was quartered and processed with four ITO thicknesses: 0 nm, 33 nm, 70 nm, and 83 nm. The ITO was blanket deposited by heated substrate e-beam deposition [26], and the thicknesses were obtained by ellipsometry with a Woollam M2000DI Ellipsometer on co-loaded silicon monitors. The samples were co-processed for a self-aligned ITO MHA RIE etching followed by a Cl₂ inductively coupled plasma (ICP) GaN mesa etch. Then the dielectric insulator (SiO₂) was deposited by sputtering and metal contacts were deposited by e-beam evaporation.

The finished devices were imaged under electrical injection (EL) at 1 A/cm² (Fig. 4) to inspect the current spreading effectiveness of the respective ITO thicknesses. Fig. 4(a) shows inadequate current spreading in the absence of an ITO current spreading layer. The p-GaN conductivity alone is insufficient to provide current spreading across the 40 μm spreading distance. This results in luminescence clustered close to the p-contact and dimmer emission near the mesa edge.

 

Fig. 4 EL images of on-wafer LEDs with ITO thicknesses (a) 0 nm (b) 33 nm (c) 70 nm (d) 83 nm under 1 A/cm² injection. Images were all taken at room temperature with 1 ms integration time.

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Fig. 4(b)-4(d), however, all show adequate current spreading with the luminescence extending from the p-contact to the mesa edges without apparent reduction in intensity. In some places, especially evident in Fig. 4(b), the mesa edge is brighter than the region around the p-contact. This brightness cannot be explained by current crowding (which would follow the opposite trend), and thus these bright areas are attributed to edge roughness and the resulting higher local LEE. Images of the same die taken at 5 A/cm² (not shown) were qualitatively similar.

We also considered the effects of reduced ITO thickness on the electrical characteristics of the devices. Voltage measurements were taken on-wafer for 10 - 14 die on each of the four samples at a current density of 1 A/cm². Results are shown as a function of ITO layer thickness in Fig. 5.

 

Fig. 5 Voltage measurements for the ITO thickness series LEDs at an input current density of 1 A/cm². The data points are average values and the error bars represent +/− the standard deviation. The data set represents measurements of 10, 10, 14, and 11 LED die for the 0, 30, 70, and 83 nm ITO samples, respectively.

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For the range 33 - 83 nm, there may be a modest reduction in V with increasing ITO thickness due to the reduction in sheet resistance with increasing layer thickness. However, 0 nm of ITO resulted in much higher voltage, which accompanied the poor current spreading observed in Fig. 4(a). The voltages were high compared to commercial devices, but this is expected considering the similarly high indium dot test voltage for the unprocessed UCSB epitaxy (~3.7 V at 1 A/cm²) compared with that of typical commercial unprocessed epitaxy (~3.0 V at 1 A/cm²).

We conclude that even for low J operation, some ITO is required for current spreading, but as little as 33 nm was sufficient and performed similarly to a thickness of 83 nm at 1 A/cm². Additional refinements of this experiment (not shown) (1) resulted in an optimized ITO thickness of 24 nm and (2) improved the ITO wetting (and thus the uniformity of light emission) by changing the deposition method from a heated deposition to a room temperature deposition followed by a post-deposition anneal.

A.3 Optimization of contact resistance and metal reflectivity

The reference design and process led to microfabrication with lower reflectivity contact metals including the Ti n-contact and Cr p-contact because of their low contact resistance and adhesion property, respectively.

The n-contact used in the reference process was a Ti/Al/Ni/Au annealed contact. The annealed Ti produces an ohmic contact to GaN. This effect has been attributed to at least two origins: production of a low work function TiN semimetallic interfacial compound and the generation of donor-type nitrogen vacancies in the contact layer [27]. An annealed Ti contact was found to reduce contact resistance compared to unannealed contacts for the case of a moderate to low-doped n-GaN contact layer, which was etched with Cl₂ chemistry by ICP or RIE [28].

In the low loss design, the n-contact resistance was addressed by switching to a SiCl₄ chemistry in the RIE mesa etch, which has been shown to reduce contact resistance [29], attributed to its contribution of surface Si donor states. The use of this etch chemistry at UCSB [28] enabled a low contact resistance, unannealed Al n-contact.

The Cr p-contact used in the reference design was chosen for its better adhesion to ITO compared with higher reflectivity Al contacts, which tend to delaminate during wire bonding. In the low loss design, the adhesion issue was solved by using off-mesa pads electrically and optically isolated by a dielectric with either a SiO₂ or Al₂O₃ top layer, which both have sufficient adhesion to Al for wire bonding purposes.

Thus, Al/Ni/Au was adopted for both n-contact and p-contacts, eliminating a mask layer, a deposition step and an anneal compared with the reference design, while increasing adhesion and reflectivity, reducing absorption, and simplifying the wire bonding process. The measured reflectivities at 450 nm of the annealed Ti/Al/Ni/Au and Al/Ni/Au on c-plane GaN were 66% and 85%, respectively [28]. The parameters used in the ray tracing simulations of the previous sections were selected to match these measurements.

A.4 Temperature-dependent EL measurement for IQE estimation

Figure 6 shows measurements of the EL intensity for temperatures from 273 K to 303 K for an on-wafer die fabricated from commercial material. The EL intensity is reduced by about 9% from 273 K to 303 K. This indicates that the IQE is far-from-unity for this epitaxial material. This material reached a best peak EQE of 74.5% in the same process and package described in this work. This suggests that the IQE of the epitaxial material is a limiting factor for the overall efficiency.

 

Fig. 6 EL measurements show a reduction of EL intensity of 9% from 273 K to 303 K for a commercial blue epitaxial material. This indicates an IQE which is far-from-unity. This material produced a best peak room temperature EQE of 74.5%, compared to the best die from another commercial material (EQE = 75.8%).

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A.5 Estimation of the number of low loss devices required to produce powers relevant for illumination applications

This paper has described the opportunities in LEE and WPE enhancement by operation of nitride LEDs at low current density. The ideas presented may find use in many applications, especially those favoring operation under low power and high efficiency conditions, e.g. portable and near-eye displays. However, because of the perennial interest in LED use for general illumination, this section provides an analysis of the tradeoffs between output power and emission area for low current density operation.

According to [1], a typical commercial mid power blue (450 nm) LED operates at 350 mA/mm² and has a voltage of ~2.86 V and WPE of 66%. Assuming an emitting area of 1 mm², this corresponds to an output power of 660 mW for input power of 1000 mW.

If the low current density approach described here is to be applied to general illumination applications, then it must produce a total output power of similar magnitude by increase in emitting area. This means scaling the device size and/or increasing the device count.

The small-sized chip modeled and demonstrated in this paper was 0.1 mm² and produced a power of 7.2 mW at the peak WPE. Scaling LEDs to from small to large area generally results in a reduction in the LEE, as previously described [15,30] We can use Fig. 9.20 in [12] to estimate the reduction of LEE by scaling the device herein from 0.1 mm² to 1 mm². The figure shows that scaling the sidewall length from 350 to 1000 um, reduces the LEE by ~3%, and even less than that if the sapphire thickness is allowed to scale with the increase in sidewall length (thereby maintaining some of the sidewall extraction benefit). This reduces the WPE to about 75%. Then the 1 mm² chip would produce about 70 mW of output power, and it would take between nine and ten chips to produce the 660 mW output.

Put another way, if a set input power of 1000 mW is considered, about eleven 75% WPE devices would be employed compared with one 66% WPE device, and the 11-device array would produce 14% more output power for the same input power.

The trend toward lower per-emitter costs and expanding opportunities for LEDs in mid and low power applications as described in the introduction are promising for low current density devices.

Funding

Solid State Lighting and Energy Electronics Center (SSLEEC) at UCSB; UCSB nanofabrication facility, part of the NSF National Nanotechnology Infrastructure Network (NNIN) (ECS-0335765); UCSB Materials Research Laboratory (MRL) facilities, supported under the NSF MRSEC program (DMR-1121053).

Acknowledgments

The authors thank J. Nedy for consultations on the mask design, S.-H. Oh for assistance with packaging, and M. Piccardo for informative simulations.

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