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Abstract
Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an ION/IOFF ratio of more than 106 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.
© 2017 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
In recent years, remarkable progress has been made in the field of opto-electronic integrated circuits (OEICs) for various emerging applications such as optical interconnection, imaging, and bio-medical sensing [1–4]. Various approaches have been taken to integrate photonic and electronic devices on the common silicon (Si) platform to exploit the advantages of the well-established Si processing technology [5–7]. However, the lack of a laser source that can be monolithically integrated on Si substrate greatly limits the robustness and hinders the large-scale production of OEICs.
Towards this, great efforts have been made to realize Si and other group IV lasers, but this is very challenging due to the indirect bandgap of Si and germanium (Ge) [8]. Although electrically pumped Ge on Si laser has been demonstrated [9], the threshold current density is very high (280kA/cm2) as compared to III-V lasers. Very recently, direct bandgap GeSn lasers have been realized [10] on the Si substrate. However, only optically pumped lasers were demonstrated and lasing was only observed at low temperature ranges of 20 to 90 K. III-V compound semiconductors are the materials of choice for semiconductor diode lasers due to their direct bandgap which provides for efficient light generation [8]. Standalone III-V lasers on Si have been demonstrated by different wafer bonding methods [6, 11–13] and direct epitaxial growth [14–18].
To achieve large-scale monolithic opto-electronic integration and realize low cost and multi-functional OEICs, an attractive option could be monolithic integration of high speed metal-oxide-semiconductor field-effect-transistors (MOSFETs) and lasers on the Si substrate. InGaAs based nanopillars were grown on source/drain and gate regions of Si MOSFETs, and optically pumped lasing was realized [19]. OEICs require electrically pumped lasers that are integrated with electronic circuitry.
Furthermore, InGaAs n-FETs are among the most promising candidates for high speed and low power devices owing to their high mobility as compared to Si [20]. High performance InGaAs MOSFETs on Si substrates have been realized through various integration methods including wafer bonding, direct epitaxial growth, aspect ratio trapping, and confined epitaxial lateral overgrowth [21–24]. However, to the best of our knowledge, the monolithic integration of InGaAs MOSFETs and III-V lasers on Si has not been reported until recently [25].
In this work, we demonstrate InGaAs FETs and GaAs/AlGaAs lasers monolithically integrated on Si substrate as shown in the 3D schematic of Fig. 1(a). The high-quality layers for realization of InGaAs transistors and lasers [shown in Figs. 1(b) and 1(c)] were grown using molecular beam epitaxy (MBE) on Si substrate using Ge and GaAs buffer layers. The InGaAs FETs show excellent electrical characteristics with high ION/IOFF ratio and a low minimum subthreshold swing. Higher drive current can be achieved at a drain voltage which is ~0.5 V lower as compared to our previous work [25]. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers were also realized at room temperature. The full width half maximum (FWHM) of laser spectral response is less than 0.5 nm. The drain of the transistor is connected to the n-contact of the laser diode, as can be seen from Fig. 1(a).
Fig. 1 (a) 3D schematic of monolithic integration of a self-aligned InGaAs MOSFETs and top-top contact GaAs/AlGaAs QW laser on Si substrate. The drain of a multifinger transistor is connected to the n-contact of the laser. (b) Cross-sectional schematic of InGaAs MOSFETs with detailed layer structure and thicknesses along the line AA’ in Fig. 1(a). (c) Cross sectional schematic of GaAs/AlGaAs QW laser along the line BB’ as shown in Fig. 1(a).
2. Materials and electrical characterization
Firstly, high quality Ge was grown on a Si (100) substrate with 6° offcut towards (110). The Ge growth was done using a 3-step process starting from heavily doped Ge layer, gradually reducing the doping, and then finally the growth of unintentionally-doped Ge layer [26]. The threading dislocation density (TDD) achieved in this growth is less than 5 × 106/cm2. The III-V laser and transistor layers were then grown on the Ge-on-Si substrate. In order to suppress the formation of anti-phase boundaries (APBs) during the III-V (polar) growth on Ge (non-polar), the sample was first annealed at a high temperature of 650 °C in ultra-high vacuum environment. This helps to form double atomic steps on Ge. Low temperature migration enhanced epitaxy (MEE) at 300 °C was then used to grow 20 monolayers of GaAs. GaAs nucleation by low temperature MEE ensures good surface quality and also helps to reduce defects related to APBs. A 500 nm p+-GaAs (Be doped with NA = 5 × 1018 cm−3) contact was grown at 580 °C followed by 1 µm thick Al0.6Ga0.4As bottom cladding layer. The laser active region comprises a single GaAs/Al0.3Ga0.7As QW sandwiched in a graded-index separate confinement heterostructure (GRINSCH) AlxGa1-xAs layer with Al composition varying from 0.3 to 0.6 from the core towards the cladding. The intended thickness of GaAs layer is ~5 nm. A 1 µm thick Al0.6Ga0.4As layer was grown as the top cladding layer. A 200 nm n+-GaAs (Si doped with ND = 5 × 1018 cm−3) contact layer completed the growth of the laser structure.
This was followed by the growth of 800 nm graded InxAl1-xAs buffer with Indium composition increasing from 0.1 to 0.52. In0.52Al0.48As is lattice matched to In0.53Ga0.47As. Transistor layers were grown, including 15 nm In0.53Ga0.47As channel, 1 nm In0.52Al0.48As etch stop layer, and 25 nm n+-In0.53Ga0.47As cap layer (doping concentration of ~5 × 1018 cm−3). The top cap layer serves as the raised source/drain structure to achieve low source/drain series resistance.
The scanning transmission electron microscopy (STEM) image shown in Fig. 2(a) clearly shows all the layers on the Si substrate. InGaAs channel transistor layers can be seen on the top of GaAs/AlGaAs QW laser layers. Figure 2(b) shows the atomic-force microscopy (AFM) scan of the top n+-In0.53Ga0.47As cap layer with a scan area of 10 µm × 10 µm and gives a root-mean-square (RMS) surface roughness of ~3.47 nm. Figure 2(c) shows the photoluminescence (PL) spectrum obtained for the GaAs/AlGaAs QW measured at 25 °C, after etching away the transistor layers, laser top contact and cladding layers. The peak PL emission wavelength is 788 nm.
Fig. 2 Cross-sectional STEM image of the integrated sample with laser and transistor layers on the Si substrate using direct epitaxial growth by MBE. (b) AFM image of top n+-InGaAs surface showing small RMS roughness of 3.47 nm. (c) PL spectrum of the GaAs/AlGaAs QW measured at room temperature indicates peak emission wavelength of 788 nm and full width half maximum (FWHM) of PL spectrum response is 150 meV.
3. Integration of the transistor and lasers
Firstly, transistors were fabricated with a self-aligned gate using a metal-first process flow [27]. The sample surface was degreased using acetone, IPA, and de-ionized water, and then cleaned with dilute sulfuric acid solution (H2SO4:H2O = 1:10 v/v) to remove the native oxides. Around 50 nm Molybdenum (Mo) and ~20 nm Tungsten (W) were deposited on n+-InGaAs as the source/drain contact metal using sputter. Mo contact on n+-InGaAs is preferred due to low contact resistance and good thermal stability. The top W layer helps protect Mo from oxidation during metal dry etch. Silicon dioxide (SiO2) was deposited by electron beam (e-beam) evaporation to serve as the hard mask. Electron beam lithography (EBL) was used to define the transistor channel using poly methyl methacrylate (PMMA) as e-beam resist. Room temperature reactive ion etching (RIE) was done to etch SiO2 using CHF3-Ar plasma with PMMA as the hard mask. Source/drain metal in the channel region were etched using SF6/O2 based inductively coupled plasma (ICP) etching at high temperature of 200 °C with SiO2 as the hard mask. Etching stops selectively on n+-InGaAs. The n+-InGaAs layer was then completely removed in the channel region by wet etch using adipic acid solution (adipic acid:H2O2 = 50:6 v/v). The wet etch stops selectively at the InAlAs layer.
The sample was cleaned again in dilute sulfuric acid (H2SO4:H2O = 1:10 v/v) to remove the oxidized thin InAlAs layer in the channel region and was loaded into an atomic layer deposition (ALD) chamber. 1.5 nm Al2O3 and 5.5 nm HfO2 high-k gate dielectric was deposited by ALD at 250 °C after a few cycles of trimethylaluminum (TMA) exposure. TMA cleaning prior to high-k deposition helps to remove native oxides from the channel area. Mo and W (W-on-Mo) were deposited as the gate electrode. The gate was then patterned using photolithography and W/Mo were etched using fluorine based plasma etching at room temperature, using photoresist as hard mask. InAlAs buffer layer was partially etched in H3PO4:H2O2:H2O (1:5:40 v/v) solution for mesa isolation. This step completes the transistor fabrication.
SiO2 was then deposited using plasma enhanced chemical vapor deposition (PECVD) at 350 °C to passivate the transistors. This step also greatly improves the electrical characteristics and uniformity of the transistors. Dry etch was used to etch SiO2 and open the areas for laser fabrication. The InAlAs buffer was then completely etched in those areas to stop at n+-GaAs (contact layer) using dilute hydrochloric acid solution (HCl:H2O = 3:1 v/v).
GaAs/AlGaAs semiconductor laser diode featuring a top-top contact and dry etched vertical mirror facet was then fabricated. The laser waveguide was patterned using photolithography and wet etch was done using photoresist as the hard mask. Phosphoric acid solution (H3PO4:H2O2:H2O = 2:1:10 v/v) was used for wet etching of III-V layers.
Next, SiO2 was deposited using PECVD and patterned using photolithography. SiO2 was then etched using fluorine plasma based RIE etch. The sample was then dipped in dilute hydrochloric acid to remove the native oxides and loaded into an ICP chamber. Chlorine based plasma etch was done at 250 °C to form the vertical laser facets using SiO2 as the hard mask. A high temperature III-V etch ensures smooth and vertical laser mirrors which would affect the threshold current and output power of the laser diode. Titanium (Ti) followed by gold (Au) were deposited for P-contact followed by lift-off. Passivation of laser waveguide was done by depositing Benzocyclobutene (BCB) which also serves as planarization material. After waveguide exposure, N-contact (Au/Ge/Ni) was deposited (Au as top contact) followed by lift-off. The contact was then annealed at 400 °C for 5 s. This completed the laser diode fabrication.
Finally, the transistors and laser were connected by metal lift-off. The samples were then thinned down and diced for measurements. The highest temperature used in the entire process flow was 400 °C. The low thermal budget of the overall process helped to maintain the high quality of the QW.
4. Materials and electrical characterization
4.1. TEM analysis of integrated transistors and layers
Figure 3(a) shows the cross-sectional transmission electron microscopy (TEM) image of the self-aligned InGaAs n-FET with the raised n+- InGaAs source/drain, W/Mo gate, and InGaAs channel. High-k gate oxides Al2O3 and HfO2 can be clearly observed in the high resolution TEM (HRTEM) image of the gate stack, as shown in Fig. 3 (b). Figure 3(c) shows the cross sectional TEM image of the complete GaAs/AlGaAs QW laser diode with the GaAs/AlGaAs QW as active core and AlGaAs cladding layers. Sharp GaAs/AlGaAs interface can be clearly seen in the HRTEM image of the laser active core [Fig. 3 (d)]. This is mainly attributed to the low overall processing temperature (≤ 400 °C). Figure 4(e) shows the energy-dispersive X-ray (EDX) analysis of the GaAs/AlGaAs QW along the line AA’ and reveals the sharp boundaries of GaAs/AlGaAs layer without any significant intermixing. It can be confirmed that thickness of GaAs layer is ~5 nm.
Fig. 3 (a) Cross sectional TEM image of a self-aligned InGaAs FET with raised n+-InGaAs source/drain, InGaAs channel, and the gate stack. (b) HRTEM image showing W/Mo gate metal and HfO2/Al2O3 high-k dielectrics on the InGaAs channel. (c) Cross sectional TEM image of a laser showing Ge/GaAs buffer, AlGaAs cladding layer, GaAs/AlGaAs QW, and contact layers on the Si substrate. (d) HRTEM of the GaAs/AlGaAs QW showing well defined GaAs/AlGaAs boundaries. (e) EDX analysis of GaAs/AlGaAs QW along the line AA’.
Fig. 4 (a) ID-VG curves of an InGaAs n-FET with LCH of 420 nm showing ION/IOFF of more than 6 orders and S of 82 mV/decade at VDS of 50 mV. (b) ID-VD characteristics of the same device in Fig. 5 (a), showing ION of ~455 µA/µm at VGS−VT and VDS of 1 V. (c) Total on-state resistance as a function of LCH in the linear regime with a source drain series resistance of 1.4 kΩ·µm and channel sheet resistance of 697 Ω/□. (d) Plot of maximum transconductance as a function of channel length at a drain voltage of 0.5 V. Transconductance scales well with channel length.
4.2. Electrical characteristics of InGaAs n-FETs
InGaAs n-FETs with channel lengths (LCH) ranging from 400 nm to 10 µm were fabricated. Figure 4(a) shows the drain current versus gate voltage curves for LCH of 420 nm at a drain voltage (VDS) of 50 mV and 500 mV. Excellent transfer characteristics with ION/IOFF ratio of more than 6 orders at both high and low VDS were obtained with very low off state leakage current. A minimum subthreshold swing S of 82 mV/decade was achieved at a VDS of 50 mV. The threshold voltage (VT) of the device is 50 mV. VT was determined by using the maximum transconductance linear extrapolation method at low VDS of 50 mV. The output characteristics of the same device show good saturation behavior as shown in Fig. 4(b). A large drive current of 455 µA/µm was obtained at a gate overdrive VGS −VT of 0.95 V and a VDS of 1 V.
Source/drain series resistance (RSD) was extracted from the total resistance versus channel length graph as shown in Fig. 4(c). Total resistance of MOSFETs can be expressed as below,
where RTOT is the total on-resistance (normalized w.r.t. width) and RCH is the channel sheet resistance. The intercept gives a value of RSD ~1.4 kΩ·µm and the slope gives RCH ~697 Ω/□. RSD can be further reduced by increasing the doping of top InGaAs cap layer. A reduction of RSD would lead to enhanced drive current. Figure 4(d) shows the maximum extrinsic transconductance versus channel length curve at a VDS of 0.5 V. A high value of transconductance value of 443 µS/µm was obtained for a device with LCH = 420 nm at a VDS = 0.5 V. Good scaling of transconductance with channel length is observed.To get a statistical plot, a large number of transistors were measured before and after laser diode fabrication. Figure 5(a) shows the cumulative probability of S at a drain voltage of 50 mV. The mean value is reduced from an S value of 107 mV/decade to 81 mV/decade after laser fabrication. A tight distribution of S and the smallest value of 75 mV/decade were obtained. This indicates excellent electrostatic gate control and gate stack quality. This improvement in S is attributed to post metal anneal (PMA) during SiO2 deposition at 350 °C which leads to reduction of interface traps at high-k/InGaAs interface [28].
Fig. 5 (a) Statistical plot of the S before and after laser fabrication at a drain voltage of 50 mV. Devices after laser diode (LD) fabrication exhibit a tighter distribution and show significantly improved S with values as low as 75 mV/decade, indicating excellent electrostatic gate control and gate stack quality. (b) VT of InGaAs MOSFETs before and after laser fabrication. All devices have positive VT and improved uniformity after LD fabrication process.
There is a considerable improvement in VT uniformity of InGaAs n-FETs after laser fabrication, as can be seen from the cumulative probability plot in Fig. 5(b). The threshold voltage shows a tighter distribution after laser fabrication. In addition, the threshold voltage shifts to positive. This can be explained by reduction of fixed positive charges in high-k layer during SiO2 deposition at 350 °C [29].
4.3. Electrical and optical characteristics of GaAs/AlGaAs lasers
The laser characteristics were measured in pulsed mode with pulse width of 5 µs and duty cycle of 5%. Current density versus voltage (J-V) curve of a laser diode is shown in Fig. 6(a) with ION/IOFF ratio of more than 4 orders. Lasing spectra was obtained at 5 °C and 20 °C for single mode lasing currents of 500 mA and 620 mA, respectively, as shown in Fig. 6 (b). It can be clearly seen that electrically pumped lasing occurs at 789 nm at 5 °C and 795 nm at 20 °C. The shift in peak emission wavelength of 6 nm corresponds to change in bandgap of GaAs/AlGaAs QW with temperature. An increase of temperature decreases the semiconductor bandgap [30], leading to an increase of the wavelength. A small laser spectral response FWHM of 0.3 nm and 0.35 nm is obtained at temperatures of 5 °C and 20 °C, respectively. Although the FWHM of around 0.3 nm is wider as compared to lasers grown on native III-V substrate, it is less or comparable to III-V lasers epitaxially grown on Si substrate [16,19,31].
Fig. 6 (a) (a) J-V curve of the GaAs/AlGaAs QW laser diode showing ION/IOFF ratio of more than 4 orders. (b) Lasing spectra of a laser diode at 5 °C and 20 °C at single mode lasing currents of 500 mA and 620 mA, respectively. For both temperatures, the line width is less than 0.5 nm. (c) Output power as a function of current density for a 540 µm × 20 µm wide laser at various operating temperatures.
Figure 6(c) shows the effect of various operating temperatures on the laser output power for a 540 µm × 20 µm laser diode. The threshold current density of the same device is ~4.9 kA/cm2 at an operating temperature of 5 °C. This threshold current density is higher than that (875 A/cm2) in our previous work where the laser was formed on bulk Ge substrate [27]. This is mainly due to higher defect density in III-V layers grown on Si substrate as compared to III-V on bulk Ge substrate. It can be seen that the laser output power at the same lasing current drops with increasing temperatures. The output power at 10 °C decreased to 77% of the laser output at 5 °C. This could be mainly attributed to increased heat generation in the QW laser core due to increased operating temperatures. Dislocation filtering layers (DFLs) such as superlattices and better heat dissipation system may be required to reduce the defect density and hence, improve the threshold current and temperature stability [16].
4.4. Electrical and optical characteristics of GaAs/AlGaAs lasers
Figure 7(a) is the symbol of the integrated laser transistor circuit. Figure 7(b) shows the voltage and current transfer characteristics of the integrated laser and transistor with multiple fingers at supply voltage of 1 V and 2 V. VIN is varied from −0.2 to 0.8 V. When VIN (gate voltage) exceeds threshold, transistor is turned on, thereby decreasing the VOUT. This increases the voltage across laser diode and thus increases the circuit current. A successful modulation of voltage (VOUT) and injection current (ID) across the laser diode is realized by varying the transistor gate voltage.
Fig. 7 (a) Symbol of the integrated laser-transistor circuit. (b) Voltage and current transfer characteristics of the integrated laser-transistor circuit. Modulation of VOUT by gate voltage (VIN) clearly indicates the successful operation of the integrated circuit.
It can be observed from Fig. 7(b), that at a supply voltage (VDD) of 2 V, the maximum current through the circuit is much lower than the lasing threshold of 600 mA. Very high VDD would be required to demonstrate the laser output power modulation in this circuit. A high VDD translates to a higher VOUT in the off state and therefore, may lead to transistor breakdown. To solve this issue, the laser threshold current should be reduced. This can be achieved by improving the materials quality to reduce the dislocation density or by using quantum dot based lasers which have been shown to have much lower threshold currents of less than 100 mA [16].
The GaAs/AlGaAs system is adopted in this work for demonstrating the integration of laser and transistor as a proof of concept. It is noted that the lasing wavelength is not transparent to the Si substrate for photonics integrated circuit (PIC) applications. To realize longer lasing wavelengths, a smaller bandgap material such as InxGa1-xAs/GaAs is required for the laser. As compared to the GaAs/AlGaAs system, using the InxGa1-xAs/GaAs system with a higher Indium composition involves a higher lattice mismatch with respect to silicon and the challenge of growing such materials with low-defectivity for laser fabrication on silicon need to be addressed.
5. Conclusion
Monolithically integrated InGaAs FETs and GaAs/AlGaAs QW laser diodes were demonstrated on the Si substrate using direct epitaxial growth. A low thermal budget process flow was developed so that InGaAs FETs and lasers with good electrical and optical characteristics can be achieved. InGaAs MOSFETs with ION/IOFF of more than 6 orders and minimum subthreshold swing of less than 82 mV/decade were demonstrated. Room temperature electrically pumped GaAs/AlGaAs laser with laser spectrum FWHM of less than 0.5 nm were realized. The co-integration of advanced logic devices and electrically pumped lasers, as demonstrated in this work, is an important milestone in the development of future OEICs.
Funding
Singapore National Research Foundation Competitive Research Program (NRF-CRP6-2010-4); Singapore MIT Alliance for Research and Technology – Low Energy Electronic Systems (SMART-LEES) program (R-263-000-C10-592).
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