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This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35–1.89 million times longer than those of current FPGAs.
© 2017 Optical Society of America
1. Introduction
Nuclear accidents have occurred at several nuclear power plants [1–3]. Some of them, particularly at Chernobyl and Fukushima Daiichi nuclear power plants, have not been repaired to the present day. They present important radiation-related difficulties. Radiation-hardened robots have been under development recently for the exploration and repair of radiation-affected sites [4,5].
For radiation-hardened robots, radiation-hardened SRAM-based field programmable gate arrays (FPGAs) are anticipated for application since low-volume production of such radiation-hardened robots has commenced [6, 7]. Nevertheless, such FPGAs are still vulnerable to radiation. The most important concern of current FPGAs used in high-radiation environments is the high frequency of soft-errors that occur on their configuration memories. Even if triple modular redundancy (TMR) arrangements are used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be resolved. The frequencies of the soft-errors must be decreased to increase the radiation tolerance of FPGAs.
To date, various scrubbing methodologies applicable to FPGAs have been proposed to decrease the frequencies of soft-errors that occur on their configuration memories [8–10]. A major scrubbing method is that configuration data stored on an external EEPROM is downloaded cyclically to a target FPGA with no check of configuration memory as blind [10]. Since the radiation tolerance of EEPROMs is higher than that of static random access memories (SRAMs), the EEPROM configuration context can be maintained correctly. The correct configuration data can be downloaded cyclically to an FPGA’s configuration memory, even in a radiation-contaminated environment. However, the scrubbing period becomes greater than 100 ms: new soft-errors occur on the FPGA configuration memory while data on the FPGA’s configuration memory are repaired. For that reason, the radiation tolerance of the configuration memory depends on its scrubbing period. That fact implies that a shorter scrubbing period is suitable to increase the radiation tolerance: a 100 ms scrubbing period should be regarded as too slow for high-radiation environments.
ICAP technology (Xilinx Inc.) is frequently used for scrubbing methodologies [8, 9]. After identification of the locations of soft-errors on the configuration memory, only the error regions on the configuration memory are reconfigured. The scrubbing period of the ICAP scrubbing method exploiting a partial reconfiguration can be decreased to 3.67–10 ms. Even so, a millisecond-order scrubbing period can be regarded as insufficient in terms of the mean time between soft-errors (MTBF).
This paper therefore presents a proposal of a high-speed scrubbing method based on an ORGA architecture. The ORGA architecture comprises an optically reconfigurable gate array VLSI, a holographic memory, and a laser array, as shown in Fig. 1 [11–16]. The ORGA-VLSI includes a fine-grained programmable gate array. The ORGA architecture is a multi-context FPGA. Many configuration contexts are stored on the holographic memory, from which they are read out by the laser array.
However, an important benefit of the ORGA architectures for scrubbing operations is their parallel configuration. The optical configuration context, which has numerous configuration bits, is received on the photodiode array on an ORGA-VLSI simultaneously. The ORGA architecture has a parallel optical bus between the holographic memory and the photodiode array on an ORGA-VLSI. Therefore, the ORGA architecture can support nanosecond-order high-speed reconfiguration or a high-speed scrubbing operation. This paper presents a demonstration of high-speed scrubbing on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically.
The remainder of this paper is organized as follows: Section II explains the proposed optical scrubbing technique. Section III presents a theoretical analysis of the soft-error rate on the optical scrubbing technique. Section IV demonstrates the optical scrubbing technique on an optically reconfigurable gate array. Section V presents the experimentally obtained results. Finally, Section VI concludes this work.
2. Optical scrubbing technique
2.1. ORGA-VLSI
The internal construction of a fabricated ORGA-VLSI is portrayed in Fig. 2. The ORGA-VLSI was used for a demonstration of the proposed optical scrubbing technique. The ORGA-VLSI was fabricated using a 0.18 μm 2P5M CMOS process at Rohm’s manufacturing facility. The photograph and specifications are also presented in Fig. 3 and Table 1. The ORGA-VLSI has a 2,720-gate fine-grained programmable gate array including 80 logic blocks, 90 switching matrices, and 8 I/O blocks. The fine-grained programmable gate array is also based on 4-input look-up tables, flip-flops, and switching metrics, as are standard FPGAs. The basic function is perfectly identical to those of currently available FPGAs. As presented in Fig. 2, each logic block consists of selectors, two four-input look-up tables, two flip-flops, and some tri-state buffers. The look-up table inside the logic block can store a Boolean function. The input signals of look-up tables are applied through selectors from the wiring channel. The outputs of the look-up tables are connected to flip-flops. Finally, either sequential output or combinational output can be selected. The output is connected to another-side wiring channel through tri-state buffers. Wiring between the logic blocks can be programmed on switching matrices. Each switching matrix is located at the cross point of the top, bottom, left, and right wiring channels. It actually serves to connect them. Each switching matrix has eight switching elements, each of which consists of six transmission gates as switch elements.
Table 1. Specifications summary.
The difference between FPGAs and ORGAs exists inside a configuration mechanism. The numerous P marks shown in Fig. 2 signify photodiodes. Programming points to define the state of the programmable gate array are connected to a photodiode array. The number of photodiodes is 10,322. Their size is 4.4 μm by 4.54 μm. The PN junction of each photodiode was constructed between the N-well and P-substrate. For example, a 4-input look-up table includes 16 photodiodes so that all 16 states of the look-up table can be programmed optically at once and perfectly in parallel. Furthermore, photodiodes control all switches, selectors, and tri-state buffers. Therefore, the programmable gate array on the ORGA can be reconfigured optically.
2.2. Optical scrubbing technique
As described above, the ORGA-VLSI can support high-speed reconfiguration based on 5-ns-response photodiodes on the ORGA-VLSI. The high-speed reconfiguration capability was applied to the proposed high-speed scrubbing operation. Since the ORGA architecture uses a parallel configuration mechanism such that the configuration time for the entire programmable gate array is equal to the configuration time for partial reconfiguration for a part of the programmable gate array, there is no reason to choose a partial reconfiguration for scrubbing operations. In the ORGA architecture, the entire programmable gate array can be reconfigured at once and at any time. This optical scrubbing technique uses blind scrubbing, which obviates the checker circuit and overhead for the configuration memory.
In the proposed optical scrubbing technique, a configuration context stored on a holographic memory is downloaded cyclically to the programmable gate array on the ORGA-VLSI at regular intervals. Since holographic memories are more robust than EEPROMs, the configuration context read from the holographic memory can be regarded as correct data [17]. Therefore, the configuration context stored on the programmable gate array on the ORGA-VLSI is repaired constantly by the robust holographic memory data.
3. Theoretical analysis of the optical scrubbing technique
Radiation incidence is categorized as a low probability event. Such a low probability event follows a Poisson distribution [18]. Here, it is assumed that a single event upset happens on the configuration memory when radiation is incident on a chip. The probability P(m) of m simultaneously occurring incidences in a single period is calculable using the following equation.
In that equation, N̄ represents the average number of incidences for the period. For this study, triple modular redundancy (TMR) is assumed to be implemented on a programmable gate array. In such TMR systems, the same three modules are implemented onto the programmable gate array. Therefore, three configuration memory blocks are used for the three modules. In this case, even if one configuration memory used for a module is broken, correct operations can be executed because of TMR. The probability of this situation is P(1). Of course, in the case of non-incidence condition of P(0), the TMR components can function correctly. Therefore, the summation of P(0) and P(1) stands for the probability that TMR components can function correctly. The related circumstances are described below. Moreover, if two charged particles were incident to two modules on a TMR system, thereby damaging the two modules, then the TMR system would be unable to function correctly. However, even if two radiation incidence errors occur simultaneously, if two particles create one error with one module or if two errors affect a single module, then the TMR system can still function correctly. That probability is calculable as 1/3 of two radiation incidence probability P(2) simply because that is the probability of the second charged particle being incident to the first particle-incident module among all three modules on the TMR. Moreover, even if three radiation particle incidence errors occur simultaneously, if three particles are incident to one module, then the TMR system functions correctly. That probability is calculated as described below. Therefore, the total probability PTMR that the TMR system functions correctly is expressed as shown below. Finally, the mean time between soft-errors, or the mean time between temporal failures (MTBF), is calculable as follows. Using the equations presented above, for example, the MTBF of current FPGA scrubbing can be calculated for a 100-ms configuration period. When assuming that one charged particle is incident to the device per second, the average number N̄ of radiation particles that are incident during 100 ms is 0.1. Therefore, assigning 0.1 to N̄ of Eq. 5 and using the scrubbing period Tscrubbing =100 ms for Eq. 6, one finds that the MTBF of the current FPGA scrub bing is calculated as 31.7 s. The frequent soft-errors cannot be neglected. However, if 50–70 ns period scrubbing is achievable, then the MTBF can be extended to 1.36–1.90 years. Here, similarly, the average number N̄ of incident radiation particles during 50–70 ns is estimated as 5 − 7 × 10−8. Therefore, assigning 5 − 7 × 10−8 to N̄ of Eq. 5 and using the scrubbing period Tscrubbing =50–70 ns for Eq. 6, one finds that the MTBF of the case reaches 1.36–1.90 years. In that case, the MTBF can be extended to 1.35–1.89 million times longer than that in the case of 100 ms scrubbing used for current FPGAs. If the ORGA architecture supported 50–70 ns high-speed scrubbing, then the soft-errors on the configuration memory on the ORGA-VLSI could be removed from consideration as a practical constraint on most radiation-related applications.4. Experimental system
To demonstrate high-speed scrubbing, an optically reconfigurable gate array (ORGA) was constructed as presented in Figs. 4 and 5. The ORGA consists of a liquid crystal spatial light modulator (LC–SLM), a laser, and the ORGA-VLSI. Specifications of the optical components, the LC–SLM, and the laser are presented in Table 1. The LC–SLM is used as a programmable holographic memory. The holographic memory patterns of an AND circuit, a 2-bit adder circuit, and a 2-bit multiplier circuit were calculated using a personal computer as shown in Figs. 6(a), 7(a), and 7(b). Figure 6(b) represents a radiation-emulated holographic memory pattern produced by application of impulse noise for a 20 % region of the original holographic memory pattern shown in Fig. 6(a). The LC–SLM resolution is 1,920 × 1,080 pixels, each of 7 × 7 μm2. These computer-calculated holographic memory patterns were displayed at the center 1,000 pixel × 1,000 pixels of LC–SLM in turn. The source laser is a Cobolt SambaTM 1500 mW Laser. The ORGA-VLSI shown in Fig. 3 was placed 120 mm distant from the LC–SLM. The ORGA-VLSI were controlled by an FPGA (APEX:EP20K200CF484C8).
Fig. 7 Holographic memory pattern of a 2-bit adder and a 2-bit multiplier circuits. They consist of 1,000 × 1,000 pixels.
5. Experimental results
Figure 6(a) shows the holographic memory patterns of an AND circuit. It was implemented onto LC–SLM. Then, 50-ns high-speed scrubbing operation was achieved on the experimental system. Next, a 20 % impulse-noise-applied holographic memory pattern of an AND circuit shown in Fig. 6(b) was displayed on LC–SLM. It has been confirmed that correct scrubbing operations can be executed. This result demonstrates that holographic memory data are extremely robust even if the holographic memory itself is damaged by radiation. Then, a 2-bit adder circuit and a 2-bit multiplier circuit were implemented onto LC–SLM. The gate array implementations of the 2-bit adder circuit and 2-bit multiplier circuit are presented respectively in Figs. 9(a) and 9(b). The 2-bit adder circuit was implemented onto three 4-input look-up tables on two logic blocks, two switching matrices, and two I/O blocks. Furthermore, the 2-bit multiplier circuit was implemented onto four 4-input look-up tables on two logic blocks, two switching matrices, and two I/O blocks. The configuration contexts corresponding to these gate array implementations are shown respectively in Figs. 8(a) and 8(b), The bright points and dark points respectively denote binary state highs and binary state lows as well as binary configuration contexts on FPGAs. Their scrubbing operations were confirmed as shown in Figs. 10(a) and 10(b). In the operation, first, the nREF signal is activated for charging the junction capacitances of all photodiodes. Then photodiodes receive a configuration context. Finally, the information is latched at the rising edge of configuration clock signal CCLK. The 70-ns-period high-speed scrubbing operations were achieved for both circuits.
Fig. 8 CCD-captured configuration context patterns of the 2-bit adder and the 2-bit multiplier circuits.
Fig. 10 Waveform of the 2-bit adder and the 2-bit multiplier circuits captured using a logic analyzer (16950A; Agilent Technologies Inc.).
Consequently, 50–70 ns period high-speed scrubbing operations are possible on currently available ORGA architecture. As discussed previously, in this case, the MTBF can be extended to 1.36–1.90 years. In stark contrast, the MTBF of current FPGA’s scrubbing based on a 100 ms configuration period is 31.7 s. Results therefore verify that MTBF can be extended to 1.35–1.89 million times longer than those for 100 ms scrubbing on current FPGAs. In the ORGA architecture, soft-errors that occur on the configuration memory on ORGA-VLSI can therefore be removed from consideration as a practical hindrance to applications in radiation-rich environments.
6. Conclusion
This paper has presented a proposal of a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. Although the most important concern of current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors that occur on their configuration memories, the proposed optical scrubbing technique based on optically reconfigurable gate arrays can increase the radiation tolerance of an ORGA to MTBF of 1.36–1.90 years from 31.7 s of current FPGAs. Results show that the MTBF on the ORGA configuration memory related to radiation can be extended to 1.35–1.89 million times longer than those of current FPGAs.
Funding
Ministry of Education, Science, Sports and Culture, Grant-in-Aid for JSPS Research Fellow, No. 16J12063 and Grant-in-Aid for Scientific Research(B), No. 15H02676.
Acknowledgments
The VLSI chip in this study was fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Rohm Co. Ltd. and Toppan Printing Co. Ltd.
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