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Abstract
We demonstrated the monolithic integration of a carrier-injection InGaAsP Mach-Zehnder interferometer (MZI) optical modulator and InGaAs metal-oxide-semiconductor field-effect transistor (MOSFET) on a III-V-on-insulator (III-V-OI) wafer. A low-resistivity lateral PIN junction was formed along an InGaAsP rib waveguide by Zn diffusion and Ni-InGaAsP alloy, enabling direct driving of the InGaAsP optical modulator by the InGaAs MOSFET. A π phase shift of the InGaAsP optical modulator was obtained through the injection of a drain current from the InGaAs MOSFET with a gate voltage of approximately 1 V. This proof-of-concept demonstration of the monolithic integration of the InGaAsP optical modulator and InGaAs driver MOSFET will enable us to develop high-performance and low-power electronic-photonic integrated circuits on a III-V CMOS photonics platform.
© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
To process gigantic amounts of data, datacenters require more advanced intra- and inter datacenter networks including high-bandwidth and low-power optical interconnects with ultrasmall photonic integrated circuits (PICs) [1]. A conventional InP-based PIC can monolithically integrate passive waveguides, laser diodes (LDs), modulators, switches, photodetectors (PDs), and other active devices on an InP wafer [2–4]. However, its low refractive index contrast does not allow us to develop ultrasmall InP PICs by using complementary metal-oxide-semiconductor (CMOS) -compatible processes, unlike Si photonics. To eliminate this drawback of InP PICs, we previously proposed a III-V CMOS photonics platform that uses a III-V-on-insulator (III-V-OI) structure on a Si wafer [5, 6]. By using direct wafer bonding, we successfully developed a III-V-OI wafer that is similar to a Si-on-insulator (SOI) wafer for Si photonics [7]. The SOI platform has advantage of manufacturability and cost, while the III-V-OI platform is potentially capable of achieving higher performance than the SOI platform since high-performance light sources, modulators, and photodetectors can be monolithically integrated. The strong optical confinement in InP-based rib or strip waveguides on a III-V-OI wafer enables ultrasmall InP photonics comparable to Si photonics. On the III-V CMOS photonics platform, microbends, wavelength multiplexers [7], grating couplers [8], ring resonators [9], optical switches [10], PDs [11, 12], and LDs [13, 14] have been demonstrated so far. The III-V CMOS photonics platform has the potential for the monolithic integration in InGaAs MOS field-effect transistors (FETs) because of the significant progress of InGaAs MOSFETs for digital logic applications [15]. Since InGaAs has a high electron mobility, ultrahigh-speed InGaAs n-MOSFETs, which can be fabricated with moderate gate length scaling, are promising particularly for a driver circuit monolithically integrated with photonics. The monolithic integration of InGaAs n-MOSFETs with GaSb p-MOSFETs [16] or Ge p-MOSFETs [17] have also been investigated for high-speed and low-power CMOS circuits [18]. However, the monolithic integration of photonic components and InGaAs MOSFETs on a III-V-OI wafer has not yet been reported.
In this paper, we demonstrate the monolithic integration of an InGaAsP Mach-Zehnder interferometer (MZI) optical modulator and an InGaAs driver MOSFET on a III-V-OI wafer. A cross-sectional schematic of each device is shown in Fig. 1(a). The InGaAsP MZI optical modulator is equipped with a lateral PIN junction for carrier injection. The InGaAs MOSFET is stacked on a photonic layer for easy integration. As shown in the three-dimensional schematic in Fig. 1(b), the drain of the InGaAs MOSFET was connected to the PIN junction to drive the InGaAsP optical modulator directly. To achieve monolithic integration and successful device operation, we performed several fabrication processes including the pre-bonding annealing for the III-V-OI wafer, Zn diffusion, and Ni alloying. Thus, a π phase shift in the optical modulator was obtained by the driving current of the InGaAs MOSFET, giving a proof-of-concept demonstration of the electronic-photonic integration capability of the III-V CMOS photonics platform.
Fig. 1 (a) Cross-sectional schematic of InGaAs MOSFET and InGaAsP optical modulator on a III-V-OI wafer and (b) 3D schematic of carrier-injection InGaAsP MZI optical modulator monolithically integrated with InGaAs driver MOSFET.
2. Device fabrication
To demonstrate the monolithic integration of the InGaAsP MZI optical modulator and InGaAs MOSFET on a III-V-OI wafer, we have to resolve two process issues: void generation in a III-V-OI wafer during a high-temperature process, and the formation of a low-resistivity lateral PIN junction for carrier-injection optical modulators with a low thermal budget. Since generated voids degrade the yield of a device, it is important to suppress void generation during a high-temperature process. It is also essential to form a low-resistivity lateral PIN junction for direct driving of the optical modulator by a MOSFET. A low-temperature formation process may also contribute to the suppression of voids. We have developed a process involving prebonding annealing for void suppression and a combination of Zn diffusion and Ni alloying for the formation of PIN junctions.
2.1 Suppression of void generation in a III-V-OI wafer
We used direct wafer bonding with an Al2O3 bonding interface formed by atomic layer deposition (ALD) because a large surface energy can be obtained without O2 plasma irradiation, enabling low-damage wafer bonding [10]. However, the moisture in an Al2O3 layer causes void generation during high-temperature annealing after bonding [19]. To achieve monolithic electronic-photonic integration, void generation must be suppressed during the entire process. To achieve a void-free III-V-OI wafer, we applied prebonding annealing at various temperatures and examined tendency of void generation upon postbonding annealing. The fabrication procedure of a III-V-OI wafer with prebonding annealing is depicted in Fig. 2. A III-V device layer was grown on an InP wafer by Sumitomo Chemical Co. Ltd. We also prepared a Si wafer with a 2-μm-thick thermal SiO2 layer on top. An Al2O3 layer was deposited on each wafer as a bonding interface by ALD. Then, prebonding annealing was carried out at 500 or 600 °C for 20 min in N2 ambient. After cleaning the wafer surfaces using megasonic water to remove particles, both wafers were bonded in air. The room mean square surface roughness of the donor InP wafer and SiO2/Si wafer was approximately 0.2 nm, sufficiently low for achieving high-yield bonding without chemical mechanical polishing. We used 2-inch wafers for bonding due to the limitation of the facilities. However, in principle, the wafer diameter can be scaled up with the same bonding process. Finally, the InP substrate was selectively removed by wet etching. To recycle the InP wafer, we may use the Smart CutTM technology as reported in [20].
Fig. 2 Fabrication procedure of III-V-OI wafer with prebonding annealing: (a) Al2O3 deposition by ALD, (b) prebonding annealing, (c) direct wafer bonding, and (d) selective etching of InP substrate.
To perform postbonding annealing, a 100-nm-thick SiO2 layer was deposited on the III-V-OI wafer by plasma-enhanced chemical vapor deposition (PECVD) as a capping layer. The postbonding annealing was carried out at temperatures from 400 to 700 °C for 1 min in N2 ambient. Figures 3(a) and 3(b) show plan-view photographs of the III-V-OI wafers after postbonding annealing at 600 °C. As shown in Fig. 3(a), we observed many voids after post-bonding annealing when we performed no prebonding annealing. According to Fig. 3(b). void generation can be suppressed by performing prebonding annealing at 600 °C. Figure 3(c) shows the density of voids as a function of the temperature of postbonding annealing. We estimated the density of void by counting voids from plan-view photographs. The bonded wafer without prebonding annealing shows severe void generation above 600 °C. The bonded wafer with prebonding annealing at 500 °C shows less void generation but microvoids still exist. When prebonding annealing was carried out at 600 °C, the density of voids was suppressed to less than 104 cm−2, which is acceptable for device fabrication. Although many voids were still generated by post-bonding annealing at 700 °C, a high-temperature process at a temperature of up to 600 °C is acceptable for our bonded III-V-OI wafer, enabling many process options including regrowth.
Fig. 3 Plan-view photographs of III-V-OI wafer (a) without prebonding annealing and (b) with prebonding annealing at 600 °C after postbonding annealing at 600 °C. (c) Density of voids on a III-V-OI wafer as a function of postbonding annealing temperature.
2.2 Formation of a low-resistivity PIN junction
It is important to form a low-resistive lateral PIN junction for carrier-injection devices with a III-V-OI wafer. However, ion implantation of Be results in a high-resistivity III-V layer due to the low activation rate. Instead of Be ion implantation, Zn diffusion from spin-on-glass (SOG) is effective for forming a heavily doped p+-InGaAsP region with low defect density at a junction edge as shown in Fig. 4(a) [21, 22]. We have also investigated the use of Ni-InGaAsP alloy to form a low-resistive n+-InGaAsP region with a low thermal budget instead of Si implantation [23, 24]. A combination of Zn diffusion and Ni-InGaAsP alloy allows us to form a low-resistive PIN junction. However, Zn diffusion induces a large thermal stress particularly in a waveguide mesa. When the gap between the edge of the waveguide mesa and the Zn-diffusion region was reduced from 4 to 2 μm, the III-V layer at the waveguide edge was delaminated, probably due to the accumulation of thermal stress at the step edge of the waveguide mesa, as shown in Figs. 4(b) and 4(c). Since a narrow gap is important for reducing the parasitic resistance in the lateral PIN junction, the thermal stress induced by the SOG should be reduced.
Fig. 4 (a) Schematic of Zn diffusion process and plan-view photographs of Zn-diffusion devices with gaps of (b) 4 μm and (c) 2 μm.
To reduce the thermal stress during Zn diffusion, we optimized the SOG thickness, curing temperature, and diffusion temperature. By changing the spin-coating conditions of the SOG, the thickness of the SOG was reduced from 160 to 140 nm. The thickness of the SOG at the edge of the waveguide is greater than in other areas. Hence, the stress is concentrated at the waveguide edge. A thinner SOG reduces the thermal stress. Secondly, we increased the curing temperature of SOG from 200 to 300 °C. The SOG shrinks while curing. If the SOG is not completely cured, the additional stress will be applied by the shrinking. We also reduced the diffusion temperature from 550 to 500 °C. Through this optimization of Zn diffusion, the delamination of the III-V layer was completely suppressed even when the gap was as small as 500 nm, as shown in Fig. 5(a). Figure 5(b) shows the distribution of Zn after diffusion evaluated by secondary ion mass spectrometry (SIMS). A Zn concentration as high as 1020 cm−3 was observed up to a depth of 200 nm. As compared with the ion implantation of Be, the sheet resistance can be reduced by a factor of ten [24]. The active hole concentration was roughly estimated to be 1 × 1019 cm−3. We also introduced InGaAsP alloy to form a low-resistive n+-InGaAsP region with a low thermal budget instead of performing Si implantation. As described in [24], Ni-InGaAsP alloy can be formed at 350 °C. The current-voltage (I-V) characteristics of InGaAsP lateral PIN junctions formed by Zn diffusion in conjunction with Si implantation or the use of Ni-InGaAsP alloy are shown in Fig. 5(c). The Si-implanted sample was activated at 600 °C for 10 s in N2 ambient. Owing to the low resistivity Ni-InGaAsP alloy, the on current of the Ni-InGaAsP alloyed device was greater than that of the Si-implanted device. By optimizing the Zn diffusion and using the InGaAsP alloy, we obtained an access resistance of the InGaAsP lateral PIN junction of 0.4 Ωcm, which is comparable to that of state-of-the-art Si photonics devices [25, 26].
Fig. 5 (a) Plan-view photo of Zn-diffused device with the gap of 500 nm, (b) Zn distribution after diffusion, and (c) I-V curves of lateral PIN junction formed by Zn diffusion in conjunction with Si implantation or Ni-InGaAsP alloy.
2.3 Electronic-photonic integration
On the basis of the developed processes discussed in the previous sections, we fabricated an InGaAsP optical modulator monolithically integrated with an InGaAs MOSFET. To fabricate a III-V-OI wafer for monolithic electronic-photonic integration, i-InP (25 nm)/i-InGaAsP (350 nm, λg = 1.41 μm)/i-InP (25 nm)/p-In0.53Ga0.47As (350 nm, 1 × 1017 cm−3)/i-InP (25 nm)/i-InGaAs (100 nm) layers were grown on an InP wafer by metalorganic vapor phase epitaxy (MOVPE). The p-InGaAs thickness was designed to suppress the short channel effect in an 1-μm-gate-length InGaAs MOSFET with the channel doping density of 1 × 1017 cm−3. The InP epitaxial wafers were provided by Sumitomo Chemical Co., Ltd. After removing organic substances, the InP wafer was immersed in NH4OH to remove the native oxide. Then the InP wafer was treated with (NH4)2Sx solution for sulfur passivation [27]. After depositing a 2.5-nm-thick Al2O3 layer on the InP wafer and the thermally oxidized Si wafer by ALD, pre-bonding annealing was carried out at 600 °C for 20 min in N2 ambient. Both wafers were cleaned using megasonic water to remove particles on the surface, then manually bonded. Finally, the InP substrate and InGaAs layer were removed by HCl and a mixture of H2O2, H3PO4, and H2O, respectively.
The fabrication procedure of the InGaAsP optical modulator integrated with the InGaAs MOSFET on the III-V-OI wafer is shown in Fig. 6. After patterning the active area of the InGaAs MOSFET by electron-beam (EB) lithography, the InGaAs layer was selectively etched by a H2O2:H3PO4:H2O (1:1:7) mixture. A 700-nm-wide InGaAsP rib waveguide was also formed by EB lithography and reactive ion etching (RIE) with CH4/H2 and O2 gas. A 100-nm-thick SiO2 layer was deposited by PECVD. After patterning the SiO2 layer, Zn-doped SOG was coated on the wafer to form a p+-InGaAsP region. The SOG was cured at 300 °C for 2 h. Then, Zn diffusion was carried out at 500 °C for 1 min in N2 ambient. After Zn diffusion, the SOG film and SiO2 cap were removed using dilute HF solution. To clean the InGaAs surface, the NH4OH and (NH4)2Sx treatment were conducted before gate formation for the MOSFET. A 10-nm-thick Al2O3 layer and a 20-nm-thick Ta layer were deposited as a gate insulator and a gate metal by ALD and sputtering, respectively. After patterning the gate, a 20-nm-thick Ni layer was deposited on the InGaAs and InGaAsP layers by EB evaporation, followed by lift off. The Ni-InGaAs alloy used as a source and drain for the MOSFET and the Ni-InGaAsP alloy used as an n + -region for the PIN junction were simultaneously formed by rapid thermal annealing (RTA) at 350 °C in N2 ambient. After removing the unreacted Ni using dilute HCl, Ti/Pt electrodes were deposited by sputtering. Particularly we used the Pt electrode to form good Ohmic contact for the p+-InGaAsP regions. Finally, a Pt interconnection was formed between the InGaAsP modulator and InGaAs MOSFET by sputtering and lift-off. Although we used the Pt interconnect for process simplicity, we may use other metals for interconnect. Figure 7(a) is a plan-view photograph of the integrated devices. An InGaAsP asymmetric MZI optical modulator and an InGaAs driver MOSFET were monolithically integrated. The bubble-like morphology observed on the Ni-InGaAs and Ni-InGaAsP regions suggests defect generation, which might degrade the junction property as we will discuss later. Cross-sectional transmission electron microscope (TEM) images of the modulator and MOSFET are also shown in Figs. 7(b) and 7(c), respectively. The dark contrast and a scratch in Fig. 7(b) were probably attributed to the sample preparation issue for the TEM observation.
Fig. 7 (a) Plan-view photograph of InGaAsP MZI optical modulator integrated with InGaAs MOSFET and cross-sectional TEM images of (b) modulator and (c) MOSFET.
3. Experimental results
First, we evaluated the electrical properties of the lateral InGaAsP PIN junction of the carrier-injection phase shifter on the III-V-OI wafer formed by Zn diffusion and using Ni-InGaAsP alloy. Figures 8(a) and 8(b) show I-V curves of the InGaAsP lateral PIN junction plotted in logarithm and linear scales, respectively. The total width of the intrinsic region of the lateral PIN diode was 1.7 μm and the length of the phase shifter (Lphase) was 500 μm. As shown in Fig. 8(a), the on/off ratio at ± 1 V was more than 105. The ideality factor of the lateral PIN diode was 1.73. From Fig. 8(b), the on current exceeded 25 mA with a 2 V bias, which was sufficient to achieve a π phase shift. The increase in the reverse current suggested defect generation in the junction as we discussed in Fig. 7(a).
Fig. 8 I-V characteristics of lateral PIN diode of InGaAsP optical modulator plotted in (a) logarithmic and (b) linear scales.
To evaluate the phase shift induced by free carriers in the InGaAsP optical modulator, we formed an asymmetric MZI configuration. The waveguide width and mesa height were approximately 0.7 μm and 190 nm, respectively. The modulator was designed for the fundamental Transverse electric (TE) mode of the InGaAsP rib waveguide. The difference between the lengths of the two arms of the phase shifter was designed to be 20 μm, which resulted in a free spectrum range (FSR) of approximately 31 nm. TE polarized light from a C-band continuous-wave (CW) tunable laser was injected to the cleaved edge of the InGaAsP optical modulator via a lensed fiber and the output light was coupled again into a single-mode fiber connected to an InGaAs PD through an objective lens. Figure 9(a) shows transmission spectra of the InGaAsP asymmetric MZI optical modulator with injection currents of 0 and 2 mA. From the cut-back measurement, the coupling loss and propagation loss were estimated to be −26.5 dB and 0.86 dB/mm, respectively. From this result, the insertion loss of the MZI was estimated to be approximately −4.3 dB, which can be improved by optimizing the MMI coupler. The measured FSR of the fabricated InGaAsP optical modulator was approximately 30 nm, in good agreement with the designed value. When an injection current of 2 mA was injected via the lateral PIN diode, the resonance wavelength peaks were shifted owing to the change in the refractive index of InGaAsP, from which we extracted the phase shift. Figure 9(b) shows the extracted phase shift as a function of injection current. We observed almost linear dependence of phase shift on injection current. A π phase shift was achieved when the injection current was 2.2 mA. Figure 9(c) shows the benchmark carrier-injection modulators based on Si [25, 26] and InGaAsP. Regardless of the materials, the injection current required for a π phase shift increased as the length of the phase shifter decreased because the shorter phase shifter required higher carrier density for a π phase shift, promoting the Auger recombination. We achieved comparable modulation efficiency to that of the Si device at the same phase shifter length.Since InGaAsP has much larger electron-induced change in the refractive index than Si [28], we expect further improvement in the modulation efficiency of the InGaAsP optical modulator. The voltage dependence of the reverse current and the ideal factor in Fig. 8(a) suggest the existence of defects in the PIN junction, which might degrade the carrier injection efficiency. We estimated that the defects were generated during EB evaporation. One possible way to reduce the defects is to use chemical vapor deposition or ALD. By introducing such a process to form the lateral PIN junction on the III-V-OI wafer, the injection current required for a π phase shift can be reduced further. We have not yet evaluated the modulation bandwidth, which is expected to be greater 10 Gbps using the pre-emphasized driving scheme [29].
Fig. 9 (a) Transmission spectra and (b) phase shift characteristic of InGaAsP optical modulator. (c) Benchmark to Si optical modulator.
The electrical properties of an InGaAs MOSFET integrated with the InGaAsP optical modulator were also evaluated. The transfer characteristics of an InGaAs MOSFET with a gate length (Lg) of 1 μm were measured at drain voltages (VD) of 0.05 and 0.5 V, as shown in Fig. 10(a). Since the thickness and doping concentration of the p-InGaAs layer were designed appropriately, we achieved an on/off ratio of approximately 103, which was sufficient to switch the InGaAsP optical modulator. From the transfer curve at VD of 0.05 V, the effective electron mobility was extracted as a function of the surface carrier density Ns, as shown in Fig. 10(b). To extract the effective mobility, we assumed the gate oxide capacitance corresponding to the Al2O3 thickness used for the InGaAs MOSFET. The parasitic resistance was included in the mobility evaluation. The measured peak effective mobility was approximately 457 cm2/Vs, which is considerably lower than that of state-of-the-art InGaAs MOSFETs [30]. The poor subthreshold swing of 210 mV/dec. in Fig. 10(a) suggests that the origin of the low effective mobility was the degraded InGaAs MOS interface. Therefore, there is room for improvement of the on current through optimization of the fabrication procedure, for example, by introducing the sulfur passivation [27].
Fig. 10 (a) Transfer characteristics and (b) effective electron mobility of InGaAs MOSFET integrated with InGaAsP optical modulator.
The driving capability of the InGaAs MOSFET for the monolithically integrated InGaAsP optical modulator was evaluated. Figure 11(a) shows a schematic circuit diagram of the measured devices. The drain of the InGaAs MOSFET was connected to the Ni-InGaAsP region of the lateral PIN junction of the InGaAsP optical modulator. When a supply voltage VDD was applied to the p + -InGaAsP region of the modulator, a drain current ID was injected into the device that depended on the gate voltage Vg applied to the MOSFET. Before investigating the driving capability, we evaluated the output characteristics of an InGaAs driver MOSFET whose gate width W and length Lg were 100 and 1 μm, respectively. The curves in Fig. 11(b) show the output characteristics with gate overdrives Vg – Vth from 0 to 2 V measured by applying a drain voltage VD directly to the drain of the MOSFET, where Vth is the threshold voltage of the MOSFET. The InGaAs MOSFET exhibited a well-behaved pinch-off property with a drain current over 10 mA when the gate overdrive was 2 V. The red curves show the output characteristics of the MOSFET when applying a supply voltage VDD through the lateral PIN junction of the modulator. Since a voltage drop occurred owing to the turn-on voltage of the lateral PIN junction, we observed a drain voltage offset in the output characteristics. Finally, we evaluated the phase shift of the InGaAsP optical modulator directly driven by the InGaAs MOSFET. Figure 11(c) shows the phase shift as a function of a Vg – Vth for the InGaAs driver MOSFET with VDD of 1 V. We chose 1 V for VDD, which was a typical value for state-of-the-art Si optical modulator driven by CMOS circuits. From Fig. 11(c), that the phase shift was approximately linear with respect to the gate voltage. We obtained a π phase shift with Vg of approximately 1 V. Thus, we successfully gave a proof-of-concept demonstration of the monolithic electronic-photonic integration capability of the III-V CMOS photonics platform.
Fig. 11 (a) Schematic circuit diagram of InGaAsP optical modulator integrated with InGaAs driver MOSFET, (b) output characteristics of InGaAs driver MOSFET measured with VD or VDD, and (c) phase shift of InGaAsP optical modulator directly driven by InGaAs MOSFET.
4. Conclusion
In this study, we successfully demonstrated the monolithic integration of an InGaAsP optical modulator and InGaAs driver MOSFET on a III-V CMOS photonics platform. By performing pre-bonding annealing, we obtained a void-free III-V-OI wafer. During Zn diffusion for p-type doping, the delamination of the bonded III-V layer was effectively suppressed by reducing the thermal stress from the Zn-doped SOG. In conjunction with Ni-InGaAsP alloy, a low-resistivity lateral PIN junction along an InGaAsP rib waveguide was successfully fabricated. As a result, we successfully drove a carrier-injection InGaAsP MZI optical modulator using monolithically integrated InGaAs driver MOSFETs. Since InGaAs has high electron mobility, the III-V CMOS photonics platform enables high-speed and low-power electrical driver circuits based on InGaAs MOSFETs for LDs, modulators, PDs, and other active components.
Funding
Japan Society for the Promotion of Science (JSPS) Grants-in-Aid for Scientific Research (Grant No. JP26709022).
References and links
1. C. Kachris and I. Tomkos, “A Survey on Optical Interconnects for Data Centers,” IEEE Comm. Surv. Tutor. 14(4), 1021–1036 (2012). [CrossRef]
2. R. Nagarajan, M. Kato, J. Pleumeekers, P. Evans, D. Lambert, A. Chen, V. Dominic, A. Mathur, P. Cchavarkar, M. Missey, A. Dentai, S. Hurtt, J. Back, R. Muthiah, S. Murthy, R. Salvatore, S. Grubb, C. Joyner, J. Rossi, R. Schneider, M. Ziari, F. Kish, and D. Welch, “Single-chip 40-channel InP transmitter photonic integrated circuit capable of aggregate data rate of 1.6 Tbit/s,” Electron. Lett. 42(13), 771–773 (2006). [CrossRef]
3. R. Nagarajan, J. Rahn, M. Kato, J. Pleumeekers, D. Lambert, V. Lal, H.-S. Tsai, A. Nilsson, A. Dentai, M. Kuntz, R. Malendevich, J. Tang, J. Zhang, T. Butrie, M. Raburn, B. Little, W. Chen, G. Goldfarb, V. Dominic, B. Taylor, M. Reffle, F. Kish, and D. Welch, “10 Channel, 45.6 Gb/s per channel, polarization-multiplexed DQPSK, InP receiver photonic integrated circuit,” J. Lightwave Technol. 29(4), 386–395 (2011). [CrossRef]
4. M. Smit, X. Leijtens, H. Ambrosius, E. Bente, J. van der Tol, B. Smalbrugge, T. de Vries, E.-J. Geluk, J. Bolk, R. van Veldhoven, L. Augustin, P. Thijs, D. D’Agostino, H. Rabbani, K. Lawniczuk, S. Stopinski, S. Tahvili, A. Corradi, E. Kleijn, D. Dzibrou, M. Felicetti, E. Bitincka, V. Moskalenko, J. Zhao, R. Santos, G. Gilardi, W. Yao, K. Williams, P. Stabile, P. Kuindersma, J. Pello, S. Bhat, Y. Jiao, D. Heiss, G. Roelkens, M. Wale, P. Firth, F. Soares, N. Grote, M. Schell, H. Debregeas, M. Achouche, J.-L. Gentner, A. Bakker, T. Korthorst, D. Gallagher, A. Dabbs, A. Melloni, F. Morichetti, D. Melati, A. Wonfor, R. Penty, R. Broeke, B. Musk, and D. Robbins, “An introduction to InP-based generic integration technology,” Semicond. Sci. Technol. 29(8), 083001 (2014). [CrossRef]
5. M. Takenaka and Y. Nakano, “InP photonic wire waveguide using InAlAs oxide cladding layer,” Opt. Express 15(13), 8422–8427 (2007). [CrossRef] [PubMed]
6. M. Takenaka, M. Yokoyama, M. Sugiyama, Y. Nakano, and S. Takagi, “Ultrasmall arrayed waveguide grating multiplexer using InP-based photonic wire waveguide on Si wafer for III-V CMOS photonics,” in Optical Fiber Communication Conference, OSA Technical Digest (Optical Society of America, 2010), paper OThS5. [CrossRef]
7. M. Takenaka, M. Yokoyama, M. Sugiyama, Y. Nakano, and S. Takagi, “InGaAsP photonic wire based ultrasmall arrayed waveguide grating multiplexer on Si wafer,” Appl. Phys. Express 2(12), 122201 (2009). [CrossRef]
8. M. Takenaka, M. Yokoyama, M. Sugiyama, Y. Nakano, and S. Takagi, “InGaAsP grating couplers fabricated using complementary-metal-oxide-semiconductor-compatible III-V-on-Insulator on Si,” Appl. Phys. Express 6(4), 042501 (2013). [CrossRef]
9. J. Van der Tol, R. Zhang, J. Pello, F. Bordas, G. Roelkens, H. Ambrosius, P. Thijs, F. Karouta, and M. Smit, “Photonic integration in indium-phosphide membranes on silicon,” IET Optoelectron. 5(5), 218–225 (2011). [CrossRef]
10. Y. Ikku, M. Yokoyama, O. Ichikawa, M. Hata, M. Takenaka, and S. Takagi, “Low-driving-current InGaAsP photonic-wire optical switches using III-V CMOS photonics platform,” Opt. Express 20(26), B357–B364 (2012). [CrossRef] [PubMed]
11. Y. Cheng, Y. Ikku, M. Takenaka, and S. Takagi, “InGaAs MSM photodetector monolithically integrated with InP photonic-wire waveguide on III-V CMOS photonics platform,” IEICE Electron. Express 11(16), 20140609 (2014). [CrossRef]
12. L. Shen, Y. Jiao, W. Yao, Z. Cao, J. P. van Engelen, G. Roelkens, M. K. Smit, and J. J. G. M. van der Tol, “High-bandwidth uni-traveling carrier waveguide photodetector on an InP-membrane-on-silicon platform,” Opt. Express 24(8), 8290–8301 (2016). [CrossRef] [PubMed]
13. S. Matsuo, T. Fujii, K. Hasebe, K. Takeda, T. Sato, and T. Kakitsuka, “Directly modulated buried heterostructure DFB laser on SiO2/Si substrate fabricated by regrowth of InP using bonded active layer,” Opt. Express 22(10), 12139–12147 (2014). [CrossRef] [PubMed]
14. D. Inoue, J. E. Lee, K. Doi, T. Hiratani, Y. Atsuji, T. Amemiya, N. Nishiyama, and S. Arai, “Room-temperature continuous-wave operation of GaInAsP/InP lateral-current-injection membrane laser bonded on Si substrate,” Appl. Phys. Express 7(7), 072701 (2014). [CrossRef]
15. J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature 479(7373), 317–323 (2011). [CrossRef] [PubMed]
16. A. Nainani, T. Irisawa, Z. Yuan, B. R. Bennett, J. B. Boos, Y. Nishi, and K. C. Saraswat, “Optimization of the Al2O3/GaSb interface and a high-mobility GaSb pMOSFET,” IEEE Trans. Electron Dev. 58(10), 3407–3415 (2011). [CrossRef]
17. Y. Nakakita, R. Nakakne, T. Sasada, M. Takenaka, and S. Takagi, “Interface-controlled self-align source/drain Ge p-channel metal-oxide-semiconductor field-effect transistors fabricated using thermally oxidized GeO2 interfacial layers,” Jpn. J. Appl. Phys. 50(1), 010109 (2011). [CrossRef]
18. M. Yokoyama, S. Kim, R. Zhang, N. Taoka, Y. Urabe, T. Maeda, H. Takagi, T. Yasuda, H. Yamada, O. Ichikawa, N. Fukuhara, M. Hata, M. Sugiyama, Y. Nakano, M. Takenaka, and S. Takagi, “III–V/Ge high mobility channel integration of InGaAs n-channel and Ge p-channel metal–oxide–semiconductor field-effect transistors with self-aligned Ni-based metal source/drain using direct wafer bonding,” Appl. Phys. Express 5(7), 076501 (2012). [CrossRef]
19. M. Yokoyama, R. Iida, Y. Ikku, S. H. Kim, H. Takagi, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, “Formation of III-V-On-Insulator structures on Si by direct wafer bonding,” Semicond. Sci. Technol. 28(9), 094009 (2013). [CrossRef]
20. J. Widiez, S. Sollier, T. Baron, M. Martin, G. Gaudin, F. Mazen, F. Madeira, S. Favier, A. Salaun, R. Alcotte, E. Beche, H. Grampeix, C. Veytizou, and J. S. Moulet, “300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart CutTM technology,” Jpn. J. Appl. Phys. 55, 04EB10 (2016). [CrossRef]
21. Y. Ikku, M. Yokoyama, N. Noguchi, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, and S. Takagi, “Low-crosstalk 2x2 InGaAsP photonic wire optical switches using III-V CMOS photonics platform,” in European Conference on Optical Communication (ECOC), paper P.2.19 (2013).
22. M. Noguchi, S. H. Kim, M. Yokoyama, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, and S. Takagi, “High Ion/Ioff and low subthreshold slope planar-type InGaAs tunnel field effect transistors with Zn-diffused source junctions,” J. Appl. Phys. 118(4), 045712 (2015). [CrossRef]
23. J. K. Park, M. Takenaka, and S. Takagi, “Low resistivity lateral P-I-N junction formed by Ni-InGaAsP alloy for carrier injection InGaAsP photonic devices,” J. Jpn. Appl. Phys. 55, 04EH03 (2016).
24. J. K. Park, J. H. Han, M. Takenaka, and S. Takagi, “InGaAsP variable optical attenuator with lateral P-I-N junction formed by Ni-InGaAsP and Zn diffusion on III-V on insulator wafer,” MRS adv. 1(48), 3295–3300 (2016). [CrossRef]
25. G. R. Zhou, M. W. Geis, S. J. Spector, F. Gan, M. E. Grein, T. T. Schulein, J. S. Orcutt, J. U. Yoon, D. M. Lennon, T. Lyszczarz, E. P. Ippen, and F. X. Karther, “Effect of carrier lifetime on forward-biased silicon Mach-Zehnder modulators,” Opt. Express 16(8), 5218–5226 (2008). [CrossRef]
26. P. Dong, S. Liao, H. Liang, R. Shafiiha, D. Feng, G. Li, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Submilliwatt, ultrafast and broadband electro-optic silicon switches,” Opt. Express 18(24), 25225–25231 (2010). [CrossRef] [PubMed]
27. H. C. Lin, W.-E. Wang, G. Brammertz, M. Meuris, and M. Heyns, “Electrical study of sulfur passivated In0.53Ga0.47As MOS capacitor and transistor with ALD Al2O3 as gate insulator,” Microelectron. Eng. 86(7-9), 1554–1557 (2009). [CrossRef]
28. J.-H. Han, F. Boeuf, J. Fujikata, S. Takahashi, S. Takagi, and M. Takenaka, “Efficient low-loss InGaAsP/Si hybrid MOS optical modulator,” Nat. Photonics 11(8), 486–490 (2017). [CrossRef]
29. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15(2), 430–436 (2007). [CrossRef] [PubMed]
30. S.-H. Kim, M. Yokoyama, R. Nakane, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, and S. Takagi, “Biaxially strained extremely-thin body In0.53Ga0.47As-on-insulator metal-oxide-semiconductor field-effect transistors on Si substrate and physical understanding on their electron mobility,” J. Appl. Phys. 114, 164512 (2013). [CrossRef]
