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Abstract
Optical properties of poly-silicon material are investigated to be integrated in new silicon photonics devices, such as capacitive modulators. Test structure fabrication is done on 300 mm wafer using LPCVD deposition: 300 nm thick amorphous silicon layers are deposited on thermal oxide, followed by solid phase crystallization anneal. Rib waveguides are fabricated and optical propagation losses measured at 1.31 µm. Physical analysis (TEM ASTAR, AFM and SIMS) are used to assess the origin of losses. Optimal deposition and annealing conditions have been defined, resulting in 400 nm-wide rib waveguides with only 9.2-10 dB/cm losses.
© 2018 Optical Society of America
1. Motivations
Silicon photonics based on Silicon-On-Insulator (SOI) technology is now providing industrial solutions for datacenter optical transceivers [1]. Silicon photonics shows high speed performances at low fabrication costs [2–4]. Modulation in silicon photonics usually employs electro-refraction effects, based on variations of free carrier concentration inside the waveguide (WG). Most of current silicon modulators are based on carrier depletion using different types of PN diodes [5–10]. However, these devices typically require above 1 mm active region length, which corresponds to power consumptions of a few pJ/bit. Capacitive modulators have been proposed as a way to reduce modulator power consumption, thanks to higher efficiency.
Capacitive modulators are currently under development in 300 mm-platform [11,12]. Their design requires the integration of a poly-silicon electrode, in order to insert a capacitor dielectric within the optical WG (Fig. 1). The poly-Si electrode overlaps with the propagating fundamental Transverse Electric (TE) mode, so obtaining a low loss optical material is critical for the performance of the modulator.
Fig. 1 Capacitive modulator cross-section and mode electric field propagating through the active region.
In this article, the optical properties of poly-Si and specifically its optical losses are investigated as a function of material deposition conditions and annealing. To this end, poly-Si on Insulator (POI) WGs are fabricated and characterized. During the POI substrate fabrication, poly-Si is processed by applying to the deposited Si several Solid Phase Crystallization (SPC) conditions [13,14]. The substrates are then patterned to generate optical devices in the poly-Si layer. Poly-Si passive circuits are finally characterized. The measurements are compared with complementary structural analysis, using Atomic Force Microscopy (AFM) and Transmission Electron Microscopy (TEM) ASTAR [15] characterization techniques.
2. Experiment
Intrinsic POI fabrication
On a bulk silicon substrate, a 1270 nm thick oxide is prepared using 600 nm thermal oxidation followed by 670 nm Chemical Vapor Deposition (CVD). Subsequently, various deposition conditions are evaluated using a Design of Experiment (DoE), to obtain 300 nm-thick silicon films in a conventional Low Pressure CVD (LP-CVD) reactor. The temperatures, pressures and silane (SiH4) gas flow rates used in the DoE are sorted as Table 1 columns, corresponding to standard (STD), High Temperature (HT), Low Temperature (LT) and Low Pressure (LP) samples. Optimal conditions are chosen in order to provide different layer phases from amorphous to poly-crystalline silicon. Chosen LT condition is an optimum in terms of uniformity, surface roughness and fabrication cost.
Table 1. Summary on intrinsic wafer process flow combinations: standard (STD) and High Temperature (HT) samples are processed with densification, half of Low Temperature (LT) and Low Pressure (LP) samples are not.
Different thermal anneals are then applied to crystallize the a-Si films (Table 1 rows). Three different annealing steps under inert atmosphere can be used and combined giving rise to 5 annealing conditions. A long anneal (1h) at 750 or 900°C is applied alone or combined with a subsequent spike anneal (S), leading to the combinations called “S, 750, 900, 750S and 900S”. Temperatures and durations are chosen among standard cleanroom capabilities in order to better optimize thermal budget for crystallization. To compensate for shorter annealing time (1h) as compared with LTA specified by Zhu [13], annealing temperature higher than the ones specified in [13] are selected to evaluate their comparative effects on SPC.
Consequently, POI substrates with different poly-Si layer deposition conditions and crystallization stages are obtained (Table 1). The samples are labeled based on the process conditions such as STD-750S, with corresponding deposition condition (e.g. STD) and crystallization condition (e.g. 750S, combination of a 750 °C long anneal 750 and a subsequent spike anneal S).
Passive process flow
Resulting POI substrates are processed to define rib WG of different lengths and extract poly-Si propagation losses (Fig. 2). This includes WG definition and isolation (2-step pattern) [16], gap-fill HDP-CVD oxide encapsulation and densification [17], and planarization. The densification step is a 9.5 h long anneal in a furnace, including a 30 min plateau at 1050 °C. Since densification is a high temperature step, that step is skipped for half of LT and LP wafers to ensure that the observed WG optical performances are related to the SPC anneal conditions and unrelated with densification anneal.
Fabricated rib WG dimensions are specified on the hereafter TEM micrograph (Fig. 3(a)). WG rib is 310 nm thick and 400 nm wide, and WG slab is 160 nm thick. Intra wafer layer thickness is very uniform across dies: below 1 nm poly-Si film thickness range, and around 5 nm slab thickness range.
The TE optical mode of POI WG, calculated using Lumerical software, is reported in Fig. 3(b). The 400 nm wide rib have optimal field confinement within the poly-Si region. Less than 9% of mode power is outside poly-Si waveguide, such that no distinction between bulk absorption and mode propagation losses is made. Buried Oxide Layer (BOX) thickness is 1270 nm, which is thick enough to prevent any propagation losses due to substrate leakage [16].
3. Optical propagation characterization
Wafers are characterized with a semi-automatic optical prober. The optical test structure is composed of a rib WG of varying length and grating couplers for 1.31 µm wavelength coupling to the fiber as input and output. Propagation losses are measured at peak wavelength through WG lengths of 1, 2 and 5 mm. Losses versus length slope extraction gives the propagation losses of poly-Si WGs across wafer. At least 12 chips are measured for each wafer with a representative mapping of selected dies. A ~1 cm edge exclusion is applied during fabrication.
Samples processed with complete process flow
The first result is that HT samples exhibit poor optical performances with optical propagation losses above 60 dB/cm. This justifies the interest for depositing amorphous silicon followed by SPC, from which much better optical performances can be expected, as they are investigated in the next paragraphs.
Propagation losses for the three amorphous deposition conditions (LT, STD and LP) are plotted as a function of annealing scenario used prior to patterning, encapsulation and long densification anneal (Fig. 4(a)). Propagation losses at 1.31 µm are impacted by the thermal budget applied to the layer. For most samples, losses are lowered when combining a long anneal with spike anneal. Moreover, LP samples show generally higher losses than LT and STD samples. Single spike anneal results in WG propagation losses within the same range for whatever the deposition condition. It suggests that spike crystallization process differs from long anneal crystallization process.
Fig. 4 Propagation losses at 1.31 µm for a-Si deposited samples (error bars indicate 3-sigma ranges over 12 chips): (a) full process flow, (b) without densification anneal.
The characterization shows that the optimal SPC scenario is 750S. Samples combining deposition at 550 °C with 750 °C - 1 h and 1113 °C spike anneal (STD-750S) correspond to the lowest loss values of 11 dB/cm. We observe that increasing the long anneal temperature degrades performances. 900 and 900S samples have reached a thermal budget above which densification anneal start degrading the film quality.
We assume that the use of spike anneal S is less efficient when followed by densification anneal. This is consistent with the analysis reported by Zhu stating that Low Temperature Annealing (LTA) followed by a Rapid Thermal Annealing (RTA) is more efficient than the reverse [13]. This is investigated in the following section.
Amorphous deposited samples processed without densification anneal
In some samples, densification anneal after encapsulation has been removed from the process flow, in order to observe whether optical performances can be improved applying only SPC thermal budget (Fig. 4(b)).
Densification and CMP are skipped for some LT and LP samples (Table 1). Without densification anneal, we observe that it is preferable to apply a higher thermal budget, either by increasing long type anneal temperature from 750 °C to 900 °C, or by combining along anneal with a consecutive spike anneal. Without densification anneal, the lowest losses obtained are 9.2 dB/cm at 1.31 µm wavelength for the strongest 900S thermal budget available in this study. To the best of our knowledge, it is the best optical propagation losses measured in poly-Si single mode rib WGs at 1.31 µm.
Influence of implantation and activation
Doping of poly-Si is required to increase its electrical conductivity, thus decreasing capacitive modulator access resistance. 2 doped wafers have been fabricated in order to evaluate whether doping causes additional loss mechanisms in polysilicon apart from free carrier absorption.
Implanted boron atoms are characterized by Secondary Ion Mass Spectroscopy, resulting in uniform measured SOI doping level of 5.35x1017 atoms/cm3. Additional losses (referenced to corresponding intrinsic 900S samples) have been measured as 5dB/cm for p-type doping and 11dB/cm for n-type doping, independent on deposition condition of amorphous silicon phase. While boron induced free carrier absorption is lower than expected [21], likely explained by incomplete activation, phosphorus induced losses are higher than expected. We suspect electron effective mobility reduction due to impurity scattering and coulomb interactions with charged defects at grain boundaries [22,23].
4. Physical characterization and analysis
AFM surface characterization
Propagation losses can originate from WG roughness. Surface roughness resulting from LPCVD deposition is characterized by AFM after deposition (Table 2). Each deposition condition has a proper crystallite density embedded in the film from which surface roughness results. LT sample exhibits very smooth surfaces, typical of purely a-Si deposited films. However, HT sample surface roughness is much higher, characteristic of poly-Si deposited layers. For LP samples, and for STD to a lesser extent, the mean roughness measured in a 10x10 µm2 window shows larger values than for 1x1 µm2 scan due to the presence of isolated sparse nanocrystals distinguishable by AFM as bright spots (Fig. 5). Thus, it demonstrates that the deposition transition from amorphous to crystalline films is in our case encountered at around 550 °C, with the formation of more numerous and larger nanocrystals at lower pressure (LP).
Table 2. AFM surface characterization: RMS roughness (nm) as a function of deposition technique, for area or 1 and 100 µm2.
Fig. 5 AFM characterization after deposition (100µm2): (a) LT, (b) LP (1 µm2 and 100 µm2) and (c) HT surfaces.
Optical characterization after SPC shows that single spike anneal S results in higher losses for LT-S sample than LP-S sample losses. With the help of AFM characterization, we estimate that purely a-Si LT film needs a long duration anneal in order to produce crystallites while LP (and STD) samples already contain some embedded crystallites in the deposited film. Spike anneal seems too fast for LT-S sample to have proper grain formation. On the contrary, when some crystallites are already in the film, such high temperature is necessary to decrease defect density and consequently absorption of LP samples. Using a long time anneal at first may create competition between pre-existing crystallites and new grain formations within the amorphous phase. Resulting grain size is smaller such that a high density of grain joints cause high optical losses.
TEM & ASTAR characterization
The high surface roughness of HT samples measured by AFM is confirmed by TEM observations (Figs. 6(a) and 6(b)). Such high roughness could be the origin of poor light transmission as measured for the directly poly-Si deposited samples. TEM ASTAR [15,18] is a technique able to recover crystal information from diffraction patterns acquired from TEM lamella (Fig. 6(c)). HT-900 sample investigation shows a preferred grain growth along vertical direction (Fig. 6(d)). This increases the number of grain boundaries within the WG, which could also lead to additional anisotropic optical scattering.
Fig. 6 TEM cross-section of rib WG: (a) STD-750S with densification (amorphous deposition), (b) HT-900 with densification (polycrystalline deposition), (c) typical ASTAR diffraction pattern used for grain orientation mapping and showing amorphous halo characteristics and (d) ASTAR reconstruction (HT-900 sample with densification).
TEM ASTAR cross-sections for full process flow samples are shown for single step (750) and two step annealing (750S) (Figs. 7(a) and 7(b)). The 3-5 dB/cm loss discrepancies cannot be explained by neither grain size nor grain orientation. Looking at random diffraction patterns across TEM sample (Fig. 6(c)), a-Si halo is always present inside grains and at grain boundaries. It corresponds to some crystallinity disorder [19], even for 750S sample. Involved optical absorption mechanisms are well described in literature [20,22]. Lattice defects allow trapping of free carriers at energy levels in the bandgap. Surface defect levels are generally measured near midgap. This creates non radiative recombination of free carriers above c-Si bandgap wavelength (1.1 µm). 750S samples seem less impacted by grain boundary optical scattering.
Fig. 7 ASTAR cross section: (a) STD-750 sample with densification, (b) STD-750S sample with densification, (c) LT-900S sample without densification.
Samples fabricated without densification anneal and characterized by ASTAR confirm that absorption is not clearly correlated to grain size [14]. Indeed, we cannot observe major grain size evolutions among samples with diverse propagation performances (Fig. 7).
5. Conclusion
State-of-the-art poly-Si propagation losses in rib WGs at 1.31 µm are demonstrated. The study shows that 525 °C a-Si deposition followed by a two-step SPC anneal (750 °C 1 h and 1113 °C spike) is optimal and thermal budget tolerant with poly-Si propagation losses below 1 dB/mm. Higher temperature deposition increases deposition rate but at the detriment of higher measured propagation losses. We can extrapolate our measurement in order to state that increasing the deposition temperature to 550°C will give comparable optimal optical performances. The advantage is also to double the deposition time, a competitive interest for capacitive modulator integration with thick (600 nm are needed) amorphous layer deposition.
We see that for SPC samples (deposited as amorphous film), grain size is not significantly sensitive to thermal budget. However, propagation losses are decreased with optimal thermal budget. It is expected to come from decreased defect density, especially at grain interfaces.
Complementary studies may be interesting to lead as a perspective to this result. Firstly, electrical measurements of the doped wafers can give insight on doping density and possibly on free carrier effective mobility in order to correlate optical measurements. In our study, patterning is done after crystallization, because anisotropic dry etching is assumed to be insensitive to neither grain orientations nor grain interfaces. It can be confirmed by carrying crystallization after encapsulation rather than before patterning.
Reasonable losses in poly-Si WGs are obtained using traditional tools available in CMOS production lines and the method is currently applied to the fabrication of capacitive modulators as part of the active WG. Nonetheless, the study shows that the material can potentially be interesting for 3D photonic applications [24].
Funding
European project Cosmicc (H2020-ICT-27-2015-688516)
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