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Abstract
We experimentally demonstrate the first all-optical Ternary-Content Addressable Memory (T-CAM) cell that operates at 10Gb/s and comprises two monolithically integrated InP Flip-Flops (FF) and a SOA-MZI optical XOR gate. The two FFs are responsible for storing the data bit and the ternary state ‘X’, respectively, with the XOR gate used for comparing the stored FF-data and the search bit. The experimental results reveal error-free operation at 10Gb/s for both Write and Ternary Content Addressing of the T-CAM cell, indicating that the proposed optical T-CAM cell could in principle lead to all-optical T-CAM-based Address Look-up memory architectures for high-end routing applications.
© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
The advent of new internet applications, mainly the video streaming and the Internet of Things (IoT), has reshaped the requirements of internet usage, demanding more bandwidth with low latencies and stimulating an unprecedent growth of internet data traffic [1]. In this regime, photonics technologies have been heralded as the key technology to overcome the limitations of electronics in order to boost operational data rates at higher speeds. Starting with the replacement of electronic with optical links in Wide Area Networks (WAN), optical technologies have gradually penetrated the field of DataCenters (DCs) and are currently the dominant interconnect technology in intra-Data Center (DC) communications, offering low-cost and low-energy modules with high data rates. The growing maturity of photonic integration technologies has already managed to release a whole new class of optical transceivers with data rates up to 200 Gb/s [2], gradually entering also the field of optical packet switch implementations with remarkable layouts already demonstrated to allow for low-energy and low-latency setups [3].
However, even if optics are currently on the verge to conquer the packet switch domain for DataCenter routing, Address Look-Up (AL) continues to be a traditional stronghold of electronics mainly due to the unavailability of reliable optical memory solutions and the complete absence of optical look-up table implementations. With electronic AL tables operating, however, still at speeds of only up to a few hundreds of MHz [4], the constant increase in optical switch i/o data rates will yield severe latency and energy overhead during forwarding operations. AL operations are executed during the translation of the destination IP address of an incoming packet to the router output port in order to forward the packet to the appropriate destination. As the mismatch between optical i/o and electronic AL speeds grows [2], forwarding has to incorporate additional SerDes and interconnect hardware for parallelizing the optical addresses and expediting their processing by electronic circuitry.
At the early-dawning of the Internet, AL operations were based on electronic Random-Access Memories (RAMs), however the need for multiple memory-content accesses during the IP search operation increased rapidly the searching time. This rendered multi-cycle memory-search operations as impractical, requiring faster AL operations, ideally to be completed within one clock cycle [4]. This led to the emergence of electronic CAMs that allowed one-clock cycle search operations and reduced searching times. The need for variable IP prefix length that implement subnet masks with wildcard “X” bits enforced the insertion of a third memory-state in CAMs to facilitate the Ternary memory-operation, yielding to T-CAMs. Early T-CAM demonstrations built on 250nm CMOS nodes supported one-clock cycle operation at 260MHz [5]. By further shrinking the width of electronic gates down to 28nm, T-CAMs achieved operation speed-up only up to 400MHz [6], while the use of more complex-parallel architectures, such as the 4x400MHz T-CAM [7], seemed as the only alternative for additionally boosting performance speed. More recently, a T-CAM cell based on Fin-FET transistors broke the limit of 1GHz [8], yet still relying on data-pattern dependent pre-fetching and pre-charging techniques. Designs of emerging-alternative electronic memory technologies based on ferroelectric Field-Effect-Transistors (FeFET) [9], nanomagnetic logic [10] or memristors [11], hold the promise for a better trade-off between low-power consumption and chip area occupancy but without raising any expectations for increased data-rates.
Most of the above T-CAM technologies are also under intense research focus for high-bandwidth electronic RAMs required both in the computing domain as well as in the AL setups for hosting the router output port forwarding information. RAM layouts have, however, already experienced some first speed and energy benefits when crossing photonics, since optics have already stepped-in by suggesting alternative optically-enabled memory-architectures with remarkable performance [12]. Following two decades of rapid developments, optical memories have achieved high-speed and low power demonstrations of optical FFs [13, 14], advancing their functionality also towards complete Static RAM [15] and Dynamic RAM [16] implementations. Considering the distinctive absence of a high-speed electronic CAM in the routing industry, we have recently demonstrated the first all-optical Binary-CAM cell [17] operating at 10Gb/s yet supporting only the states “0” and “1”. This work was later extended by presenting an architectural layout and simulation-based verification of a 4-bit Ternary CAM architecture [18] and a complete roadmap towards all-optical AL-table architectures [19] that can support also the ternary “X” state. However, an experimental demonstration of an optical T-CAM cell is still missing from the literature.
In this paper, we demonstrate experimentally an all-optical T-CAM cell performing at 10Gb/s and utilizing two monolithically integrated FFs built on an InP platform [14] and a SOA-MZI optical gate. The two FFs are responsible for storing the actual data bit and the ternary state “X” for the “Care/don’t care” functionality, respectively, while the SOA-MZI operates as an optical XOR logic gate comparing the data bit and the search bit. Experimental evaluation of both the Write and Ternary Content Addressing operations is presented at 10Gb/s, yielding error-free performance with 3dB and 4dB power penalty values, respectively. The 10Gb/s demonstrated T-CAM cell operation achieves a speed enhancement of almost an order of magnitude when compared with state of the art electronic counterparts [8], suggesting a high potential towards releasing similar speed enhancements for the complete AL functionality when scaling to multi-bit optical CAM and RAM setups.
2. T-CAM concept & cell layout
Towards storing the routing paths and performing hardware AL-lookup, routers utilize AL tables consisting of T-CAM cells. The typical layout of an AL table architecture is presented in Fig. 1(a), comprising a T-CAM and a RAM table inter-connected through an encoder/decoder circuit. The T-CAM table stores the list of IP prefixes of the router for fast comparison with the destination address and the RAM table maintains the respective router output port for each known route, as described in detail in [4,17,18]. In this architecture, the most crucial element of the AL-table is the T-CAM cell, which is responsible both for storing the 0, 1 or X bits of each IP prefix in the list as well as for performing the fast comparison. The most common layout of the electronic 16T XNOR T-CAM cell is presented in Fig. 1(b) [3], comprising two FFs: the TFF is responsible for storing the “0” or “1” data bit as this is being determined by the Set (TS) and Reset (TR) signals, with the second FF, referred to as XFF, being responsible for storing the special state “Care”/“Don’t Care”, as this is being determined by the XS and XR set-reset signals, respectively. Finally, the TFF and XFF output signals along with the searchline signal and its inverted value, are driven into a XNOR gate, where every search bit is compared with the corresponding stored bit of the T-CAM cell when the XFF is in the “Care” state and the result emerges at the matchline.
Fig. 1 (a) Address Look-up table, (b) Electrical T-CAM cell, (c) All-Optical T-CAM cell, (d) 2 Packaged InP FFs and a close-up view of a single chip
By adopting the main design principles of the electronic T-CAM cell, we have recently proposed and numerically investigated the architecture of the first all-optical T-CAM cell layout in [18] using two SOA-MZI-based optical FFs and a SOA-MZI-based optical XOR gate, as schematically illustrated in the conceptual layout of Fig. 1(c). By adopting this layout, we extend our previous works [17] [18] by demonstrating and evaluating experimentally the performance of an optical T-CAM cell architecture, employing two monolithically integrated InP flip-flops as the TFF and XFF storing units and a Silica-on-Silicon SOA-MZI device as the XOR gate [21]. The two fully packaged and pigtailed FFs used as the TFF and XFF during the experimental demonstration of the T-CAM and a close-up view of a single InP monolithically integrated FF chip are depicted in Fig. 1(d). Every FF chip has a footprint of only 6 × 2 mm2 using 1mm-long SOAs, while the two SOA-MZI switches of the FF were coupled via a 5mm long InP waveguide. Based on the analytical theoretical findings of [20], the 5mm coupling length forms one of the main speed determining factors of the optical FF allowing for theoretical speeds up to almost 40Gb/s provided that the SOA recovery time is lower than 25psec [20]. The two FF chips have been designed and fabricated during the multi-project wafer run of the EU-funded project PARADIGM [14] using library-based components.
T-CAMs can perform in two different operational regimes in order to support both the Content Addressing and Write operations. Content Addressing and Write functionalities comprise two discrete memory operations that performed at different time-slots and not simultaneously, as has been already known from the respective electronic TCAM circuitry [6, 22–24], suggesting that a Content Addressing operation can be done once the TCAM content has been set to one of its three possible legal states 0, 1 and X [6, 22–24]. During the Content Addressing operation, a fast parallel XOR-based comparison operation is performed across the stored data of the T-CAM table, targeting a fast match with the packet destination address of the incoming packet of the router. On the contrary, a Write operation is performed during network-topology changes, when the stored routing paths need to be dynamically reconfigured and new data have to written in the memory [23]. During Write operation, the AL operations are stalled and the router remains idle, implying that high-speed Write capabilities of the incorporated TFF and XFF modules are necessary in order to minimize the router downtime and avoid considerable latency-induced performance limitations [24].
3. Experimental setup and results for TCAM Write operation
Figure 2 depicts the experimental setup used for the evaluation of TFF and XFF write operation. Four CW beams at λ6 = 1549.3nm are injected into separate LiNbO3 modulators driven by respective Programmable Pattern Generators (PPGs), producing in this way the Set/Reset signals at 10Gb/s that are subsequently launched at the TS, TR, XS and XR inputs of the Optical T-CAM cell. Both the Set and Reset signals had a length of 256-bits each with NRZ-formatted pulses.
The two optical FFs that will be used as TFF and XFF, rely on identical InP monolithically integrated circuit configurations where two coupled SOA-MZI switches provide the master-slave operational mechanism [20]. The TFF is configured in master-slave operation by two CW beams at λ1 = 1552.51nm and λ2 = 1553.81nm, while its TS and TR ports are connected to the respective LiNbO3 modulators, responsible for the generation of TS and TR signals. The λ1-emitting output is amplified in an EDFA and filtered in Optical Band-Pass Filter (OBPF), and afterwards is driven to an oscilloscope (OSC) and Bit-Error-Rate Tester (BERT) for evaluation purposes. The XFF employed two CW beams at λ3 = 1546.46nm and λ4 = 1547.9nm for also setting the XFF in a master-slave operational scheme, with its Set/Reset signals being fed by the respective XS and XR ports. The λ3-emitting XFF output is amplified, filtered and evaluated as well as the TFF output. Polarization controllers are used throughout the setup for polarization adjustment.
The evaluation of TFF Write functionality takes place by launching the corresponding Set/Reset signals into the TFF at TS and TR ports, respectively, and monitoring the TFF stored content at the λ1-emitting output. The experimental results obtained in that case at 10 Gb/s are depicted in Fig. 3. Figures 3(a) and 3(b) illustrate the time traces of the TFF Set and Reset signals, respectively. Figure 3(c) illustrates the λ1-emitting TFF output denoted as “FF out” in the figure, while Fig. 3(d) depicts the corresponding eye-diagram of TFF output. Successful Write operation can be confirmed since the TFF alters its content and its respective FF out signal whenever a Set pulse follows a Reset pulse or a Reset pulse follows a Set pulse, proving the re-mapping capability of T-CAM cell at 10Gb/s.
Fig. 3 (a)-(d) TFF write operation time traces, (e)-(h) XFF write operation time traces, (i) Eye diagrams & BER measurements for both TFF & XFF write operation. Time division in Fig.(a)-(h): 200psec.
The evaluation of the XFF Write functionality is carried out by monitoring the XFF stored content at its λ3-emitting XFF output when the corresponding Set/Reset signals are forwarded to XS and XR ports, respectively. Figures 3(e) and (f) illustrate the time traces of the Set/Reset signals, respectively, while the Figs. 3(g) and (h) depict the XFF output time trace and eye diagram. Successful Write operation at 10Gb/s can be confirmed since the XFF content changes whenever a Set pulse follows a Reset pulse or a Reset pulse follows a Set pulse.
The BER performance of the TFF and XFF Write operations has been evaluated by means of the BER curves presented in Fig. 3(i), revealing error-free writing operation with a power penalty of 4dB. The extinction ratio of the TFF and XFF out eye diagrams was measured at 6.3dB, obtained for peak power values of 17.5dBm and 17.8dBm for the Set and Reset signals injected in the two FFs. SOA1 and SOA2 of the XFF and TFF were driven by 271mA and 278mA, respectively.
4. Experimental evaluation of Ternary Content Addressing operation
The experimental setup is illustrated in Fig. 4. Two CW beams at λ6 = 1549.3nm are injected into separate LiNbO3 modulators driven by respective Programmable Pattern Generators (PPGs), producing in this way the Set/Reset signals at 10Gb/s that are subsequently launched at the XS and XR inputs of the Optical T-CAM cell. Both the Set and Reset signals had a length of 256-bits each with NRZ-formatted pulses. The Search-Bit signal was generated by a CW laser beam at λ5 = 1551nm that was launched into a LiNbO3 modulator driven by a PPG to produce a 10 Gb/s NRZ signal with a 256-bit period. This signal was then injected into the optical T-CAM cell as the optical XOR gate control signal.
The optical T-CAM cell comprises two optical FFs serving as the TFF and XFF, respectively, and an additional SOA-MZI-based optical XOR gate. Both the TFF and the XFF rely on identical InP monolithically integrated circuit configurations where two coupled SOA-MZI switches provide the master-slave operational mechanism [20], while the SOA-MZI-based XOR gate consists of a Silica-on-Silicon layout as employed in [21]. The TFF is powered by two CW beams at λ1 = 1552.51nm and λ2 = 1553.81nm, while its λ1-emitting output is connected via an optical circulator to the XOR optical gate, after being amplified and filtered, in order to act as the second control signal to be compared with the Search-Bit. The XFF employed two CW beams at λ3 = 1546.46nm and λ4 = 1547.9nm for setting the XFF in a master-slave operational scheme, with its Set/Reset signals being fed by the respective XS and XR ports. The λ3-emitting XFF output is then connected via an optical circulator to the optical XOR serving as the gate input signal, after having been amplified in an EDFA and filtered in anoptical Bandpass Filter (OBPF). Finally, the XOR gate output emerging at the T-CAM cell output port is filtered at λ3 and launched into an oscilloscope (OSC) and Bit-Error-Rate Tester (BERT) for monitoring purposes and quality analysis. Polarization controllers are used throughout the setup for polarization adjustment.
The Ternary Content Addressing operation of the T-CAM cell at 10 Gb/s is obtained by employing the complete experimental setup as shown in Fig. 4 and the respective results are illustrated in Fig. 5. Figures 5(a)-(d) depict the results obtained when the TFF content equals “0”, while Figs. 5(e)-(h) include the results obtained when the TFF content is “1”. Figures 5(a) and 5(d) show the TFF content when being “0” and “1”, respectively, Figs. 5(b) and 5(f) depict the Search Bit stream signal and Figs. 5(c) and 5(g) illustrate the XFF output signal that feeds the SOA-MZI XOR gate in both cases of the TFF stored bit. Figures 5(d) and 5(h) present the corresponding T-CAM-cell-out signals, both of them carrying the XOR operation between the respective TFF and the Search Bit beams imprinted on the XFF data stream. Successful Ternary Content Addressing operation in both Figs. 5(d) and 5(h) can be confirmed by evaluating the T-CAM-cell-out signal when the XFF signal is “1” and “0”, corresponding to a “care” and “don’t care” state, respectively, and designated on the figure with a green- and red-shaded area, respectively. As long as the XFF signal is “1”, the T-CAM-cell-out carries a signal that is identical to the Search Bit stream when TFF equals “0”, while the inverted Search Bit is produced when TFF content equals “1”, in both cases confirming successful XOR operation between TFF and Search Bit. Whenever the XFF signal is “0” implying that the T-CAM cell is at its “X” state, the T-CAM-cell-out is always “0” irrespective of the TFF content value, suggesting successfully a matching case. Error-free Ternary Content Addressing operation was achieved for both cases of TFF content value having a 3dB power penalty at a 10−9 error rate, as revealed by the BER measurements presented in Fig. 5(i). The corresponding eye diagrams of the Search Bit and T-CAM-cell-out signals are shown as insets in Fig. 5(i), with the T-CAM-cell-out eyes exhibiting 6.3dB extinction ratio in the case of TFF = 0 and 5.9dB for TFF = 1. The results were obtained for Set/Reset signals entering the XFF with 17.5dBm and 17.8dBm peak power values, respectively, for average power levels of 7.4dBm and 10.4 dBm for the two CWs feeding the XFF, while the XFF SOA1 and SOA2 driving currents were 271mA and 278mA, respectively. The TFF was powered with CW average power levels of 8.1dBm and 9dBm with its SOA1 and SOA2 modules operating at a driving current of 250mA and 204mA, respectively.
Fig. 5 (a)-(d) T-CAM cell output time traces for TFF = 0, (e)-(h) T-CAM cell output time traces for TFF = 1, (i) BER measurements. Time division in Fig.(a)-(h): 200psec
5. Conclusion
We have experimentally demonstrated the first all-optical ternary-CAM cell exploiting two monolithically integrated InP FFs along with a XOR optical logic gate implemented by means of SOA-MZI. Error-free operation was achieved for both Ternary Content Addressing and Write operations at 10 Gb/s, achieving a close to one order of magnitude speed enhancement compared with state-of-the-art electronic T-CAMs and suggesting a high potential towards the deployment of high-speed all-optical T-CAM-based AL tables.
Funding
This work has been supported by the EU H2020 projects ICT-STREAMS (688172) and L3MATRIX (688544).
Acknowledgement
The authors would like to acknowledge Dr. Ronald Broeke from BrightPhotonics for mask-layouting, Dr. Francisco Soares from Heinrich-Hertz Institute for chip fabrication and Dr. Tolga Tekin from Fraunhofer IZM for the packaging of the InP FFs.
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