1. Introduction

Recently, as potential and promising components of photonic integrated circuits (PIC), mode converter and power splitter, realizing mode conversion and power splitting in the output ports respectively, continue to be investigated to meet the demand for greater transmission capacity. On the one hand, there are many schemes to design mode conversion, such as mode conversion in tapered submicron silicon ridge optical waveguides [1,2], tapered polymer single-mode waveguides for mode transformation [3], mode conversion in planar-dielectric separating waveguides [4], bilevel mode converter [5], mode conversion based on optical silicon waveguides of different sizes and types [6] and mode conversions in discontinuous taper [7,8]. Moreover, in mode division multiplexing systems, the mode multiplexer (MUX) can likewise achieve the functionality of mode conversion. The design schemes include asymmetric directional couplers [9–12], multimode interferometers [13,14], and asymmetric Y-junction [15,16] and so on. The existing designs for mode converters are effective in principle, but a drawback is the footprint of these devices may be extremely large, which may impede their widespread applicability. Driven by the requirement of highly PIC, other emerging advanced inverse design methods were used to realize nanophotonic devices, such as the direct-binary-search (DBS) algorithm [17–22], genetic algorithm [23–25], objective-first design [26–27] and deep learning [28–30]. Compared with conventional approaches, various computational optimization methods can not only avoid overdependence on intuition and experience of the designer but also search a full-parameter space [31,32]. Researchers have recently begun to employ them to overcome the limitation of footprint. A novel multimode and ultra-compact MUX with a footprint of only 2.4 µm × 3 µm, composed of a wide divergence angle asymmetric Y-junction, was proposed in [33]. The authors of [34] demonstrated an ultra-compact MUX for TE₀, TE₁, TE₂ and TE₃ modes with a footprint of only 5.4 µm × 6 µm. These structures occupied both compact footprints and excellent performance. On the other hand, power splitter has also shown great potential in optical interconnect systems. There are many power splitters designed by utilizing advanced optimization methods, including a planar photonic crystal waveguide Y-splitter by utilizing topology optimization [35], arbitrary-direction, multichannel and ultra-compact power splitters [36] and a power divider with arbitrary power ratios [37]. Actually, we often use a variety of devices to achieve efficient and high-speed transmission in the optical communication systems. It is not difficult to find that simultaneously using power splitter and mode converter can take up more space, and loss of each device necessarily causes the superposition of loss. As a result of these, the whole photonic system may suffer from the limitations of large footprint and high loss. Therefore, the device with multipurpose design goals becomes more expected.

As mentioned above, inverse design algorithms are beneficial to the design of compact devices, compared with conventional approaches. As one of the crucial algorithms, DBS algorithm, detailed in [38], has drawn more and more attentions recently, such as power splitter [39–41], MUXs [33,34], wavelength demultiplexer [20] and polarization splitter-rotator [19,38]. Unfortunately, based on our experience, optical devices optimized by DBS can not usually yield acceptable results. The circle voids instead of square voids as the basic shapes can avoid the sharp angles and be much easier in fabrication [39]. There is also a high chance for DBS algorithm to become stuck in a local convergence, instead of the optimal global solution. The appropriate manually-set initial pattern can effectively avoid local convergence in our previous work [36]. Meanwhile, we have come up with the other challenge in [36] that further decreasing footprint brings about high loss by comparing two power splitters with the same functionality and different footprints. In terms of this issue, we present a unique method, a hugely modified version of DBS algorithm called rotatable DBS (RDBS), to overcome the limitation of footprint and unleash enormous potential to maintain, or even improve the performance.

In this paper, we design and theoretically demonstrate highly compact and efficient 1 × 2 mode converters with multipurpose design goals on a 220 nm-thick top silicon-on-insulator (SOI) platform based on the RDBS, which can simultaneously complete power splitting and mode conversion. By 3D fine difference time domain (3D FDTD) solutions, the 1 × 2 mode converter that converts TE₀ mode into TE₁, with a footprint of 2.7 µm × 2.4 µm, exhibits the excess loss (EL) of 0.1 - 0.2 dB (TE₁ mode), crosstalk (CT) of lower than -20.6 dB (TE₀ mode) and reflection loss (RL) of lower than -19.5 dB (TE₀ mode) from 1500 nm to 1600 nm, respectively. In addition, the 1 × 2 mode converter that transforms TE₀ mode into TE₂ occupies the footprint of 3.6 µm × 3 µm. The EL is 0.3 - 0.4 dB (TE₂ mode) over 100 nm bandwidth at the centered wavelength of 1550 nm, the CTs are lower than -17.5 dB (TE₁ mode) and -25.1 dB (TE₀ mode), and the RL is lower than -18.3 dB (TE₀ mode). We believe our multifunctional devices and the modified algorithm will play an important foundation for high-density PIC.

2. Methods

In this section we provide an introduction to the RDBS method, which is employed to optimize the structures presented in this paper. The main idea of RDBS algorithm is to add a calculation of rotational dimension based on the DBS algorithm. The nanophotonic devices are designed in a planar binary structure, which is composed of two different materials with different refractive indices, such as silver and air, silicon and silica and some copolymers. We often implement structure on a 220 nm-thick top SOI platform, because of a high refractive index difference between silicon and silica [38]. The coupling region is divided into many nanoscale elements as the basic pixels, whose sizes are equal and determined by their total number and the footprint of device. According to design and fabrication requirements, the pixels can be set with specified or arbitrary shapes, such as rectangle in Fig. 1(a), triangle in Fig. 1(b), circle in Fig. 1(c) and other polygons. However, when the circle is used, the pixel does not need to be rotated, because it is still the same shape as the beginning when rotated around its center. Besides, we need to control the distance between the basic pixels within the fabrication capacity.

 

Fig. 1. The different shapes of basic pixel. (a) The rectangular pixels in silicon layer. (b) The triangular pixels in silicon layer. (c) The circular pixels in silicon layer.

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The building process for RDBS algorithm is shown in Fig. 2. The steps in RDBS mainly include deleting pixel in green parts, adding pixel in blue parts and selecting optimality in the gray part. The first two steps mean switching the state of pixel which includes silicon and air in our work. In other word, deleting pixel and adding pixel stand for no etching and a shaped void etched into silicon, respectively.

 

Fig. 2. The flow chart of RDBS algorithm

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• Deleting pixel

This step is the same as the process of DBS algorithm. In green parts, we delete the current pixel, which means the pixel is fully filled with silicon. Then the function of figure-of-merit (FOM) that responds to performance of device is calculated. It's very convenient for us to control the structure by codes.

• Adding pixel

This step is different from the process of DBS algorithm, and the primary selling point of RDBS as well. In blue parts, we add a shaped pixel, which means the pixel is fully filled with air. Then the pixel is rotated to a set angle, and the FOM is calculated. For every rotation, the algorithm calculates the FOM each time, until the pixel returns to original angle. As mentioned earlier, the pixels can be set with specified or arbitrary shapes, according to the actual demand. Consequently we can add multi-shape pixels and obtain the corresponding values of FOM by repeating the same way.

• Selecting optimality

Through the first two steps, we saved many values of FOM that correspond to the pixels with multi-dimension parameters (air or silicon, shape and rotation) one by one. By comparing all values of FOM, we select the optimal one in the gray part and retain corresponding pixel. Here one basic pixel was searched. We calculate all the basic pixels repeatedly until the function error range or performance fulfills practical request.

We earlier mentioned further decreasing footprint brings about high loss by comparing two power splitters with the same functionality and different footprints [36]. We can try to overcome this challenge to prove the tremendous advantage of RDBS algorithm. In order to carry out a convincing assessment, we use RDBS and early reported DBS algorithms to design 1 × 2 power splitters under coincident criteria and compare the loss of each port. There is no doubt that the two 1 × 2 power splitters must occupy almost equal and greatly ultra-compact footprints, the same functionality and the initial patterns designed by the same way. The trouble we face is that it is not easy to keep the same parameters of pixels due to the calculations of rotation in RDBS algorithm. By summarizing the efforts of researchers [21,33,34,35,36,39,40,41,42], the empirical truth is that the shortest distance between adjacent pixels is not smaller than 60 nm. Besides, the depths of pixels in these devices should be equal.

We implement structures with 500 nm-wide input waveguide and two 500 nm-wide output waveguides on a 220 nm-thick top SOI platform. Figure 3(a) and Fig. 3(e) display the initial patterns of DBS and RDBS algorithms which are designed by the same method proposed in our previous work [36]. As is shown in Fig. 3(b), the coupling region of 2.04 µm × 1.56 µm designed by DBS algorithm is divided into 17 × 13 pixels. The size of each pixel is 120 nm × 120 nm. The radius and etching depth of each air hole are 45 nm and 220 nm, respectively. We can easily calculate the shortest distance of 60 nm between adjacent air holes in Fig. 3(d). RDBS algorithm is adopted to design the power splitter with a footprint of 2.1 µm × 1.5 µm in Fig. 3(f). In the coupling region, 14 × 10 rectangular pixels are evenly distributed which can adjust the distribution of light field by self rotation. Obviously, the total number of 3D FDTD simulation is proportional to the number of possible rotation angles. In order to reasonably control design efficiency and time cost, every time the rectangular pixel rotates 10 degrees, RDBS algorithm calculates it once. The size and depth of each is 104 nm × 60 nm and 220 nm respectively. As is shown in Fig. 3(d), when the diagonals of adjacent rectangular pixel coincide with a straight line (black line), the distance of about 60 nm between adjacent pixels is the shortest. Here, these two devices meet the criteria of comparison we mentioned above. By 3D FDTD simulations, it is easy to find the truth, reflected by optical field distributions in Fig. 3(c) and Fig. 3(g), that the structure achieved by RDBS algorithm has a better ability to realize power splitting than another one calculated by DBS algorithm. Meanwhile, the results in Fig. 3(h) indicate that the transmittances of two devices are greatly uniform because of their symmetrical structures. However, the transmission curve optimized by RDBS algorithm is less volatile than that one optimized by DBS. The devices, designed by DBS and RDBS algorithm respectively, exhibit the loss of each port of less than 4.5 dB and 3.4 dB from 1500 nm to 1600 nm.

 

Fig. 3. The simulated results of comparing DBS algorithm with RDBS. (a) and (e) The initial patterns of DBS and RDBS algorithms. (b) and (f) The top views optimized by DBS and RDBS algorithms. (c) and (g) The corresponding light field distributions. (d) The shortest distances between adjacent pixels in DBS and RDBS algorithms. (h) The simulated spectral responses of transmission loss for different algorithms.

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The comparisons and summaries for various power splitters are shown in Table 1. These data display the performance of our devices visually. If we compare column 3 with column 4, we easily find the issue of DBS that further reducing the footprint brings about bad performance. Compared column 2 with column 4, we find that the losses are approximately equal, but the device achieved by RDBS occupies much more compact footprint than the device designed by DBS. What is more, if the footprints are almost equal, the low loss in column 2 is in sharp contrast to that in column 3. We here may draw the conclusion that RDBS can provide more potentials for ultra-compact and greatly effective device than DBS.

Table 1. Performance comparison of different power splitters

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Based on pixelated structure, DBS algorithm can enable unique and efficient integrated-photonic applications in a very compact area by controlling a large scale of effective index engineering [31,39,43,44]. Similarly, RDBS algorithm realizes device through the same principle. The difference is that RDBS adds a calculation of rotational dimension to the every pixel. This of course increases time cost. However, this issue can be availably dealt with by adjusting the angle step of rotation and introducing multi-node parallel computing. In this case, the inverse design process is performed on the CPU partition of the National Supercomputing Center in Guangzhou (NSCC-GZ). The total computation times cost for the devices optimized by DBS and RDBS, is around 4 hours and 45 hours respectively on one node with two Intel Xeon E5-2692 v2 processors, 64 GB of RAM. By contrast to the unacceptable loss in column 3, it is necessary to take efficient time to optimize by utilizing RDBS.

3. 1 × 2 mode converters designs

After mastering RDBS, we design the 1 × 2 mode converters, with the functionalities of both power splitting and mode conversion, on a 220 nm-thick top SOI platform and use the 3D FDTD simulations to optimize. We can make a good use of a symmetric coupling region to realize great uniformity from 1500 nm to 1600 nm. In addition to getting the strict 50:50 splitting ratio, we can also save at least half of the computing time. To begin with, as shown in Fig. 4(a), the 1 × 2 mode converter that converts TE₀ mode into TE₁ is composed of a 500 nm-wide input waveguide, two 900 nm-wide output waveguides and coupling region of 2.7 µm × 2.4 µm area. We set the gap between the output waveguides to 900 nm. In the coupling region, 18 × 16 rectangular air holes are evenly arranged. The size of each hole is 104 nm × 60 nm, and the etching depth of each is 220 nm. After setting the initial pattern, we determine the inversion states (air or silicon) and rotation angles of all the basic pixels by using the RDBS. As we expect, the optical field distribution, shown in Fig. 4(b), displays that TE₀ mode launched from the input waveguide is converted to 1 × 2 TE₁ mode with high efficiency and mode purity in the output waveguides. Furthermore, the simulated spectral responses of this device for different ports are plotted in Fig. 4(c). Here, the EL and CT are defined as:

 

Fig. 4. The simulated results of 1 × 2 mode converter of dual-mode version. (a) The top view. (b) The corresponding light field distribution. (c) The simulated spectral responses of the transmission loss.

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Here we have explained the design process of RDBS algorithm by realizing 1 × 2 mode converter of dual-mode version. The RDBS algorithm itself has no limitation on device design. The 1 × 2 mode converter that transforms TE₀ mode into TE₂ can also be achieved by using single rectangular pixel. However we choose two different-shape pixels (triangular and rectangular pixels) as the basic units to accomplish this device so as to investigate the flexibility of selecting shapes in RDBS algorithm and etching errors caused by sharp corners or complicated acute angles. As is shown in Fig. 5(a), the coupling region of device is 3.6 µm × 3 µm where the 24 × 20 initial basic pixels are placed. This coupling region simultaneously contains triangular pixel of 104 nm × 60 nm and regularly triangular pixel with side length of 104 nm. Similarly, the depth of each pixel is set to 220 nm. The input waveguide and output waveguide widths are set to 500 nm and 1.3 µm to provide mode conversion, and the separation of output ports is set to 1 µm. The distribution of optical field in Fig. 5(b) vividly embodies this functionality of power splitting and mode conversion. Figure 5(c) describes the simulated spectral responses for different ports. The EL of this device is 0.3 - 0.4 dB (TE₂ mode) from 1500 nm to 1600 nm. At the same time, the CTs are lower than -17.5 dB (TE₁ mode) and -25.1 dB (TE₀ mode), and the RL is lower than -18.3 dB (TE₀ mode).

 

Fig. 5. The simulated results of 1 × 2 mode converter of three-mode version. (a) The top view. (b) The corresponding light field distribution. (c) The simulated spectral responses of the transmission loss.

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Obviously, the pixels, in Fig. 4(a) and Fig. 5(a), provide a startling contrast in shape. The facts prove that selecting pixel shape is flexible enough in RDBS algorithm. The method we propose have great potential to design complex structures with multi-shape and multi-rotation pixels according to actual requirements.

4. Tolerance to fabrication errors

As we all know, the expansion or contraction of etched pattern contour caused by over or under etching is one of the typical etching errors. Here we theoretically study the impact of variations of pixel side on 1 × 2 mode converter that converts TE₀ mode into TE₁. Figure 6 depicts the spectral responses under the variations of rectangular-pixel side from -10 nm to 10 nm. As is shown in Fig. 6(a), the transmission curve (blue dashed line) fluctuates greatly after imposing variation of 10 nm to the each side of rectangular holes, but the all efficiency drops are within 1.2 dB. The variations of pixel side have a powerful influence on CTs and RLs in Fig. 6(b) and Fig. 6(c), but the CTs and RLs can still be maintained lower than -13.2 dB and -14.1 dB under the variations from -10 nm to 10 nm.

 

Fig. 6. The analysis of fabrication tolerance for 1 × 2 mode converter of dual-mode version. (a) - (c) The simulated spectral responses under the variations of pixel side from -10 nm to 10 nm.

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Although the expansion or contraction of etched pattern contour is considered, the fabrication tolerance of round corner effect is another etching error. Thus the three-mode device, 1 × 2 mode converter that transforms TE₀ mode into TE₂, was realized with triangular and rectangular pixels. The triangular pixel that has acute angle in black dashed line of Fig. 7(a) is different with rectangular pixel. We can explore the fabrication tolerance of round corner effect as well as the flexibility of selecting pixel shape in RDBS algorithm. We assumed a rounding radius at the corner in blue dashed line. The ELs, CTs and RLs of this structure with different rounding radii (0 nm, 10 nm, 20 nm), are described in Fig. 7(b), Fig. 7(c) and Fig. 7(d), respectively. We can obviously see that the fabrication error of round corner effect has little influence on the performance. When the rounding radius is set to 20 nm, this device still exhibits the EL of less than 0.6 dB (TE₂ mode), CT of lower than -13.1 dB and RL of lower than -17.5 dB, respectively.

 

Fig. 7. The analysis of fabrication tolerance for 1 × 2 mode converter of three-mode version. (a) The sharp corner and rounding radius of triangular pixel. (b) - (d) The simulated spectral responses considering the fabrication tolerance of different rounding radii (0 nm, 10 nm and 20 nm).

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5. Conclusion

In this paper, we innovatively propose a rotatable direct-binary-search algorithm, which can achieve a novel structure with multi-shape and multi-rotation pixels. Meanwhile, we design and theoretically demonstrate multifunctional 1 × 2 mode converters, simultaneously occupying power splitting and mode conversion, on a 220 nm-thick top silicon-on-insulator platform by utilizing this new algorithm. The 1 × 2 mode converter that converts TE₀ mode into TE₁, with a footprint of 2.7 µm × 2.4 µm, exhibits the excess loss of 0.1 - 0.2 dB (TE₁ mode), crosstalk of lower than -20.6 dB (TE₀ mode) and reflection loss of lower than -19.5 dB (TE₀ mode) from 1500 nm to 1600 nm. The 1 × 2 mode converter that transforms TE₀ mode into TE₂ occupies the footprint of 3.6 µm × 3 µm. The excess loss is 0.3 - 0.4 dB (TE₂ mode) in the wavelength range of 1500 - 1600 nm, the crosstalks are lower than -17.5 dB (TE₁ mode) and -25.1 dB (TE₀ mode), and the reflection loss is lower than -18.3 dB (TE₀ mode). What is more, the fabrication tolerances caused by both expansion or contraction of etched pattern contour and round corner effect are also investigated. Our innovative approach can easily be applied to most photonic devices to drastically decrease their footprints and greatly develop their performance. At the same time, the 1× 2 mode converters, proposed in our work, could be a potential and promising component for future all optical networks.