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Abstract
We demonstrate low-loss and broadband light transition from III-V functional layers to a Si platform via two-stage adiabatic-crossing coupler waveguides. A 900-µm-long and 2.7-µm-thick III-V film waveguide consisting of a GaInAsP core and InP cladding layers is transferred onto an air-cladding Si photonic chip by the µ-transfer printing (µ-TP) method. An average optical coupling loss per joint of 1.26 dB is obtained in C + L telecommunication bands (1530-1635 nm). The correlation between alignment offset and measured optical coupling loss is discussed with the frequency distribution of µ-TP samples. We also performed a photoluminescence measurement to investigate the material properties in the GaInAsP layer to see if they are distorted by the strong bending stress produced during the pick-up and print steps of the µ-TP process. The peak intensity reduction of 80-90% and a wavelength shift of 0-5 nm (blue shift) were observed after the process. The series of fundamental studies presented here, which combine multiple analyses, contribute to improving our understanding of III-V/Si photonic integration by µ-TP.
© 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
The global market for modern data center networking is rapidly growing due to the huge increases in Internet Protocol traffic. This trend is expected to grow steadily, with traffic volume reaching over 20 zettabytes per year by the end of 2021. Si photonics and related ultra-compact photonic integrated circuits (PICs) play significant roles in meeting current demands owing their low-cost and high-volume producibility. However, the light source in PICs still presents major challenges in the integration process of heterogeneous materials, including III-V compound semiconductors. The development of the III-V hybrid bonded evanescent laser opened up the possibility of stable and efficient lasing on a Si-on-insulator (SOI) platform [1]. Since that breakthrough, various types of hybrid laser light sources have been developed and even installed in commercial products [2,3,4,5]. Over the last decade, optical circuit design and fabrication technologies in Si photonics have made a great success as an industry. The wafer-to-wafer and wafer-to-die bonding techniques are economical and promising ways to produce hybrid lasers. Particularly, the strengths of these techniques have proven to be effective in mass production, unless a variety of hybrid materials. In other words, the future high-density heterogeneous integration of different types of materials remains a challenge. Each wafer or die shares at least a few millimeters, but the devices actually needed are much smaller. From a different point of view, the large and thick piece of hybrid materials can result in damage and stress due to their thermal expansion mismatch with the target materials [6,7] (Note that this issues can be mitigated by recently reported low-temperature bonding below 150 °C with N2-plasma assistance [8]). To avoid these critical issues, µ-transfer printing (µ-TP) technology is gaining traction for future heterogeneous integration on the premise that it can minimize the amount of hybrid material at any location [9,10,11,12]. This advantage enables ultimate device performance through fully customized device manufacturing for hybrid materials, which will lead to a great improvement in productivity and economics. Another feature of the µ-TP is parallel printing. These advantages have already been confirmed in applications such as micro-LEDs [13,14] and high-performance electronic devices [15]. In the fields of integrated photonic circuits, while a distributed feedback laser (DFB) [16] and a tunable III-V-on-SOI laser light source [17] have recently been demonstrated through the µ-TP, the inter-layer light transition between the III-V waveguide to Si platform, and the µ-TP induced light emission degradation have not yet been fully characterized. Especially in the article on tunable lasers, the behaviors of multiple thresholds and instability in lasing, which are suspected to be caused by the multi-mode confinement and light coupling issues, are essential issues to be solved. In this paper, toward III-V light source integration with the µ-TP, we designed and characterized a high-efficiency coupling structure consisting of multi-step taper waveguides. The device design concept incorporates neither an adhesive layer (e.g., benzocyclobutene (BCB) [17,18,19]; Al2O3 [20]) nor a special thick SOI platform (e.g., 300-500 nm [4,18], including the epitaxial growth of poly-Si). A GaInAsP core with a photoluminescence (PL) wavelength at 1.2 µm was used instead of conventional 1.55-µm MQWs in the active III-V layers. Thus, we can accurately characterize the loss of the designed structure, as well as the influence of stress on the µ-TP by µ-PL method because the strong bending moment was predicted during the pick-up and print steps of the µ-TP process (i.e., detachment from the III-V substrate and bonding onto the Si substrate). Our potential target through this study is realizing narrow-linewidth lasers for recent advanced modulation formats, in which other hybrid functional devices such as broadband III-V modulators are simultaneously integrated onto a chip.
2. Device design and simulations
As shown in Fig. 1, we designed an inter-layer light transition between the III-V and Si photonic platforms with a two-stage adiabatic taper waveguide of III-V, which faces another adiabatic taper waveguide of Si. There are two requirements in device design for µ-TP, neither of which is common in wafer-to-wafer or die-to-wafer hybrid III-V/Si device integration. One is that steep projections (cf. taper structure) should be avoided because the wet sacrificial etching process or pick-up/print procedures in µ-TP may seriously damage them. The other is that the bonding area on the backplane of samples should be as large and smooth as possible to maximize the strength of bonding to the Si surface. Broadband and efficient light coupling with minimum light reflection are also essential for hybrid lasing properties. Contrary to taper waveguide designs in conventional bonding methods, we assumed a standard SOI platform and a bonding interface without extra adhesives (i.e., hydrophilic bonding).
Fig. 1. Schematic of III-V/Si hybrid integration configuration. The device consists of two-stage adiabatic tapers made of a III-V film and an underlying photonic platform with a one-stage adiabatic taper of Si.
Table 1 summarizes the material selection, including the thickness and refractive index values used in the device design. A mechanically robust structure is proposed with a side terrace region formed by an InP slab layer [see Fig. 2(b)], which is desirable under µ-TP-based fabrication process. The two-stage adiabatic tapers installed here to provide a smooth light transition from the III-V layers to Si waveguide toward a laser structure with vertical current injection. In the III-V region, a 270-nm-thick GaInAsP core with an InP rib-core and cladding layers on the top and bottom were grown on a 1-µm-thick AlInAs sacrificial layer. The composition of the GaInAsP core was selected for a peak emission wavelength at 1.2 µm for PL measurement. This material design allows us to characterize the light coupling efficiency without light absorption. Although all materials are non-doped, since we are focusing on the passive characteristics, it should be noted that the thickness parameters assigned to each layer are fully compatible with future laser fabrication processes with metal contacts. In terms of the target Si integration platform, to satisfy the specifications of the standard SOI available in most Si photonics foundries, we assumed Si and BOX layer heights of 220 nm and 3 µm for the device design.
Fig. 2. (a) Top view of the designed optical coupling structure with two-stage adiabatic tapers. (b) Cross-sectional views at dotted slice lines A, B, and C, respectively.
Table 1. Material information for stacked III-V layers and Si platform. The sacrificial layer (Layer 5) is etched off before µ-TP.
Figures 2(a) and 2(b) show top and cross-sectional schematics of the designed optical coupling structure. The dotted lines in Fig. 2(a) correspond to Cut-A: active region, Cut-B: 1st InP taper, and Cut-C: 2nd InP/Si taper, respectively. The III-V waveguide features a terrace layer (∼200 nm) to enhance the mechanical robustness and broaden the µ-TP bonding contact region as much as possible. The III-V film for µ-TP has a width of 100 µm, and a length of 900 µm. Six 3-µm-wide tethers support the film mechanically. The separation gap between the III-V device and substrate for etching to remove the sacrificial AlInAs layer is 20 µm.
Through a series of light propagation simulations using the finite difference method (FDM) and eigen-mode expansion (EME) methods, we calculated the design parameters such as the width, thickness, length, wavelength dependence, and misalignment tolerance for the structural optimization. As shown in Fig. 3(a), our structure supports a fundamental TE mode with the GaInAsP-core III-V waveguide confinement factor of 38.8% for ΓGaInAsP. Figure 3(b) shows the mode cross-sectional evolution of light propagation from the top III-V active region to the underlying Si waveguide. The mode field is completely confined within the III-V layer stack due to the underlying air-cladding layer which contributes to the reduction of the lasing threshold.
Fig. 3. (a) Mode-field profile and estimated confinement factor Γ in active region. (b) Mode-field evolution observed at cross-section of designed device. Insets are mode-field profiles at each position. (c) Color-contour plots of transmittance with various InP and Si taper widths. Width of the two InP tapers is assumed to be identical. (d) Wavelength dependence ranging in range of 1.55-1.65 µm. (e) Transmittance variation induced by III-V misalignment offset for X axis, and (f) offset for Y axis.
Among the three taper regions, one with the most excess loss is the last one, where the 2nd InP taper has a mode-height mismatch to the connecting 2-µm-wide Si channel waveguide [see the right end region of Fig. 3(b)]. A color-contour map of the transmittance derived from the width parameters of the Si and InP tapers is plotted in Fig. 3(c) for each adiabatic taper. A Si layer thickness of 220 nm is assumed. The taper length is 190 µm in total, which includes 80 µm for the 1st InP taper and 40 µm for the 2nd InP taper [see Fig. 2(a)]. In the calculation, the widths at both InP taper tips were assumed to be identical. While a maximum transmittance of about 85% is expected for InP and Si taper widths less than 200 nm, the transmittance gradually decreases for InP taper widths over 400-nm wide. An InP taper width of 400 nm was finally selected in our device design and fabrication. We confirmed that the back reflectance from the whole structure is about −30 dB. The reflectance can be further reduced to below −35 dB by increasing the Si waveguide thickness above 450 nm.
The Si taper width was set to 200 nm, which is the minimum acceptable value in the process design kit (PDK) of the AIST foundry service. At this width, 80% in the optical transmittance (corresponding to the cross mark in Fig. 3(c); 0.97 dB/coupling loss in decibels) can be expected at a wavelength of 1.55 µm. Most of the remaining ∼20% loss is due to the mode mismatch of the Cut-C: 2nd InP/Si taper waveguides. It should be noted that the transmittance can be further improved by increasing the underlying Si waveguide thickness. For example, >95% transmittance can be expected at a Si thickness of 380 nm because of the improvement of mode overlapping between the InP slab and Si waveguides. Next, we examined the wavelength dependence in the C- and L-telecommunications bands, and transmittance variation due to the misalignment along the X- and Y-axes, as presented in Figs. 3(d)–3(f), respectively. The transmittance is around 80 ± 5% in the wavelength range of 1.45-1.65 µm. A flat response of transmittance was obtained for the Y-axis alignment offset because the waveguide length of the 2nd InP taper has 40 µm as shown in Fig. 2(a). Thus, a few microns offset along the Y-axis does not cause any excess loss. In the case of the X-axis, a flat dependence is given within an alignment offset of ± 0.6 µm, and the transmittance of over 50% is maintained even the offset value exceeds ± 1.0 µm. This result can be explained by the excitation of higher-order modes (note that the 2nd InP taper has a width of 4 µm), which occurs by increasing the displacement. For efficient and continuous single-mode coupling, it is desirable to maintain the misalignment offset along the X-axis to less than ± 0.6 µm.
3. Device fabrication with µ-TP
In the sample preparation, the III-V layer stack was grown by metal-organic chemical vapor deposition (MOCVD) [Fig. 4(a)], and the device structure was defined by i-line lithography and inductively coupled plasma-reactive ion etching (ICP-RIE). After the III-V fabrication procedure, even though the etching rate of GaInAsP is considerably low, a protective photoresist is needed to partially cover the active region and sharp tapers because they are very sensitive to chemical erosion [Fig. 4(b)]. To remove the AlInAs sacrificial layer, it was etched with a mixture etching solution of HF (49%) : H2O2 : DI (1:1:10) at room temperature for 35 mins. After the photoresist cover had been dissolved with acetone and an IPA rinse, the sample was dried in a CO2 supercritical point drier (CPD) at 35 °C and 7.5 MPa [Fig. 4(c)]. This CPD process allows us to avoid temporary photoresist anchoring and internal stress due to the surface tension of liquids. It also enables us to clean the device surfaces with superfluid of CO2, which eventually improves the yields in the following µ-TP steps.
Fig. 4. Schematic illustration of the major fabrication process flow of active region. (a) Epitaxial growth of III-V layer stack. (b) Partially covered photoresist after completing all dry-etching process. (c) Sacrificial layer removal and “pick-up” through µ-TP experiment. Side six tethers support the suspended membrane. (d) After “print” of µ-TP experiment (also see Visualization 1 for µ-TP procedure).
Before conducting the µ-TP experiment, a patterned elastomer (900×100 µm2) of poly (dimethylsiloxane) (PDMS) was fabricated by soft imprinting lithography. An SU-8 epoxy resin mold was formed on a Si wafer followed by PDMS casting and curing steps. To control the stickiness of the PDMS surface, a curing agent ratio of 20:1 and a heating temperature of 80 °C for 4 hours was applied. For the target Si substrate, a standard SOI thickness of 220 nm and a waveguide width of 2 µm were used. The width of the Si taper edge for the III-V/Si light transition region is 200 nm. This target Si chip, without top-cladding passivation of SiO2, was fabricated by AIST’s in-house 12-inch ArF immersion lithography, which is compatible with 45-nm CMOS technology. Thus, the free-standing III-V membrane was mechanically supported by six pieces of tethers (cf. tether width: 3 µm, window opening width for sacrificial layer etching: 20 µm), and then transfer-printed onto the Si target substrate of interest by pick-up and stamp procedures by in-house µ-TP equipment [Fig. 4(d), see Visualization 1 for detailed actions]. It consists of a 6-axis alignment unit with all pulse-controlled stepping motor actuators, and a sample stage with a built-in heater for up to 200 °C. The minimum resolution is 50 nm for X, Y and Z axes, and 0.015 deg for θX, θY, and θZ axes. The adhesion energy of PDMS was carefully controlled by the peeling velocity, where fast and slow rates (10000 : 1) correspond to the two modes of pick-up and print modes. The alignment between the III-V and Si was performed with as-etched markers [cf. dots at the corners shown in Fig. 4(a)] of Si layer under a high-resolution optical zoom microscope [WD: 205 mm, NA: 0.09 (max), magnification: ×588 (max)]. Temperatures of up to 60 °C, and a displacement of 10 µm in X and Y directions for PDMS to induce shear strain [21] were applied in the print step. The bonding interface was characterized by STEM-EDX in the device characterization paragraph.
Figure 5(a) shows a microphotograph of the µ-TP device consisting of the III-V active region on a Si photonic platform. An expanded scanning electron microscope (SEM) view of the 2nd-stage taper with an InP slab layer (region enclosed in the blue box) is shown in Fig. 5(b). While the taper tip width was designed to be 400 nm, the edge measured with the SEM has a somewhat rounded shape with a mean width of about 200 nm (cf. its impact on the offset dependence with the frequency distribution will be discussed in the device characterization). Consequently, we used a focused ion beam (FIB)-SEM to check the cross-sections at the dotted slice lines for Cut-A, Cut-B, and Cut-C shown in Fig. 2(a) and Fig. 5(a). As seen in Cut-C, the alignment offset between the 2nd InP taper and Si waveguide is estimated to be less than 50 nm. The air gaps in both Cut-A and Cut-C are clearly open without bending or contacting the bottom substrate at any of location.
Fig. 5. (a) Microphotograph of µ-TP device. (see Visualization 1 for µ-TP integration) (b) Top-view SEM image of 2nd InP taper and facing Si waveguide corresponding to blue enclosed box in Fig. 5(a). (c) Cross-sectional FIB-SEM images of dotted slice lines for Cut-A, Cut-B, and Cut-C of Fig. 2(a) and Fig. 5(a), respectively.
4. Device characterization
We started the µ-TP device evaluation with the light transmission measurement. A broadband light generated by a super-luminescence diode (SLD) was used to investigate the wavelength-dependent transmittance. By adjusting the light polarization to be the TE mode, the incident light was coupled through a lensed fiber with a mode diameter of 4.1 µm. The output light was collected by an identical lensed fiber followed by an optical spectrum analyzer. Figure 6(a) shows the typical transmitted response in our designed structure, obtained by subtracting the response from the neighboring reference waveguide. The III-V/Si coupling loss of interest is 1.26 dB/coupling (74.8% in transmittance) on average for the C + L telecommunications bands (1530-1625 nm) and a total of 10 samples, which is consistent with our simulation. It should be noted that the values on the vertical axis in Fig. 6(a) are for two III-V/Si sets of couplers with a 0.5-mm-long III-V waveguide for the active region (i.e., the coupling loss here includes a small amount of the sidewall-roughness induced propagation loss). We estimated the standard errors of the transmittance of the reference waveguides were ± 0.40, ± 0.19, and ± 0.34 dB at the wavelengths of 1530, 1580, and 1630 nm, respectively. Note that the effective error is expected to be further reduced since the neighboring waveguide (i.e. distance of a few hundred microns) was used for our calibration purpose.
Fig. 6. (a) Typical III-V/Si coupling spectrum in C + L bands. (b) Overview of relationship between optical loss and alignment accuracy of X-axis for all µ-TP samples (n = 10).
The overall trend in wavelength dependence follows the calculation results. The ripples and notches in the spectral response are due to internal light reflection between the Si spot-size converters (SSCs) at both facets which are designed for fiber-to-chip coupling. The SSCs consist of 300-µm-long adiabatic taper waveguides with a tip width of 200 nm. While these Si SSCs contribute to improving the optical fiber coupling efficiency, the asymmetric air-cladding configuration causes a high coupling loss (∼10 dB), which degrades the signal-to-noise ratio. Another reason for this issue is the coupling of higher-order modes in the region of the InP rib-core, in which the width was designed to be 4 µm to mitigate the alignment accuracy during the µ-TP printing. For further characterization regarding the relationship between the alignment accuracy and loss, we combined the SEM measurement data with the corresponding optical measurement and calculation results, which gave us the plot shown in Fig. 6(b). Note that the X-axis alignment offset (horizontal axis) of these measurement data corresponds to the sum of the left and right sides of each sample. The alignment accuracy was found to be 410 nm/side (n = 10, 3σ). In addition to the Y-axis [see Fig. 3(f)], the angular misalignment is also negligible because the X-axis offset of 500 nm/side gives only 0.03° for the axis of rotation. We can conclude that an alignment error of less than 0.8 µm on a side is acceptable for the X-axis. Undoubtedly, further improvements can be expected by utilizing automated image recognition and advanced position control systems.
PL measurement at room temperature was carried out to reveal the internal distortion induced by the µ-TP process. Although the III-V film is highly resistant to bending and twisting process, the impact on III-V optical devices has not been fully investigated. We prepared samples with a III-V waveguide on a bulk Si substrate instead of a SOI platform. This layer structure can avoid a strong reflection from the Si and BOX layers couples with light from the upper III-V surface to form a resonant cavity that enhances the PL intensity by ∼2.7 times [22]. The buried GaInAsP core layer (λpeak: 1.2 µm) was pumped perpendicular to the laser by a 532-nm laser diode. A line scan with spatial resolution of 2 µm was performed from the edge to the center region of the 900-µm-long sample along the dotted line (i.e., the waveguide propagation direction) in the microphotograph of Fig. 7(a). The corresponding IR transmission image is shown in Fig. 7(b). Owing to the absence of voids or cracks in all regions, the internal distortion induced by the µ-TP can be reliably evaluated. Very uniform peak intensity and wavelength distributions were observed as shown in Figs. 7(c) and 7(d). In the same fashion, the length dependence was also evaluated by measuring PL spectra for a total of 13 samples (7 chips for 100 µm; 6 chips for 900 µm) in Figs. 7(e) and 7(f). In comparison with the reference (as-grown) samples on InP substrates as shown in yellow frames, the peak intensity decreased by 10-20%, and the peak wavelength had a blue shift of 0-5 nm. The full width at half maximum (FWHM) of 55-60 nm is comparable to that of the as-grown sample on III-V substrates. The longer devices exhibited a meaningful larger blue shift in the range of nanometers, which is probably caused by the bending moment (cf. proportional to the sample length) during the printing process. These PL measurements suggest that our integration method does not raise significant concerns regarding the active layer.
Fig. 7. (a) Microscope photograph (reflection) at visible-light wavelength. III-V film was transferred onto bulk Si substrate for PL measurement. (b) Microscope photograph (transmission) at IR wavelength. Non-uniform brightness is caused by IR light irradiated from the backside. (c), (d) Normalized PL peak intensity and PL peak wavelength distributions of 1-D line scan. (e), (f) Device length (100 and 900 µm) dependence of normalized PL peak intensity and PL peak wavelength.
To evaluate the spontaneous bonding interface enabled by µ-TP, the cross section was evaluated by scanning transmission electron microscopy (STEM) with an energy-dispersive X-ray spectroscopy (EDX) analysis. The STEM image and distributions of O, Si, and P elements are presented in Fig. 8. We found a homogeneous and void-free bonded interface between the Si and InP layers [also see Fig. 7(b)]. The thickness of the bonding layer is estimated to be about 15 nm, which almost matches with one in the O mapping. The content of O element varied gradually with distance from the Si surface. These results suggest that the hydroxyl group and native oxides on both the III-V and Si layers coupled to form an intermixing amorphous state. This is a meaningful evidence showing the bonding interface is based on a hydrophilic bonding mechanism. A similar phenomenon has been reported in other large-scale (i.e., wafers and dies) bonding processes by wet treatment and oxygen plasma activation [23,24,25]. Here, we further examined whether the layer thickness of interest can be reduced by high-temperature annealing in N2 gas atmosphere. At 300 and 500 °C, the final thickness was about 5 nm for both conditions without any void generation confirmed by IR imaging. In general hydrophilic bonding, a reaction with water molecule assistance (i.e., Si + 2H2O ⇒ SiO2 + 2H2) is applied for the Si substrate. When the pressure from trapped hydrogen gas exceeds the energy of adhesion, interference fringes induced by agglomerated bubbles should be found through the IR transmission observation at such high-temperature annealing conditions [25]. However, in the case of µ-TP, where the substrate is extremely small, thin, and flexible, it is expected that those hydrogen molecules can immediately flee before forming critical defects. Regardless of whether a post-annealing process is required, thanks to the synergic effects of the microscale device, surface cleaning with the CPD, and atomically flat back plane due to the epitaxially growth, we have found that this µ-TP without adhesive can potentially change our conception of hybrid integration.
5. Conclusion
A two-stage III-V taper structure designed for efficient and robust light coupling to a Si waveguide was investigated toward future µ-TP integration. Contrary to common methods of forming III-V materials on Si photonic circuits, our proposed design is fully compatible with standard SOI stacks and requires neither an adhesive layer nor additional surface activation. In both simulation and experiment, we confirmed that the coupling loss of our design is around 1.0-1.5 dB/coupling. We also performed a PL and bonding mechanism analysis by STEM-EDX with multiple µ-TP samples to understand the fundamental properties, which had not yet been revealed for the purpose of photonic device integration. Through a series of these feasibility studies for µ-TP, we expect to gain more flexibility in the future device design and fabrication rules.
Funding
Ministry of Education, Culture, Sports, Science and Technology (Leading Initiative for Excellent Young Researchers).
Acknowledgments
The authors thank M. Motoki and S. Inoue for their support in fabricating the III-V devices and for helpful discussions.
Disclosures
The authors declare no conflicts of interest.
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