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Abstract
We experimentally demonstrated a low-complexity probabilistic shaping (PS) 16-ary quadrature amplitude modulation (16QAM) scheme based on intra-symbol bit-weighted distribution matching (Intra-SBWDM) for discrete multi-tone (DMT) symbols with field-programmable gate array implementation in an intensity modulation and direct detection (IM-DD) system. Different from the traditional PS scheme such as Gallager many-to-one mapping, hierarchical distribution matching and constant composition distribution matching, the Intra-SBWDM scheme with lower computation and hardware complexity does not need to continuously refine the interval to find the target symbol probability, nor does it need a look-up table, so it does not introduce a large number of extra redundant bits. In our experiment, four PS parameter values (k = 4, 5, 6, and 7) are investigated in a real-time short-reach IM-DD system. 31.87-Gbit/s net bit PS-16QAM-DMT (k = 4) signal transmission is achieved. The results show that the receiver sensitivity in terms of the received optical power of the real-time PS scheme based on Intra-SBWDM (k = 4) over OBTB/20 km standard single-mode fiber can be improved by about 1.8/2.2 dB at the bit error rate (BER) of 3.8 × 10−3, compared to the uniformly-distributed DMT. In addition, the BER is steadily lower than 3.8 × 10−3 during a one-hour measurement for PS-DMT transmission system.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
With the rapid growth of bandwidth requirements for applications such as cloud computing, big data, social networking and virtual reality, current communication systems are confronting severe challenges in improving transmission rates and capacity [1,2]. In recent years, many low-cost and high-capacity transmission schemes with real-time reception for optical interconnection, such as discrete multi-tone (DMT) based on intensity modulation and direct detection (IM-DD), have been proposed [3–6]. In the literature, many real-time IM-DD-based DMT transmitters, receivers [7–11], and transceivers [12–14] have been extensively demonstrated. Furthermore, recent research results suggest that probabilistic shaping (PS) technology has significant advantages in improving the optical SNR tolerance, extending the transmission distance and supporting flexible spectral efficiency [15–18]. At present, some research results based on PS schemes have been reported, such as Gallager many-to-one (MTO) mapping [19], hierarchical distribution matcher (HiDM) [20], prefix-free code distribution matcher (PCDM) [21] and constant composition distribution matching (CCDM) [22]. However, only the look-up table-based PCDM and HiDM have been shown using real-time FPGA implementations among them [23,24]. The MTO shaping method requires the deployment of a joint iterative scheme at the receiver, which applies the outer iteration between the PS de-mapper and the LDPC decoder in addition to the inner iteration in the LDPC decoder. This indicates that the solution has a high hardware implementation complexity and comes at a cost in terms of compute time, memory, and power consumption. Additionally, in order to be compatible with cascaded LDPC-based Forward Error Correction (FEC) coding and higher order modulation, the labels indicating the desired probabilities still need to be transformed or mapped into binary sequences before applying a symbol-level CCDM [25]. Also, the CCDM calls for extremely precise division and multiplication operations, which is quite resource-intensive, and the AC algorithm used for CCDM is an inherently serial sequential method [22]. Due to these two factors, the CCDM is extremely challenging to implement in high-speed real-time hardware with significant parallelism. In contrast to MTO and CCDM, HiDM and PCDM just need look-up tables instead of sophisticated iterative processes, multipliers, and divisions. In [25], a simple bit-weighted distribution matching-based PS 16-ary quadrature amplitude modulation (16QAM) scheme was first proposed. Since it relies only on bit-class processing, the proposed PS scheme has the advantage of less hardware and computational complexity.
In this work, a low-complexity PS-16QAM-DMT transceiver based on intra-symbol bit weight distribution matching (Intra-SBWDM) is investigated over 20-km standard single-mode fiber (SSMF) with real-time reception. It is worth noting that, in the Intra-SBWDM operation (referenced from [25]), the probability of binary data ‘1’ is improved by jointly processing the intra-symbol weight bit labels and subsequent bit reconstruction before QAM mapping. As a result, the Intra-SBWDM-based PS scheme can achieve symbol probability distribution with little redundant bit loss and can be implemented based on FPGA without requiring complex operations. 31.87 Gbit/s net bit PS-16QAM-DMT (k = 4) transmission is achieved with the bit error rate (BER) under HD-FEC limitation of 3.8 × 10−3 after real-time reception. Furthermore, the BER is steadily lower than HD-FEC 3.8 × 10−3 during the one-hour measurement period of the PS-DMT transmission system compared with the standard uniformly-distributed DMT (UD-DMT) signal.
2. PS-16QAM architecture based on Intra-SBWDM
The PS-16QAM architecture based on Intra-SBWDM is shown in Fig. 1. The 16QAM uses Gray mapping rules, as shown in Fig. 1(b). we found that in the red marker bits of the 16QAM constellation diagram, the innermost circle is all ‘1’, the outermost circle is all ‘0’, and the number of ‘0’ and ‘1’ in the middle circle is the same. The red bits represent amplitude bits and the black bits represent sign bits. Therefore, PS can be achieved by changing the probability of ‘0’ and ‘1’ in the amplitude bits of the mapping point. Figure 1(a) elaborates the PS encoding process based on Intra-SBWDM. Firstly, the serial M bits from pseudo-random binary sequence (PRBS) read-only memory (ROM), which are contained within one clock cycle before PS encoding, are divided into four parallel sequences, G1, G2, G3 and G4. The lengths of G1, G3 and G2, G4 are N/4, (M-N/2)/2 respectively. N is the number of bits contained in one DMT symbol after PS encoding. N = Nsc*log216, Nsc is the number of data subcarriers. Then, G2 and G4 are bit-wise divided into groups of k bits each, weighted according to their original k elements. One more bit is introduced as the newly-added effective weight bit (EWB) in each set. Through Intra-SBWDM operation, if the bit weight decision value (BWDV) of ‘1’ is greater than k/2, the corresponding EWB is defined as ‘1’. Otherwise, the EWB is set to ‘0’, and the bit inversion operation will be performed on the remaining k bits in the set. In this way, the probability of ‘1’ in the G2 and G4 will be significantly increased, and the probability of constellation points mapped in the inner circle of constellation diagram will be significantly improved after series parallel conversion. Figure 1(c) shows the example of k = 4 for PS-16QAM based on Intra-SBWDM generation, in which Rm refers to the EWB. In our experiments, Nsc = 48, PS encoding is performed once per clock cycle, one frame of PS-encoded DMT symbols can be implemented for 200 clock cycles.
Fig. 1. PS architecture (a) The PS encoding based on Intra-SBWDM, (b) The constellation labeling design with Gray mapping rules for 16QAM, (c) Intra-SBWDM example of k = 4.
The probability distributions for the constellation of PS-16QAM format are illustrated in Fig. 2. The bar graph represents the probability of each symbol. In order to transmit different symbols with unequal probabilities, four bits representing one codeword are extracted from each of the four binary sequences, which are mapped into a single 16QAM symbol. Therefore, it is obvious that when the symbol corresponds to the second and fourth bits of the codeword with a greater weight ‘1’, the transmission probability of the symbol is greater. In this way, according to the Gray mapping rule, the probability of the symbols in the inner circle of the constellation diagram increases significantly, the probability of the symbols in the middle circle is second, and the probability of the symbols in the outer circle appears the lowest. Different from the PS scheme in [5], the PS coding scheme based on Intra-SBWDM proposed in this paper only needs to perform PS coding on a small number of bits in a clock controlled by the control unit (CU) module, which has low implementation complexity and less on-chip resource usage. In our experiment, the PS-16QAM DMT based on Intra-SBWDM with k = 4, 5, 6 and 7 is investigated in the optical IM-DD transmission system with real-time reception.
Fig. 2. Probability distribution constellation for PS-16QAM based on Intra-SBWDM. (a) k = 4, (b) k = 5, (c) k = 6, (d) k = 7.
3. Real-time experiment setup
Figure 3 shows the experimental setup for PS-16QAM DMT with real-time reception in an IM-DD system. In the modulation of PS-16QAM DMT signal, FPGAs are used to execute the DSP in the transmitter, as shown in Fig. 3(a). The pseudo-random binary sequence (PRBS) with length of 34,800/35200/35600/36000 bits is generated, encoded according to the PS-16QAM mapping rules of k = 4, 5, 6 and 7, and stored in the ROM of FPGA. The read width of the ROM is 174, 176, 178 and 180 for the PS-16 QAM modulation format with k = 4, 5, 6 and 7, respectively. The read depth of the ROM is 200. In addition, the PRBS is pushed into the PS encoding module under the control of the CU. Due to the unsatisfactory frequency response of digital-to-analog converter (DAC)/ analog-to-digital converter (DAC), the pre-equalization technology is used to realize high-frequency component compensation [26]. The compensated signal is conjugated and arranged to be Hermit symmetric, and then 128 complex-valued QAM symbols per cycle are sent in parallel to the 128-point IFFT module, resulting in 128 fully- parallel real-valued data per cycle. Here, the 48 data-carrying subcarriers (SCs) are in the range of 1 to 48. Additionally, the high-frequency and direct current SCs are zero-filled. Add 16-point cyclic prefix (CP) to resist inter-symbol interference (ISI). Subsequently, the PS-DMT signals are digitally clipped with a clipping ratio of 11 dB to reduce the PAPR and DAC quantization noise. The clipped signals are scaled to 6 bits to match the resolution of the 29.4912GSa/s DAC (ADA06S032G). It is also necessary to convert the clipped 144-path in parallel data into 6*128bits serial data and send it to the first input first outputs (FIFO) module for buffering. Moreover, one 144-point synchronization sequence (SS) and eight 144-point training symbols (TSs) are generated offline and used for symbol synchronization and channel estimation, respectively. Therefore, an DMT frame consists of 1 SS, 8 TSs and 200 PS-16QAM data-carrying DMT symbols. The frame structure in the time domain is shown in Fig. 4. The bandwidth of PS-16QAM-DMT signal is about 11 GHz. Under the control of the CU module, the DMT frames are sent to the DAC interface via the low-voltage differential signaling (LVDS) interface. Here, under the hard-decision forward error correction threshold (HD-FEC), the net bit rate (NBT) of the 16QAM-encoded UD-DMT signal is 35.17Gbit/s. And the NBTs of the PS-16QAM-encoded DMT signal with k = 4, k = 5, k = 6, and k = 7 are 31.87 Gbit/s, 32.24 Gbit/s, 32.6 Gbit/s and 32.97 Gbit/s, respectively.
Fig. 3. Experimental setup, (a) block diagram of transmitter FPGA, (b)DAC + ADC + FPGA real-time processing, (c) The electrical spectra without pre-equalization, (d) The electrical spectra with pre-equalization, (e) block diagram of receiver FPGA. (f) The RTL schematic of the real-time PS-DMT transceiver.
The converted DMT analog signal is attenuated by an attenuator (ATT) with a fixed attenuation of 12 dB to reduce nonlinear distortion caused by saturation of the optical modulator. Afterward, the attenuated signal was amplified by a 24 GHz electrical amplifier (EA) and driven a 20 GHz MZM to achieve the E/O conversion. The optical source is a C-band external cavity laser (ECL) operating at 1559.8 nm with a linewidth of 50kHz. The modulated optical DMT signal is amplified by an erbium-doped fiber amplifier (EDFA) and fed into 20-km SSMF for launch fiber power investigation. The working wavelength of EDFA is 1530nm∼1565 nm, and its gain is 25 dB. After 20 km SSMF transmission, the variable optical attenuator (VOA) is employed to adjust the received optical power (ROP). Subsequently, the received optical signal is directly detected by a photodiode (PD) to realize O/E conversion. The converted electrical signal is sampled by a 6-bit 29.4912GSa/s ADC. In our experiments, the operating clock frequency of DAC and ADC is 230.4 MHz. The spurious-free dynamic range of DAC is 28 at a signal frequency of 15000 MHz. The effective number of bits of ADC are 4.3 bits at a signal frequency of 14000 MHz. Additionally, the max output voltages of the DAC and ADC are 1.38 V and 0.78 V, respectively. The captured samples are sent to the Xilinx AUV901 FPGA through the LVDS interface. The 128*6bits stream per clock cycle from the ADC interface is output to 144*6 bits data stream through FIFO buffer, and then sent to the symbol synchronization module. The DSP algorithms of the FPGA receiver include symbol synchronization based on SS [5], CP removal, 128-point FFT [27], TS-aided and intra-symbol frequency averaging (ISFA) enhanced channel estimation and equalization [28], PS-decoding and QAM de-mapping. Subsequently, PRBS data error counts are implemented after demodulation. In addition, the FPGA captures the samples received from the ADC and the real-time recorded error count using a Xilinx integrated logic analyzer (ILA) and sends them to a personal computer (PC) via the Joint Test Action Group (JTAG) interface. Xilinx ILA can capture the waveform of digital signal inside FPGA in real time through one or more probes. Figure 3(b) shows a data acquisition board based on the Xilinx AUV901. Figures 3 (c) and 4 (d) show the electrical spectrum without pre-equalization and with pre-equalization, respectively, demonstrating the performance of pre-equalization, where the spectrum of the received red equalized signal of 11 GHz bandwidth is much flatter than that of the blue non-equalized signal. Thus, the high-frequency components can be accurately compensated. The register-transfer-level (RTL) schematic of real-time PS-DMT based on Intra-SBWDM transceiver is shown in Fig. 3(f).
4. Real-time experiment results and discussion
This section presents FPGA implementations and experimental results for two different transmission configurations: optical back-to-back (OBTB) and 20-km SSMF. The performance of the proposed Intra-SBWDM-based PS scheme with real-time reception is investigated in the IM-DD system. The hardware resource utilization, system transmission performance and stability are analyzed.
4.1 On-chip resource overhead comparison
In our experiment, a Xilinx Virtex UltraScale + AUV901 FPGA is used as a real-time experiment platform, which has 2,364,480 configurable logic block (CLB) registers, 118,2240 CLB LUTs, 6480 DSPs and 2160 Block RAM. Table 1 compares the Intra-SBWDM-based PS-16QAM DMT transmission hardware resource utilization estimated by the FPGA design tool of the real-time DSP of the transceiver. It can be seen that the PS-encoding only requires a small number of registers and LUTS for data caching and reorganization, no additional block RAMs and DSPs block are required. The usage of CLB registers and LUTs for PS-encoding accounts for less than 2% and 1% of the total FPGA Tx resources, respectively. The total CLB registers, CLB LUTs, DSPs and block RAMs of FPGA Tx accounts for 6.9%, 3.6%, 10.2% and 0.1% of the total FPGA resources, respectively. Following the use of the automatic place and route tool, the Xilinx FPGA Editor was used to obtain the FPGA chip plan views of the UD-DMT and PS-DMT transceivers. The overhead of BRAMs and DSPs in the transmitter mainly comes from PRBS ROM and multiplier of the pre-equalization module. Compared with the transmitter, the resource utilization of the receiver is greater. The usage of CLB registers and LUTs for symbol synchronization accounts for 54.8% and 59.7% of the total FPGA Rx resources, respectively. This is mainly due to the fact that the DMT receiver uses 128-path in parallel to achieve data buffering and reorganization for the timing synchronization, which requires a large number of registers and CLB LUTs. Additionally, the usage of registers and LUTs for PS-decoding accounts for less than 0.2% of the total FPGA Rx resources. The results verify the feasibility and effectiveness of the scheme in practical applications.
Table 1. FPGA Chip Resource Utilization Comparison of the Transceiver
Table 2 compares the on-chip resource usage of the Intra-SBWDM and three other reported distributed matchers. It can be seen that the Intra-SBDWM requires only a few CLB LUTs and CLB registers compared to the other three reported distributed matchers. Compared with the HiDM, PCDM (n = 300, w = 32) and DM/invDM, the Intra-SBWDM can save the CLB LUTs by 88.6%, 97.1% and 99.8%, respectively. The CLB Register used by the Intra-SBWDM is basically the same as that of HIDM and PCDM. The Intra-SBWDM can save the CLB Register by about 99% compared to the DM/invDM. In addition, the Intra-SBWDM does not require Block RAM. It takes 4 clock cycles to input data into the Intra-SBWDM module until it outputs a valid PS result. So, the latency of Intra-SBWDM is about 17.36 ns. PS decoding is the inverse process of Intra-SBWDM, and its required latency is the same as the Intra-SBWDM.
Table 2. Resource Utilization Comparison of Four Distribution Matchers
4.2 Transmission performance of the PS scheme
The BER performance after OBTB/20-km SSMF transmission over different ROPs is measured by real-time DSP approaches for PS-16QAM DMT signal based on the Intra-SBWDM scheme with k values of 4, 5, 6 and 7 as well as the UD-DMT. Figure 5 shows the BER performance for the Intra-SBWDM-based PS-DMT in OBTB case. We observe that receiver sensitivity in terms of ROP, at the 7% HD-FEC threshold of 3.8 × 10−3 [31], can be improved by approximately 1.9, 1.7, 1.5 and 0.6 dB for the Intra-SBWDM-based PS-DMT with k values of 4, 5, 6 and 7, respectively, compared to the UD-DMT with pre-equalization. However, when the received optical power is small, the BER performance of PS-DMT with k = 6 is better than that of PS-DMT with k = 4. Given the circumstances, some of the received EWBs may be inaccurate, and as a result, the associated sets may also be incorrect. This explains why the PS-DMT performance curve for k = 6 is subsequently lower than the PS-DMT performance for k = 4. The insets (a), (b) and (c) of Fig. 5 show the constellation diagrams for UD-DMT without pre-equalization, UD-DMT with pre-equalization and PS-DMT with pre-equalization and k = 4 on the 8-th SC in OBTB link, respectively. Obviously, the constellation points of UD-DMT with pre-equalization are more convergent than those of UD-DMT without pre-equalization. This is mainly because the frequency response of high-speed DAC/ADC is not ideal, and pre-equalization technology can achieve accurate compensation of high-frequency components.
Figure 6 depicts the BER performance for PS-DMT (k = 4, 5, 6 and 7) signals after 20 km SSMF transmission over different ROPs. Compared with U-DMT using pre-equalization, when the PS-DMT with the PS parameters k = 4, 5, 6 and 7, there is 2.3, 2.1, 1.9 and 1 dB improvement in receiver power sensitivity under the 7% HD-FEC threshold of 3.8e-3, respectively. Both the IM/DD and the coherent detection systems with negative electrical field can benefit from the reduced signal average power by PS scheme, which can lessen the damage on the transmitted signal caused by the fiber nonlinear effect [32]. The recovered constellation diagrams for the UD-DMT without/with pre-equalization and PS-DMT in the case of k = 4 with the ROP of 0 dBm are shown in insets (a)-(c) of Fig. 6, respectively.
4.3 System stability over time
In order to further verify the feasibility of PS-16QAM-DMT based on Intra-SBWDM, the BER performance stability of the 16-QAM encoded PS-DMT real-time DMT transceiver using Intra-SBWDM within 60 minutes is investigated, and the real-time recorded BER values are shown in Fig. 7, in which the ROP is set to -1 and 0 dBm for OBTB and 20-km SSMF, respectively. The UD-DMT with pre-equalization is near the BER of 4.0 × 10−3 during the entire measurement period for OBTB and 20-km SSMF. Moreover, with the help of Intra-SBWDM, the BER is consistently lower than the BER of 2.0 × 10−3 over the entire measurement period of the PS-DMT with k = 4 transmission systems in the case of OBTB and 20-km SSMF.
5. Conclusion
In this paper, we use FPGA and DAC chips to implement a low-complexity Intra-SBWDM-based PS-16QAM-DMT transceiver for IM-DD system. The hardware implementation complexity of the Intra-SBWDM-based PS-DMT is analyzed and compared to the UD-DMT. And we also analyzed and compared three reported FPGA-implemented of distributed matchers. 31.87 Gbit/s net rate PS-16QAM-DMT (k = 4) transmission is achieved with the BER under HD-FEC limitation of 3.8 × 10−3 after real-time reception. Experimental results show that up to 2.2 dB improvement in receiver power sensitivity can be achieved under the 7% HD-FEC threshold of 3.8 × 10−3 over 20-km SSMF compared to UD-DMT using pre-equalization. In addition, the BER is steadily lower than HD-FEC 3.8 × 10−3 during the one-hour measurement period of the real-time PS-DMT transmission system. Thus, the IM-DD transmission system employing Intra-SBDWM-based PS-DMT can be a suitable candidate for short-reach optical interconnection in terms of hardware implementation complexity.
Funding
National Natural Science Foundation of China (61835002, 61935005); National Key Research and Development Program of China (2018YFB1800905); National Postdoctoral Program for Innovative Talents (BX2021071).
Disclosures
The authors declare no conflicts of interest
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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