Introduction

Some of the recent terabit transmission experiments [1] use a combination of WDM and OTDM to achieve the highest throughput on a single fiber to date. These experiments demonstrate the viability of OTDM as a relevant enhancement technology for present and future long haul WDM networks. OTDM is also a promising technology towards the realization of local area networks (LAN). OTDM’s ability to rapidly switch among various channels could offer superior performance when high speed access is needed [2]. It becomes clear that a rapidly tunable delay line will be required to precisely position the data in its assigned time slot at the transmission end or select the desired time slot at the receiving end. Demonstrated techniques for tuning time slots include altering the optical path length via mechanical means, using coherent WDM to generate precise timing delay [3], and processing optical signals using temporal gratings [4]. Previously we demonstrated a fast tunable serial delay line capable of accessing over a thousand 50 Mb/s OTDM channels with approximately 20ns latency [5]. However, in the previous design, the delay line required two modulators, one at each end of the delay structure, operating at a minimum of four times the baseband rate and a polarization controller in each arm of the delay structure. In this paper, we demonstrate a new rapidly tunable parallel optical delay line capable of accessing high speed OTDM channels with very low latency using one modulator operating below baseband

Principle of Operations

The parallel delay line consists of a N+1 parallel delay line structure, where N is the number of accessible time slots, and one modulator at the input of the delay line as shown in figure 1. An optical clock with a bit period of τ is injected into the modulator. The modulator selects the state of the delay line structure by gating one selected optical clock pulse out of every N. Both the optical clock and the modulator operate at a bit rate of 1/τ. A passive splitter makes N+1 copies of the modulated clock. Each copy propagates through a different fiber length in parallel along the delay structure and recombines at the output terminal. The clock pulse immediately after the modulator (but before the passive splitter) can be described as

Where p (t) is the signal waveform and G_I is either 0 or 1 depending on the input gating function.

 

Fig 1. Schematic for the tunable parallel optical fiber delay line. MOD: modulator

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The first copy propagating down the delay line structure is labeled as the reference delay and it can have an arbitrary delay time, labeled t₀. The second copy of the patterned optical clock is delayed by t₀+T, where T is the baseband bit period at the output of the delay line structure. T is related to τ, the bit period of the input modulator, through the relationship governed by the equation T=τ*N/(N+1). For example, if the modulator bit period τ is 125 ps [8 Gb/s] and the number of time slot is N=4, then the base band bit period will be 100ps. The third copy of the patterned optical clock is delayed by t_o +2T. The n^th copy of the optical clock is delayed by t_o +(n-1)T. Since there are total of N+1 parallel delay lines, the last copy of the parallel delay line structure is delayed by t₀+N*T. A passive combiner merges the N+1 copies of the original signal at the end of the delay line structure. The combined signal can be described as

The factor of 1/N+1 is a result of the passive splitting at the input. The i summation term and the G_i gating function allows the parallel delay line to choose one among N time slot. Equation 3 tells us that the output is the summation of the N+1 copies of the patterned clock, with each copy delayed by time T with respect to the previous copy. For example, if the number of time slot is N=4 and the user needs to tune to the 3^rd time slot, the gating function would be ∑G_i={0, 0, 1, 0}. The j summation term indicates that N+1 copies of the original pattern are recombined and delayed such that all N time-slots within a given bit period T are occupied. The parallel delay line is thus able to access one time slot from an aggregate OTDM data rate of N/T.

 

Fig. 2. Timing Diagram of the parallel delay line

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Figure 2 (a–c) shows the timing diagram of the parallel delay line. The figure shows the case for N=4 time slots. The modulator applies the gating function to the clock pulses in figure 2a to chose time slot 2, labeled S₂ in the timing diagram. Both clock and modulator operate at a bit rate of 1/τ, with the modulator gating the third pulse out of every four pulses passing through using the sequence {S₁, S₂, S₃, S₄}={0,1,0,0}. In the figure 2, the chosen pulses are marked black, while the empty time slots are marked orange. N+1=5 copies of the gated pulses are made by the splitter and each propagates down a unique length of fiber. Figure 2b shows the relative delay of each copy with respect to the reference. The five copies of the pulse pattern are the recombined at the passive combiner. The successive delay of T between each copy upon their arrival at the passive combiner gives rise to the conversion of the bit-period from τ to T. The output of the parallel delay line, diagramed in figure 2c, shows the original sequence {S₁, S₂, S₃, S₄} compressed in time into an OTDM time frame of T. This gives a compression ratio of T/(N*τ), and since T=τ*N/(N+1), the compression ratio is 1/(N+1). Since only S₂ was selected at the modulator, the output pulses all reside in time slot two.

To tune to a different time slot within the OTDM frame, the user can apply a different gating function to the modulator. For example, to tune to the 1^st time slot the modulator applies the following gating function, {S₁, S₂, S₃, S₄}={1,0,0,0}. The reconfiguration time from the initial time slot to the new time slot depends on the bit period of the gating function applied by the modulator and the number of time slots in the OTDM frame. The reconfiguration time is also a function of the initial time slot and the final destination time slot. Applying the gating function immediately following a command to change time slot yields a maximum latency of N*T and an average latency of approximately N*T/2. A simple algorithm can reduce both the maximum and average latency by 50% by involving a binary decision to either immediately change the gating function or to delay the change by allowing the modulator to run through an extra null period prior to applying the new gating function. A null period is equivalent in time to the modulator processing through an entire gating function with the all value of the gating function equal to {0}. Using this algorithm, the maximum reconfiguration time becomes N*T/2 if N is even, and (N+1)*T/2 if N is odd.

A latency diagram best illustrates the decision making steps involved in the algorithm. To describe the relationship between each time slot in the baseband bit-period, the N time slots are looped in a circle, with each time-slot represented by one block and with a Null block connecting the N^th time-slot and the 1^st time slot. For a given transition from time-slot i to time-slot j that involves the immediate change of the gating function, the latency is equal to the number of blocks traveled on the latency diagram in the counter-clockwise direction, with each block representing a time delay of T. Conversely, if the modulator changes the gating function after a null period, the latency is equal to the number of blocks traveled on the latency diagram in the clockwise direction. By measuring and comparing the amount of blocks traveled in either direction for a given i->j time-slot change, the algorithm can decide on whether to immediately change the gating function or insert a null period first. Figure 3 shows how the latency diagram applies to a N=7 time-slot delay line. In both figure 3a and 3b, the initial time slots are i=2. In figure 3a, the destination time-slot is j=7 and the counterclockwise direction offers the least number of blocks traveled to reach time-slot 7. In this case, the algorithm would prescribe an immediate change of gating function. In figure 3b, the destination time-slot is j=5, and the clockwise direction offers the least number of blocks traveled to reach time slot 5. In this second case, the algorithm would prescribe a delay of an extra null period prior to changing the gating function. If both clockwise and counter-clockwise direction offers the same delay, either one can have priority.

 

Fig 3. Latency Diagram

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Experiment

To demonstrate the operating principle, we constructed a parallel delay line with four parallel delays capable of accessing three time slots within an aggregate bit rate of 10Gb/s. A modelocked Erbium fiber laser generates 2.5 GHz optical clock pulses with 1.3ps pulse width at FWHM. The laser feeds the optical clock into a LiNbO₃ modulator and gates one pulse out of every three. Three different patterns are used to select the three available time-slots: (1,0,0), (0,1,0), and (0,0,1). The gated optical clock then passes through a 1×4 splitter, which makes four copies of the signal and sends one down each delay lattice. The reference lattice is 245.6 cm long. The second, third, and fourth delay lattices are longer than the reference lattice by 6cm(300ps), 12cm(600ps), and 18 cm(900ps), respectively. Free space tunable delay lines are placed in the delay lattices to fine tune their delay with respect to the reference lattice. The four lattices are combined using a 4×1 combiner. Including the splitting loss of the two 1×4 splitters and the loss induced by the tunable delay lines, the overall loss of the delay structure is 16.3 dB. The loss induced by the modulator is dependent on the value of N. For N=3, the loss induced by the modulation format is 4.8dB plus any additional insertion loss.

To demonstrate tuning, the output of the parallel delay line for three different time slots in a bit period of 300ps is shown in figure 4a. The second and third pulses are each delayed by 100ps with respect to the pulse in the previous time slot. Also in the figure are two dash lines spaced 200ps apart for measuring the delay. Figure 4b shows the tuning across the same three time slots in a longer time scale that covers six bits. In figure 5, the two dashed lines are 300 ps apart. The pulse amplitude variations in figure 5 can be attributed to variations in the splitting and coupling losses. Using an all fiber implementation can eliminate the uneven loss experienced by the four lattices.

 

Fig. 4 The output of the parallel delay line for three time slots are shown on two time scales. Dashed lines are 300ps apart in figure 4a. Figure 4b shows the output from the delay line on a longer time scale. The dashed lines in figure 4b are 400ps apart.

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Discussion

To rapidly tune N number of timeslots, the optical parallel delay line needs to selectively modulate the input pulse train and make N+1 copies of the patterned optical pulses. From equation 3, we see that the power at the output of the delay line decreases by a factor of 1/(N+1). In table 1, the optical splitting loss of the parallel delay line is shown. For 16 time slots, the parallel delay line has a 12.3dB splitting loss, and the splitting loss increases to 18.1dB for 64 time slots. This places a practical limitation on the number of timeslots the parallel delay line can tune and access to 16 time slots. For higher number of timeslots, such as N=64, the serial delay line offers a 6.1dB advantage over the parallel delay line in terms of splitting loss. The parallel delay line does offer significant advantages over the serial configuration in terms of simplicity and electronic bandwidth requirement. In the serial delay line, tuning the timeslots required two modulators, one at each end of the delay structure, operating at multiples of the baseband bit rate and polarization control throughout the delay structure [5]. The parallel delay line only uses one modulator operating below baseband.

Table 1. A comparison between the parallel and the serial delay line strucutres

View Table

Since the modulator bandwidth is actually lower than the baseband of the output data, regardless of the chosen time-slot, the parallel design offers an advantage over the serial design in terms of simplicity and scaling towards higher optical baseband bit rate. In addition, the use of only one modulator requires only one polarization controller, at the input of the modulator to optimize coupling, and no polarization controller or polarization maintaining fiber are needed within the delay structure. The serial design offers superior performances when many (1000+) channels are needed. The parallel configuration’s performance advantage comes in when the system requires only a few OTDM channels, such as 8 or 16 time slots, but at a much higher electronic baseband bit rate, such as 10Gb/s or 40Gb/s. At the high electronic baseband bit rates of 10Gb/s and 40Gb/s, the serial delay line implementation would require electronic controllers with bit rates of 40Gb/s and 160Gb/s, respectively. A comparison between the two fast tunable delay lines is shown in table 1. Note that the low latency values associated with the serial delay line for high baseband bit rates imply the usage of hypothetical high speed electronics.

Conclusion

The parallel optical delay line uses a new parallel compression scheme to rapidly tune pulses into different time slots of a given OTDM frame. The results from our demonstration show that fast tuning among multiple high bit rate OTDM channels can be achieved and practically implemented using standard high speed electronics.

Acknowledgement The authors would like to thank Li Linbo for his useful comments on the timing diagram.