1. Introduction

In ultra high speed optical communication networks, clock recovery is an essential element for any optical access node because it synchronizes the receiver decision circuitry with the incoming data stream [1]. For example, in the fiber-optics communication systems, the clock signal is extracted out in the receiver end, and the clock could be distributed to demultiplexers, receivers, selectors etc. Therefore, a stable clock source with low jitter characteristic [2] at the receiver end is required. However, due to the speed limitation of electrical circuits, at data rates beyond ~ 40 Gb/s, it becomes increasingly difficult to perform the stable clock recovery electronically. Optical clock recovery techniques that can be scaled to data rates of many tens of Gb/s to > 100 Gb/s will be a prerequisite to high data rate communication links of the future. For the optical clock recovery systems, the key steps are Optical-Electric (OE) mixing and cross-correlation detection.

One approach to high-speed clock extraction is the injection mode locking technique, in which optical clock signal is obtained by launching the pulse trains into the cavity of a self-pulsating laser [3,4]. Another approach is based on the four wave mixing (FWM) phenomenon [5]. In this scheme, a semiconductor optical amplifier (SOA) is employed as the cross-correlation detector, and the FWM signal, generated by the beat of input signal and clock pulses, is filtered through an optical band pass filter. Besides the FWM based on the SOAs, one can also employ the nonlinearity based on intensity modulators such as electroabsorption modulator (EAM) to realize the cross-correlation detection. Regarding the EAM scheme, it has been reported that by using an EAM as the cross-correlator, clock recovery operation at 80Gb/s or higher data rate can be achieved [6–11]. For example, C. Boerner et al. reported 160G/s clock recovery by employing EAM as an electro-optical phase comparator with an electro-optical PLL [6]. In Ref. [7,8], up to 80Gb/s and 160Gb/s clock extraction were achieved respectively by using schemes based on EAM, however, the rms jitter of the extracted clock were larger than 300fs in both cases. In ref. [9], J. P. Turkiewicz et al. demonstrated 160Gb/s clock recovery using a single unidirectional EAM, with the measured rms timing jitter of 205ps. Recently, it has also been suggested that self-correlation using EAM can be employed as a powerful tool to characterize the ultra-short optical pulse profiles [10].

In this paper, we present a phase-locked–loop (PLL) type clock recovery method. A cascaded modulator is employed to act as the OE mixer and a PLL is used to lock the cross-correlation component between the optical signal and an optical clock pulse train [12].

. Experiments and results

Figure 1 shows the schematic diagram of the PLL circuit. As we have mentioned before, in order to realize the clock extraction from input signal, the first step is to estimate the cross-correlation between the locally generated clock and the original input signal. Previously this was done using FWM in SOA [5]. In this proposed work, the cross-correlation function is achieved by using cascaded LiNbO₃ Mach-Zehnder (MZ) modulator.

We generate 160Gb/s patterned data stream by multiplexing two sets of 20GHz pulse trains, then the 160 Gb/s data stream is sent into the input port of MZ modulator. We assume the input pulse signal as Gaussian waveform, therefore, the input pulse train is represented in a Fourier series as

where I₀ and a_k are constants. In this work, the bit rate (f ₁) is 20 GHz, which contributes to the fundamental component of input signal. The modulation signal of (f_vco + Δf) is used to drive MZ modulator. The Fourier expansion of the modulation signal is given by

where V'₀ and b_k are constants.

 

Fig. 1. Schematic diagram of (a) the PLL circuit and (b) cascaded modulator. [Media 2]

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In order to improve the PLL performance and address the problem of polarity ambiguity in the error signal, the offset technique is adopted in the setup. In this case the offset frequency Δf is chosen to be 1.25 MHz, which is generated by sine wave generator. As illustrated in Fig. 1, Δf is split in two arms, in one arm the frequency is multiplied by 16 (it is the reference signal for the phase detector), the other is combined with 10GHz (f_vco) voltage controlled oscillator (VCO) output in the single-side band (SSB) modulator. Thus the sum frequency at (f_vco + Δf) is the modulation signal of the MZ modulator. Since the transmission function of MZ modulator can be expressed by

where γ is the insertion loss, V_B is the bias voltage of the modulator, and the V_π represents the half-wave voltage, from Eqs. (1) (2) and (3) one can obtain the output signal of the MZ modulator

If properly biased at the nonlinear region, the MZ modulator will act as a highly efficient OE mixer, i.e., from Eqs. (1), (2) and (4),a_m cos(2πmf ₁ t), the m ^th term of input signal and b_n cos(2πn(f_vco + Δf)t), the n ^th term of modulation signal get mixed inside the modulator and produce a different frequency at (nf_vco+nΔf)±mf ₁. In order to achieve 160Gb/s clock recovery, a narrow band pass filter centered at 20MHz is inserted to filter out the 16^th harmonics while blocking all the other components. Since the phase locking enables the corresponding frequency error (2nf_vco - nf ₁) to be zero, in the electrical frequency domain, we only need consider the 16^* Δf component, which comes from the interaction between the 160GHz component (m=8) of the input data stream and the 16^th harmonics of the modulation signal (n=16). This beat signal is then sent to the RF port of phase detector and compared with the reference signal. Thereafter, the phase detector returns the feedback voltage to the VCO, which synchronizes the 10GHz signal to the 160Gb/s-data stream.

 

Fig. 2. RF spectrum at the photodiode produced by a beating of the 160 Gb/s optical data and the 16^th harmonic of the electrical input to the modulator. (a) Beat frequency spectrum using cascaded MZ modulator (b) Beat frequency spectrum using a single MZ modulator (c) Spectrum of supermodes in the input optical pulse train. [Media 1]

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The experiment setup for optical pulse generation consists of a ring fiber laser with an intracavity LiNbO₃ modulator. The fiber laser is mode locked to generate a 20GHz pulse train at 1550nm using the technique of rational harmonic mode locking. The pulse width is 2.5 ps (FWHM). A RF synthesizer is used to drive the LiNbO₃ modulator at 10GHz. The 20GHz pulse trains are then multiplexed to 160Gb/s by interleaving the pulses through optical fiber delay lines. The input signal used in this work is patterned as “1010000010100000”.

As discussed earlier, the 16* Δf component carries the cross-correlation information which allows 160Gb/s clock recovery. Therefore, we need to maximize the 16^th beating component for performance optimization. In this work, we replace the regular MZ modulator with a JDS-Uniphase cascaded modulator to enhance the nonlinear effect of the modulation. The schematic of a cascaded modulator is shown in Fig. 1(b). Figure 2 shows the spectrum of RF signals at the output of the fast photodiode. The beat electrical spectrum using the cascaded MZ modulator and a single MZ modulator are shown in Figs. 2(a) and (b) respectively. When Δf is set to 1.25MHz, in the frequency domain, the 16^th beating component appears at 20MHz (see Fig. 2). Using cascaded modulator, the intensity of the 20 MHz signal (produced by beating of the 160 Gb/s optical data and the 16^th harmonic of the electrical input to the modulator) is significantly increased, which indicates that the use of cascaded modulator could improve the OE mixing efficiency. In both Figs. 2(a) and (b), it is clearly seen that a lot of supermodes [13] exist in the spectrum. The RF spectrum of the patterned data is shown in Fig. 2(c), in which 1.33 MHz spaced modes are seen clearly. These modes correspond to the longitudinal modes in the fiber laser used to produce the input optical pulse train. These weakly oscillating supermodes can be viewed as noise background. This supermode noise results from statistical independence of the intracavity modes [14] of the mode locked fiber laser used to generate the data.

 

Fig. 3. Waveform of the 160Gb/s patterned input data measured by wide band oscilloscope (Left) triggered by original clock and (Right) triggered by recovered clock

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To optimize the performance, a polarization controller (PC) is placed before the cascaded modulator. Carefully tuning the VCO bias voltage will enable the VCO output signal to synchronize to the synthesizer frequency, thus the system is locked. In Fig. 3, we show the digital scope traces of the incoming data triggered both by original clock (Left) and recovered clock (Right) respectively. In Fig. 4, we also show the waveform of the recovered clock triggered by original clock and the RF spectrum of the recovered clock. The stable phase difference between the original clock and the recovered clock demonstrates the clock recovery has been achieved.

 

Fig. 4. (Left) Waveform of VCO output 10GHz recovered clock triggered by original clock and (Right) its RF spectrum

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Since in the offset-locking technique, the clock recovery is provided by the locking between these two offset 20MHz lines, and the 20MHz offset signal at the RF port can only be generated through the beating between the two 160GHz components (i.e., beating between the 16^th harmonic of the modulation signal at 10 GHz and the 160 Gb/s pattern. The locking range of this PLL was also measured to be 200kHz.

The dynamic range for the input signal is ~ 12 dB. The input signal frequency values is determined by the bandwidth of the modulator and the configuration. As noted in this experiment, the cascaded modulator configuration provides a better performance.

When the system is locked, two factors contribute to the total timing jitter [15]. One is input signal phase noise induced jitter. This noise arises from drive electronics and from the random nature of individual pulse generation in the laser. Another is relative jitter coming from the cross-correlation processes and signal detection processes. In this work, the rms jitter is mainly from the thermal noise, shot noise, and the noise associated with supermodes. Fig. 5 shows the RF spectrum of the recovered clock, and the rms timing jitter is evaluated using the expression [16]

where n is the harmonic number (here, n=1),f is the pulse repetition frequency p_c and p_n are respectively the powers of the nth harmonics and the maximum of the phase noise centered on the harmonics, Δf is the noise bandwidth (full width at half maximum FWHM), and RB is the resolution bandwidth of the RF spectrum analyzer used, The value of the parameters in Eq. (5) are n = 1, f = 10GHz, p_n = -55dBm, p_c = 5dBm, RB = 300Hz and the measured Δf from Fig. 5 is 20KHz. Thus, the measured timing jitter of the recovered clock using Eq. (5) is 130fs.

 

Fig. 5. RF spectrum of the recovered clock for jitter analysis.

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3. Conclusion

We have proposed and demonstrated 160Gb/s clock recovery based on PLL. The cascaded MZ modulator served as a cross-correlation detector. The RF spectrum analysis indicates that the use of cascaded modulator increases the efficiency of OE mixing. By tuning the bias voltage of VCO, the system was synchronized to the original clock. The 10GHz clock was successfully extracted from 160b/s “1010000010100000” patterned RZ data stream. The measured timing jitter was ~ 130fs.