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We preset a new method to optically represent and implement binary logic, and we implement some unforced logic gates. The binary logic zero and one are taken to be an optical beam, or any electromagnetic wave, that is polarized at a selected state and its negation, orthogonal counterpart, or otherwise. In one implementation, a thin-film system is then designed and used so as it can move between 2 positions producing the net desired polarization change of the output. The output consists of a wave that is polarized either in the direction of the original logic 1 or 0 or any other chosen state and its negation, orthogonal counterpart. The system can be cascaded infinitely due to the fact that the output and input are both of the same format and that the logic zero and one are not dependant on the intensity of the input or the output light beam. The unforced gates exclusive OR and exclusive NOR along with a simple inverter are demonstrated in this communication. We present three design architectures, where each has two types of gates. In one type of gates the polarization state magnitude can carry information that can be employed for testability or reverse logic. XOR, XNOR, and inverter gate designs and operation are discussed in detail, and an easy-to-follow step-by-step algorithm is presented. The introduced architectures are easily adapted for simultaneous cascading, multiple input designs, and integrated optical architecture. * Patent Pending
©2006 Optical Society of America
1. Introduction
Binary logic operations rely on systems that can produce only two states of output: zero and one. It is important for physical systems to have both values be non zero quantitatively, and be easily distinguishable from one another. The current electronic binary logic systems use a low voltage as zero, and a higher voltage as one.
The use of the two horizontal and vertical polarization states of an electromagnetic wave to implement binary logic gates is of great interest since the eighties of the last century. The two states of polarization were used to represent logic one and logic zero. A speculative account of the combination of nonlinear optics and polarization optics that held good promise for binary optical logic [1], a logic based on spatial filtering polarization [2], a suggested implementation of the 16 logic functions of two input patterns based on the birefraction of uniaxial crystals [3], a suggested implementation of the 16 two-input logic operations by use of the recording and readout of photoinduced volume gratings in photorefractive crystals [4], only XOR and XNOR realization utilizing ferroelectric liquid crystals [5], vertical/horizontal input logic representation and on/off output logic representation for N-input gates [6], 2D data array logic gates using an improved polarization-logic algebra [7], shadow-casting logic units using masks and on/off logic representation [8–10], shadowgram-based Boolean logic gates [11–12], logic gates using laser-excited gratings [13],and logic gates based on digital speckle pattern interferometry [14], are examples of concerted efforts devoted to the subject.
We propose using any polarization state and its negation, orthogonal state, as zero and one. Such representation allows the creation of extremely fast optical gates and binary systems that are far more superior to current semiconductor-based systems.
The new proposed system representation allows the implementation of much faster systems, since its output is bound by the speed of light and its input by the optical, electronic, or mechanical control system. It is important to note that the gate processing virtually generates no heat, and accordingly does not suffer from heat problems as in semiconductors. Furthermore the system can be optimized to minimize the control parts, in many cases to a single element even in cascaded systems that represent complicated Boolean functions.
Due to the fact that the unforced new representation produces an output in the form of a beam that mainly retains the original intensity but only differ in polarization state, the system can be infinitely cascaded to produce the desired functions. Such advantages allow the design and implementation of self sufficient units of microprocessors, inverters, XOR, and XNOR gates. A different communication will address the design and representation of forced optical gates and processors, and the integration between forced and unforced logic designs.
Our system, in one of its realizations, only utilizes two different cheap components as needed: thin-film wave retarders, and thin-film wave polarizers. The materials of the thin-film system can be selected to optimize various aspects of the operation, including cost. Previous polarization-based optical logic realizations do not satisfy the general input/output condition at which the difference between logic zero and one is always 180° in the ρ plane, or alternatively polarized in the negative direction, orthogonal. Only work with the special case of parallel and perpendicular polarizations to the system of axes, p and s polarizations, is reported. The new representation allows for easily inverting the input or the output without altering the operation of the system, following the well established digital logic rules. Furthermore other systems incorporate expensive materials such as uniaxial crystals or nonlinear optical elements, or incorporate complicated parallel procedures of beam splitting and interference. Most of these previous systems also rely on the intensity of the output beam to distinguish between the logics zero and one which prevents cascading (requires regeneration of the beam) and involves semiconductor based photo-detectors at each gate which significantly add to the cost, and slows down and complicates the system.
2. Components
In this section we discuss the two types of components that compose the system; retarders and polarizers. In general, the most complex architecture of the logic gates discussed in this paper employs a general polarization device (GPD). It introduces a relative amplitude attenuation of any chosen value, tan ψ, and a relative phase shift Δ also of any chosen value, between the two orthogonal components of the electric vector of the electromagnetic wave parallel (p) and perpendicular (s) to the plane of incidence or transmission. In the case of reflection from a thin-film system (TFS), the polarization transfer function ρ (PTF) is given by
where Rp and Rs are the complex amplitude reflection coefficient. [15, 16] A similar expression the case of refraction through a TFS is given in terms of τp and τs, the complex transmission coefficients. [17] The TFS might be a film-substrate system, an unsupported film (pellicle), a bare substrate, or any other optical device.
In addition to TFSs, a GPD can also be made of birefringent crystals in the standard common way, and electro-optic devices may also be used.
Retarders and polarizers are special cases of the GPD, as we discuss in the following subsections.
The input-output amplitude transfer function (ATF) for any TFS is equal to ∣ ρ∣. For a succession of TFSs, the resultant TFS for the system is the product of all.
The absorption losses in a TFS depend on the choice of materials. If we choose a transparent, i.e. non-absorbing, material(s), then no absorption takes place. The coupling efficiency for a TFS is 100%. Also, the contrast, which is defined as the ratio between the input optical power and the output one when a 0 or 1 state is expected at the output is given by the relative intensity
where a TFS can be designed for an RI > 0.99.
2.1. Ret orders
Retarders are devices that are designed to produce in the output wave a cretin relative phase shift Δ while preserving the relative amplitude (magnitude) of the input wave unchanged; tan ψ = 1, therefore no relative amplitude attenuation is introduced.
For the purpose of our application, we use one of three types of retarders, or a combination thereof, as needed; thin-film reflection type, thin-film transmission type, or non-thin-film type. Note that simple thin-film systems are used in logic implementation for the first time. In the following subsections, we briefly discuss all three.
A. Reflection-type retarders
A.1. Thin-Film (Film-Substrate) Reflection Retarders
Thin-film reflection (TFR) retarders are simply a film-substrate system where a thin film is deposited over a substrate, which operates in the reflection mode. [15] The most widely used one is the SiO2-Si system used in the semiconductor industry. When employed as a TFR retarder device, it produces the required retardation angle Δ to the electromagnetic wave, laser beam, upon reflection at the surface of the device at the design angle of incidence. For example, a quarter-wave TFR retarder produces a 90° phase shift between the two p- and s-components, TM and TE components, respectively. A general retarder produces a retardation value of Δ; accordingly, any light beam that is reflected from the device has an added phase difference of ∆ between the two components of the electric vector of the input wave. For example, if the incident wave is a linearly polarized light at +45°, the reflected wave emerges a right-handed circularly-polarized wave if Δ = 90°. On the other hand, if the incident wave is linearly polarized at -45°, the reflected wave emerges a left-handed circularly-polarized wave for the same value of ∆.
The film-substrate system is divided into three categories depending on the relative values of the optical constants of the ambient N0, of the film N1, and of the substrate N2. When N1<(N0N2)1/2 it is a negative system, when N1=(N0N2)1/2 it is a zero system, and when N1>(N0N2)1/2 it is a positive system. The performances of the three categories in reflection and in transmission are drastically different as the film thickness and angle of incidence are changed. [16]
TFR retarders can be realized using negative and zero film-substrate systems. They cannot be realized using positive film-substrate systems. Any TFR retarder of any retardation angle can be designed and realized using a negative film-substrate system; 0 ≤ Δ ≤ 360° except Δ = 0 and ±180°. With a reasonable tolerance, the TFR retarders of Δ = 0 or ±180° can be designed and implemented. For an exact retarder with a zero tolerance, two TFR retarders of Δ = ±90° can be used. Also, any two TFR retarders with the sum of their retardation angles equal to ±180° can be used.
Only one exact TFR retarder can be designed and realized using a zero film-substrate system; a TFR retarder of Δ = 0. That is a special case of TFR retarders where the retardation angle is zero, where it doubles as a polarization-preserving device (PPD). That device produces an electromagnetic wave polarization-identical to the input electromagnetic wave, hence a PPD.
Other TFR retarders with any selected retardation angles, within a certain range that is material and wavelength dependent, can be designed and implemented within a certain tolerance of choice using zero film-substrate systems. [17]
A.2. Pellicle Reflection Retarders
Pellicle reflection (PR) retarders are retarders designed using a pellicle, which is an unsupported (embedded) thin film. [15] They provide the required retardation angle Δ upon reflection without introducing any relative amplitude attenuation. Their design procedure is similar to that of TFR retarders. Their performance differs from that of TFR retarders in the tolerance of each device to changes in the design parameters; optical constant, film thickness, and angle of incidence.
B. Transmission-Type Retarders
B.1. Thin-film (film-substrate) transmission retarders
Thin-film transmission (TFT) retarders are simply a film-substrate system, where a thin film is deposited over a substrate, which operates in the transmission mode [18]. When employed as a TFR retarder device it produces a required retardation angle Δ to the electromagnetic wave, laser beam, upon transmission through the device at the design angle of incidence. TFT retarders cannot be designed to produce any retardation angle. TFT retarders are also represented on the complex τ-plane in a similar way to that of the complex τ-plane, see Sec.3.
TFT retarders can be designed using negative, positive, and zero film-substrate systems. When using negative or positive film-substrate systems, TFT retarders can be designed and implemented to produce values of Δ in certain ranges depending on the optical constants and wavelength of operation of the device. When using zero film-substrate systems, the only TFT retarder that can be designed is that of a retardation angle of Δ = 0. As for the case of a TFR retarder, the zero-retardation TFT doubles as a PPD [17].
B.2. Pellicle transmission retarders/transmission polarization-preserving device
The Pellicle transmission (PT) retarder is a retarder of a retardation angle of Δ = 0, which is designed and realized using a pellicle. It is the only exact PT retarder that can be designed and implemented using a pellicle. As before, it also doubles as a PPD.
C. Angle-of-Incidence Tunable Retarders
Angle-of-incidence tunable (AIT) retarders are retarders than change their retardation angle Δ with the angle of incidence. That tunability allows for use of the same retarder at different angles of incidence to produce different retardation angles. Therefore, in an optical system, a single retarder can be designed and implemented to function at different parts of the design, and or at different angles of incidence, instead of designing and producing several designs for the same gate. That’s easier to implement and more economical. It also provides for tuning the whole system in a practical way.
D. Non-Thin-Film Retarders
Non-thin-film (NTF) retarders are made of birefringent crystals, or other systems, that would provide a retardation angle into the emerging beam, with reference to the incident beam, based on the crystal having two different optical constants depending on the direction of propagation of the beam within the crystal itself with reference to its optic axis. Those retarders are much more expensive and difficult to make.
The design of these devices is discussed more thoroughly in Ref [19]. It is important to note that the device can be constructed of several materials of choice.
2.2. Polarizers
Polarizers are devices that produce a linearly polarized light beam where the two components of the beam are in phase in the time domain.
A. Thin-film polarizers
As the retarders, or as any other thin-film polarization device, thin-film (TF) polarizers are of two main types, reflection and transmission. Each type is either constructed of a film-substrate system or of a pellicle (unsupported film). The only difference is in the value of the relative amplitude attenuation and relative phase shift produced by the device upon reflection or transmission. In the polarizer case, we have three categories, a p-suppressing polarizer, an s-suppressing polarizer, and a linear partial polarizer.
A3. Linear-Partial Polarizer (LPP)
It is a TFS that produces a relative amplitude attenuation to the electromagnetic wave upon interacting with the device, in addition to a 0 or 180° relative phase shift. It is represented by the real axis of the complex ρ-plane, see Sec. 3.
A.3.1. p-suppressing polarizer (PSP)
It is a TFS that eliminates the p-component of the electromagnetic wave upon interacting with the device. It is represented by the origin of the complex ρ-plane, see Sec. 3. Note that it is a limiting case of the LPP where the emerging wave is TE polarized..
A3.2. s-suppressing polarizer (SSP)
It is a TFS that eliminates the s-component of the electromagnetic wave upon interacting with the device. It is represented by the point at infinity of the complex ρ-plane, see Sec. 3. Note that it is also a special case of the LPP where the emerging wave is TM polarized.
B. Non-thin-film polarizers
Non-thin-film (NTF) polarizers are made of birefringent crystals, or any other system, and are sometimes called birefringent polarizers. They use the fact that the entering beam to the crystal is divided into two beams each traveling through the crystal at a different speed. The output of the polarizer is a linearly polarized beam with a specific relation between the two components parallel and perpendicular to the plane of incidence, retardation angle of Δ = 0 and a relative amplitude determining the angle of inclination of the linearly polarized light to the plane of incidence. That angle can be changed by rotating the crystal around the beam axis.
An NTF polarizer only passes the electromagnetic wave component in its polarization direction. If the wave is linearly polarized perpendicular to the polarization direction of the polarizer, the output of the polarizer is then zero; no wave emerges.
C. Electro-optic devices
In general, an electro-optic device is one that provides interaction between an electric signal and an optical characteristic of the device. In that sense, it is a transducer/sensor. We only consider those electro-optic devices that provide a rotation of the electric vector to represent an electric signal directly or indirectly. Examples of transducer/sensor phenomenon are kerr effect, magneto-optic effect, or a faraday rotation due to propagation through a material. An example of the electro-optic device is the use of liquid crystals to produce a rotation of a polarized light in response to an electric signal.
3. Binary-logic representation
The complex ρ-plane is defined as the complex plane at which the ρ vector represents the relative phase difference and relative amplitude attenuation of the two components, p and s, of the electric vector of the electromagnetic wave discussed before. The complex ρ-plane is used to represent both the polarization state of the wave and the optical components discussed in the previous section; retarders, polarizers, and GPDs. In this study, we use the complex ρ-plane and ρ vector extensively to illustrate how the architecture of different designs can be achieved, and how they function, using the new binary logic representation. The complex ρ-plane is replaced by the complex τ-plane when we use transmission devices.
3.1. Polarization-state representation
Each point in the complex ρ-plane represents a different state of polarization of the electromagnetic wave. The positive (negative) real axis represents linearly-polarized waves, where there is a zero (180°) phase shift in the time domain between the p and s components of the wave, or light beam. Each point on the real axis represents a light beam with a different relative amplitude; between the p and s components. That relative amplitude determines the polarization angle of the beam P, measured counterclockwise from the x-axis of the coordinate system. P is zero at the origin, increasing in the positive direction of the real axis to +90° at infinity, and decreasing in the negative direction of the real axis to -90° at negative infinity. Note that ±90° represent the same linearly polarized light.
Points on the imaginary axis of the complex ρ-plane represent elliptically polarized light with a phase difference in the time domain of +90° on the positive part of the axis and of -90° on the negative part. That leads to elliptically polarized light.
Any straight line passing through the origin represents different polarization states of equal phase shift in the time domain. Accordingly, each polarization has a different relative amplitude. On the other hand, any circle with its center at the origin represents different polarization states of equal relative amplitude; and accordingly of different phase shifts.
Some additional points of interest in the complex ρ-plane are the points ρ = (+1, 0), ρ = (-1, 0), and those on the unit circle. The point ρ = (+1, 0) represents a linearly polarized light with P = +45°. The point ρ = (-1, 0) represents a linearly polarized light with P = -45°. The points on the unit circle represent retarders with different retardation angles. Of special interest on the unit circle are the two points (0, +1) and (0, -1). The first represents right-handed circularly-polarized light, and the second represents left-handed circularly-polarized light.
Each of the two components of the two pairs of (+1, 0) and (-1, 0); and of (0, +1) and (0, -1), is orthogonal to the other. That orthogonality property is very important and is a key in our binary representation.
A. Orthogonal polarization states
Two polarization states are said to be orthogonal if, and only if, they satisfy the condition;
where ρ1 and ρ2 are the two ρ-vectors representing the two polarization states in the complex ρ-plane. is the Hermitian adjoint of ρ1; the transposed complex-conjugate. Accordingly, any two origin-symmetrical points on the unit circle; two points on the unit circle joined by a straight line through the origin, represent two orthogonal states.
In general, two points in the complex ρ-plane are orthogonal if they are joined by a straight line going through the origin and the magnitude of one is the reciprocal of the other; distance from the origin.
3.2. Polarization-device representation
We do have two types of polarization devices, thin-film (TF) and non-thin-film (NTF) types. We have two types of representation for each; passive device representation and active device representation.
A. Passive-device representation
The passive-device representation for both types is the same in the complex ρ-plane; by a point which represents the device polarization state. For example, a linear partial polarizer is represented by a point on the real axis representing its relative amplitude attenuation P, and a retarder is represented by a point on the unit circle representing its relative retardation angle.
B. Active-device representation
The representation of a device in action, active-device representation, is a manifestation of the device action in the complex ρ-plane. That is representing the effect of the interaction of the beam with the device.
B.1. Thin-film devices
The interaction of a beam with a thin-film (TF) device is represented by the resultant of the vector multiplication, dot product, of the two ρ vectors representing the beam and the device. For example, if a linearly-polarized light at +45° reflects at the surface of a TFR retarder of Δ = +90° (right-handed circular retarder), the output beam is a right-handed circularly polarized light. On the other hand, if the input beam is right-handedly circularly polarized, the output beam is then linearly polarized at -45°. Also, a left-handed circularly polarized beam comes out a TFR retarder of Δ = -90° (left-handed circular retarder) linearly polarized at +45°.
B.2. Non-thin-film (NTF) devices
The interaction of the beam with the device is represented by a ρ-vector derived using either Jones or Stokes matrix representation [18]. For any two orthogonal polarizations, the representing ρ vectors should satisfy Eq. (3). For simplicity, and to mention a few, we only consider the special cases of polarization states of linearly polarized at +45°, linearly polarized at -45°, right-handed circularly polarized, and left-handed circularly polarized. As mentioned before, the first two polarization states are orthogonal to each other and the second two are also orthogonal to each other. If one of the two polarization states is that of the beam and the other is that of the polarization device, the output is null; no beam outputs the device. If the laser beam and the polarization device are having the same state of polarization, the beam emerges from the device as is; unchanged.
4. System realization
System realization is achieved through the design of logic gates that can be cascaded together. The most general design of a logic gate is one where the laser beam has its own polarization state, and where also each of the two components, e.g. thin-film substrate systems, comprising the logic gate has its own different polarization state. Since any polarization state is represented by a vector in the complex ρ-plane, then we have two parameters to work with; the magnitude and phase of the vector representing the relative amplitude attenuation tan ψ and relative phase shift Δ of the laser upon reflection at, or transmission through, the film-substrate, or other, systems. For simplicity, we keep one of the two constant and change the other to achieve our design. Accordingly, we have two types of gate designs; constant-ψ and constant-Δ designs. Again, the simplest one of each type is discussed; the unit circle where tan ψ = 1 and the horizontal axis where Δ = 0 or 180°. Those two types of binary gates pave the way easily to the most general, and complex, case where both tan ψ and Δ simultaneously change.
We conclude, for each case, with the design of a general logic gate that satisfies the two conditions: 1) the laser beam carries the binary information on the optical input and output of the gate. That provides for cascading of an unlimited number of gates. 2) The two binary controls of a gate are provided by an electronic input signal.
A second gate architecture uses the laser beam as the medium carrying the information and as one of the two control inputs to the gate. The other control input is an electronic input signal.
4.1. Two-electronic-signal (TES) architecture
A general two-electronic-signal (TES) architecture binary gate is constructed of a collection of optical devices that are cascaded together, Fig. 1. Each device is, for example, a thin-film polarization device that is designed to take two states, e.g. positions, and produce a cretin general retardation angle at one position (logic one: L1), and its orthogonal counterpart; orthogonal image through the origin at the second position (logic zero: L0). Therefore L1 and L0 are represented by two orthogonal states of polarization. The change of state is carried out using an electronic signal.
Fig. 1. General two-electronic-signal (TES) binary gate architecture is constructed of a collection of optical devices that are cascaded together. Each device is a thin-film polarization device, or an electro-optic device, that is designed to take two states.
The TES architecture design is shown in Fig. 2, where the input and output beams are parallel. The PTF for this architecture is ρ = ρ1 ρ2. If the input and output beams are required to be collinear, a third reflection is to be added for that purpose, Fig. 3. In that case, the third element (thin-film system) could be designed to preserve the polarization properties of the beam emerging from the second element (thin-film system) or could be co-designed and co-controlled as needed with the second element (film-substrate system) to perform together the function of the second element (thin-film system) of Fig. 2, where φ2= 2 ψ1 - π/2 and ρ = ρ1 ρ2 ρ3.
A. General retarder(R) gates
As we discussed above, we have two major special types of the TES gate architecture; the constant- Δ and the constant- ψ designs. We start with the simplest, the constant- ψ design, which is the retarder (R) gate.
A.l. XOR retarder (R)-gate
The design of any general logic gate starts with the choice of the state of polarization representing the incoming Laser. For the R-gate type, it is represented in the complex ρ-plane by point A on the unit circle, Δ = α, Fig. 4.
The second step is to determine the two polarization states representing the laser after each of the two film-thickness systems TFS1 and TFS2 of Fig. 2, point B for L11, Δ = β, and point C for L12, Δ = γ, respectively. Accordingly, L01 = β + 180° and L02 = γ +180° (the value of Δ); orthogonal to the β and γ polarization states, respectively. Those two polarization states are represented by points B′ and C′, respectively.
The third step is to determine the two polarization states representing each of the two reflections at TFS1 and TFS2 themselves. That is achieved through a quick study of the operation of the gate. For the operation of the gate, the laser’s state of polarization A is first to be transformed into the state of polarization B or B′ representing L11 or L01, respectively, by interacting with TFS1 in either of its two controlled states 1 or 0, respectively. The state of polarization of the emerging beam from TFS1 is changed upon interaction with TFS2 in either of its two controlled states of 1 or 0. That interaction leads to a transformed polarization state of either C or C′, depending on the controlled states of TFS2, Table 1.
Table 1. Gate-design table, which includes the truth table and the constructed operation table of the R-gate type of the TES architecture of Fig. 4; XOR gate.
Table 2. Gate design parameters (transformations) derived from Table 1., for the two film-substrate systems TFS1 and TFS2, for the two control states 1 and 0 of each; for an XOR R-gate of the two-electronic-signal (TES)
Table 1 gives the truth table of the R-gate type of Fig. 4, which is clearly that of an XOR gate. Note that in generating Table 1, we use the starting point as point A and use the phase information we just discussed to determine the resultant transformations. Note also that vector multiplication is reduced to phase addition; magnitudes of both vectors are unity. Table 2 shows the obtained respective design parameters (transformations) of TFS1 and TFS2. Note that the transformations are obtained by use of a retarder of any type, see Sec. 2. 1. A above.
The following is an easy to follow step-by-step algorithm to do the design;
Algorithm:
- Fill in columns A, B, and C with the info from Fig. 4, corresponding to 0’s and 1’s of the truth table of the gate.
- Fill in column TFS1 by finding the difference B – A.
- Fill in column TFS2 by finding the difference C – B.
- Identify the 0’s and 1’s corresponding to TFS1 and TFS2; transformations.
- Construct the gate-design table.
Figure 6 shows a possible realization of the PTFs of TFS1 or TFS2 of Table 1. The two angles of incidence φ01 and φ02 might be equal or not. If they are equal, the two film thicknesses d1 and d2 provide two different PTFs of ρ1 and ρ2, corresponding to L1 and L0. If not, then we have an extra degree of freedom. Figure 7 shows a second possible realization, where the two angles of incidence are not equal, and each provides a PTF for L1 and L0. Those are only two possible configurations with others are under consideration. Also, remember that a liquid crystal, or any other electro-optic device, can be used for the same purpose.
A.2. XNOR retarder (R)-gate
To design a general XNOR R-gate, we can do either of three things. First, we can simply invert one of the inputs of the XOR R-gate discussed above by an inverter. Second, we can invert the output of the XOR gate by an inverter. For those two cases, an inverter is simply a TFS that produces a relative phase shift of 180° without producing any relative amplitude attenuation, simply a retarder. The above two cases amount to having the retarder at the input, output, in the middle, or even switching the corresponding 1 and 0 of one of the two electronic control inputs with respect to the associated TFS retardation of Table 2.
Third, we use the algorithm of the previous subsection to design the gate. Tables 3 and 4 are the gate-design table and the gate parameters table, respectively.
Table 3. Same as in Table 1., but for an XNOR TES-architecture R-gate.
Table 4. Same as in Table 2., but for an XNOR TES-architecture R-gate.
A3. Cascading: the subsequent (S) gate
To cascade any number of the R-gates together, L1 and L0 are to be the same at the input and output of the gates. The general gate designed above does not satisfy this condition. Therefore, we have a different design for the subsequent (S) gates; the cascading design. For that S-gate, the input laser beam is the output of the first gate, or any other S-gate. That is a polarization state of either C or Ć. Therefore, TFS1 of the S-gate should produce an uncontrolled retardation of - (γ - β) to bring the input polarization state of the beam to either B or B′, Figs. 2 and 34. TFS2 of the S-gate should produce the controlled retardation of γ - β, as before. Now the logic inputs to the S-gate are the laser beam and the controlled electronic input through TFS2. That is the case of one optical logic input and one electronic logic input. On the other hand, if the two inputs to the S-gate are both optical, we can use any of three methods for cascading: 1) convert one of the two input beams to an electronic signal through a photodetector and use the electronic signal as the input through TFS2 as explained above, with a price paid in speed, 2) use the electro-elimination design methodology introduced in Ref. [20] to keep the high speed of the gate unchanged, or 3) use an optical switch which also does not slow down the operation. This S-gate design can be indefinitely cascaded. Operation and truth tables similar to Tables 1 – 4 are easily generated for the S-gates. They are not presented here.
B. General linear-partial polarizer (LPP)-gate
Again, as we discussed above, we have two major special types of the TES gate architecture; the constant- Δ and the constant- ψ designs. In the previous section, we discussed the simplest of the constant- ψ designs, which is the R-gate. Now, we discuss the simplest of the constant-Δ designs, which is the linear-partial polarizer (LPP) gate.
B.1. XOR LPP-gate
As we discussed above, the design of any general logic gate starts with the choice of the state of polarization representing the incoming Laser. For the LPP-gate, it is represented in the complex ρ-plane by a general point A on the real axis, tan ψ = α, where α now is the distance 0A from the origin, Fig. 5. The second step is to select the two polarization states represented by the general points B for L11 = β and C for L12 = γ. Similarly, β(γ) is the distance 0B (0C).Accordingly L01 = 0B́ and L02 = 0Ć; orthogonal to the β and γ polarizations, respectively. Those two polarization states are represented by points B́ and Ć, where 0B́ = 1/0B and 0Ć = 1/0C, respectively.
Table 5. Same as in Table 1, but for a TES-architecture LPP-gate type; XOR.
Table 6. Same as in Table 2., but for an XNOR TES-architecture R-gate.
The same discussion of Subsec. 4. 1. A. 1 holds for our three new points A, B, and C. Using the algorithm of the same subsection, using division instead of subtraction, we derive Tables 5 and 6. Table 6 gives the design parameters for TFS1 and TFS2 for the two controlled states of each. Note that the transformations of Table 5 transform a linearly polarized light to a linearly polarized light with a different value of P. That is achieved by a linear partial polarizer TFS or electro-optically using a liquid crystal, for example, see Sec. 2. 2. A. 3 above.
By closely inspecting Table 5 and 6, we recognize the fact that the TFS1 design is physically correct; same required 0’s and same required 1’s. But for TFS2, the design is not physically correct, because it requires two different 0’s and two different 1’s. To have only one state of 0(1), we equate the two; β/γ = γ/β (γβ⌞ 180° = 1/γβ⌞ 180°). Both lead to γ = β = ±1. Therefore, regardless of the position of point A, B = C = (+1, 0) and B′ = C′ = (-1, 0), or vice versa. A second limiting case is of the two points of 0 and ∞, which is discussed in Subsec. 4. 3. C. 2, and the following subsections.
B.2. XNOR LPP-gate
As before, to design a general XNOR LPP-gate, we can do either of three things. First, we can simply invert one of the inputs of the XOR LPP-gate discussed above by an inverter. Second, we can invert the output of the XOR LPP-gate by an inverter. For those two cases, an inverter is simply a TFS that produces a relative amplitude attenuation of γ + (1/γ) without producing any phase shift, simply an LPP, which is actually equivalent to 180° phase shift for the limiting case discussed in the previous subsection; (+1, 0) and (-1, 0). The above two cases amount to having the LPP at the input or output, in the middle, or even switching the corresponding 1 and 0 of one of the two electronic control inputs with respect to the associated TFS retardation of Table 6.
Tables similar to Tables 5 and 6 can be similarly generated using the same algorithm of Subsec. 4. 1. A. 1.
B.3. Cascading
For the sake of conciseness, we do not repeat the discussion related to the cascading of the R gates. A similar discussion holds for an LPP gate, with proper referencing to points A, B, and C of Fig. 5.
B.4. Magnitude information
The analysis and discussion of the previous subsections limited the LPP gate design to completely identical 0’s and 1’s, which led to the limiting case of B = C. We can do the design with a relaxed condition on the 0’s and 1’s, where we define the 0’s as being of a phase of ⌞ 180° with no restrictions on the magnitude, and the 1’s as being of a phase of ⌞0° also with no restrictions on the magnitude. That allows for more degrees of freedom in the design process, and affords the opportunity to use the magnitude to carry independent information that can be utilized for testing, logic, or reversible logic designs. That is discussed in a separate publication.
4.2. Single-electronic-signal (SES) gate architecture
From the above discussions, it becomes evident that combining points A and B, Figs. 4 and 5, to represent the logic states of the laser beam provides an elegant design architecture. In this case the laser beam carries the information within the optical system as an input and output for the gate, in addition to being one of the controls of the gate. The second control is an electronic one, hence the single-electronic-signal (SES) gate architecture. Now, in Fig. 8 the input laser beam logic states 1 and 0 are represented by the polarization states B and B́, and that leaving the single TFS is represented by the polarization states of C and Ć. It is easy to obtain the truth table for the SES gate architecture using the same algorithm used before and recognize that it is that of an XOR gate. XNOR gates are obtained in a similar fashion as before, simply by an inversion or a redesign.
Fig. 9. Complex ρ plane representation of the single-reflection single-electronic-signal (SRSES) R-gate architecture.
Cascading of the gates is evident in this architecture. The output polarization states are either C or Ć, where the input is always B or B́. Accordingly, a second uncontrolled TFS is introduced at the output of the gate, or at the input, to return the polarization states to B or B́, as we discussed above, Sec. 4.1.A.3.
4.3. Single-reflection single-electronic-signal (SRSES) gate architecture
The single-reflection single-electronic-signal (SRSES) gate architecture is achieved by making points B and C, and hence B́ and Ć, coincide together. That way, the input and output beams have the same L1 and L0 polarization state representation of C and Ć, respectively. In this case, cascading the gates does not require any additional manipulation of the beam since we only have two polarization states of C and C′, and we only have one kind of gate for each type; the S-gate design is not needed. That holds for both gate types, R and LPP.
A. R gate
For the R gate, Tables 7 and 8 give the gate-design and operation table, and the retardation of the TFS, refer to Fig. 9. It is clear from Table 7 that the gate is an XOR one. Two possible realizations for the TFS are those of Figs. 6 and 7.
As we discussed before, XNOR gates of this design can easily be achieved.
Table 8. Same as in Table 2., but for single-reflection single-electronic-signal (SRSES) architecture R-gate; XOR gate.
B. LPP gate
For the SRSES-architecture LPP-gate, Fig. 10 gives the gate polarization-state representation. Tables 9 and 10 give the gate-design and operation, and retardation of the TFS. Note from Tables 9 and 10 that the TFS logic 1 is either of magnitude γ2 and relative phase angle 180° or of magnitude 1/γ2 and of the same relative phase angle. On the other hand, for a TFS to produce this logic one operation it requires a condition of γ = 1, for the operation to hold correct; SRSES architecture. That means, C and Ć are both on the unit circle; points (+1, 0) and (-1, 0), respectively. That special case is to be discussed in the following subsection. It is clear from Table 9 that the gate is an XOR one.
As we discussed before, XNOR gates of this architecture can easily be achieved.
Fig. 10. Complex ρ plane representation of the single-reflection single-electronic-signal (SRSES) LPP-gate architecture.
A second case for the γ condition to be satisfied, is the limiting case where γ = 0 or ∞. That leads to the special case of p-polarized and s-polarized waves as our L1 and L0, which is the only case reported and discussed in the literature [1–14]. This case is also discussed in the following subsections.
C. Limiting and special cases
In the following subsections we discuss several limiting and special cases, some of which are mentioned in the previous subsections.
C.1. Linearly-polarized light at ±45° (LPL45)
Fig. 11. Special case of C and Ć coinciding with the points (+1, 0) and (-1, 0), respectively, in the complex ρ plane, is an intersection case between the R and LPP designs architectures.
The special case of C and Ć coinciding with the points (+1, 0) and (-1, 0), respectively, is an intersection case between the R and LPP designs, Fig. 11. Point (+1, 0) represents a state of polarization of a linearly polarized light at +45°. At the same time, it represents a TFS that produces a relative amplitude attenuation of one and a zero relative phase shift, a PPD device. It is both a retarder and an LPP. On the other hand, point (-1, 0) represents a state of polarization of a linearly polarized light at -45°. It also represents a TFS that produces a relative amplitude attenuation of one and a relative phase shift of ± 180°. Also, it is both a retarder and an LPP.
Tables 11 and 12 give the gate-design and operation, and the TFS functions of the gate. As can be clearly seen from Table 11, the truth table of the gate in this case is that of an XOR. As before, two possible realizations are given in Figs. 6 and 7. Also, XNOR is easily obtained as discussed before.
Cascading of such gates is evident with no additional requirements; see the discussion of Sec. 4.1.A.3
C.2. Linearly-polarized light at 0 and 90°
The linearly-polarized light at 0 and 90° is the limiting case of the LPP gate. The two polarization states are represented by the origin and the point at infinity, respectively. It is directly derived that L1 is the s-polarized light (90° polarization state) and that L0 is the p-polarized light (0 polarization state), or visa versa. L1 of the controlled signal is a rotation of 90° and that of the L0 state is a rotation of 0°, no action or a PPD. That gives an XOR gate. An XNOR gate is simply devised as discussed before.
Also, cascading of such gates is evident with no additional requirements as discussed above.
As mentioned before, that is the only case of polarization-based logic representation previously reported in the literature, with two controlling devices corresponding to the two-electronic-signal design but with no cascading possible without regenerating the output beam, and with zero intensity (no output beam or darkness) representing L0 and a measured intensity representing L1 at the output: on/off output logic representation. That seriusly slows down the operation of the gates and greatly add to the cost [1–14].
4.4. ρ-gates
We discussed the general cases of having a different polarization state for the laser beam, TFS1, and for TFS2. That led to several special cases including the simplest and best, for our current purpose, of SRSES design architecture with its two varieties, constant-Δ and constant-ψ designs, and their special and limiting cases. For completeness, we discuss the design with a general polarization state ρ, represented by point C in Fig. 12. Clearly, similar discussions to all other cases are in order.
Tables 13 and 14 give the gate-design and operation, and the design transformations tables of the ρ-gate. As before, we see that the condition for proper operation and simplest cascading requirements is that Γ = 1/Γ. That condition is only satisfied for the retarder design; R-gate, and for the limiting case of Γ = 0, which is the parallel and perpendicular polarization case.
4.5. Inverter architecture
The architecture of an inverter gate is very simple. In the general case, it is a single TFS that produces 180° relative phase shift and a relative amplitude attenuation of the reciprocal of the state of polarization tan ψ. In the R-gate and LPL45 architectures, the inverter TFS is to induce only a 180° relative phase shift and no relative amplitude attenuation.
4.6. Simultaneous cascading, multiple input, and integrated optical architecture
It is important to realize that cascading any of the above discussed optical gate architectures is not sequential in time. It is simultaneous cascading. Therefore, all electronic signals are to be input simultaneously and the laser output-input delay is determined only by the speed of light. With today’s manufacturing capabilities, and the nanotechnology moving into a more mature stage, delays in the order of femto seconds are achievable. That leads to bandwidths of several orders of magnitude of what is possible today.
Also, it is important to note that multiple input architectures are straight forward from the discussed two-input designs. They are not discussed in this communication to limit the size of the paper.
In addition, integrated optical architecture (IOA) is where any number of Boolean statements of XOR, XNOR, and Inverter operations is involved. IOA can be directly implemented using an integrated architecture that is the subject of a separate publication. For example an IOA can be designed to do switching, demultiplexing, or parity checking, to mention a few applications.
The gates can be cascaded independently or internally. Gates that has more than 2 inputs can be designed by adding one extra retarder for each extra input. A gate that satisfies the Boolean function A XOR B XOR C can be represented by 2 retarders and one polarizer. The polarizer will produce linearly polarized light at +45 and -45 representing the input 0 and 1 respectively, while ρ1 and ρ2 logic 1 will be at angle 0 and logic zero will be at an angle of 180 in the ρ plane. On the other hand, the Boolean expression A XOR B XNOR C will be very similar to the latter, but it requires an inverter to be added after the output of the first retarder, and ρ2 logic 0 and 1 must be interchanged. As illustrated, multiple input Boolean expressions that rely on XOR, XNOR, Inverters or any combination of the latter can be easily cascaded by adding an extra layer or layers of thin films. The discussion of Sec. 4.1.A.3 on cascading holds here, obviously without the need for the uncontrolled TFS.
At the end of the whole cascaded system, or at the end of each gate the output can be easily identified and turned into an electric signal, as required. For the simple case that is deigned to produce linearly polarized output at +45 and -45 degrees, a slightly off-axis polarizer or a thin film based system can be design to maximize the transmission or reflection of one case while minimizing the other. That, in conjunction with the use of a simple photodetector allows the photodetector to produce an electric output of high reading representing logic 1, and low reading representing 0. Also, it allows for the integration of the new optical binary logic implementation with the current semiconductor based binary logic systems. Such integration at the input and the output provides great versatility for the new optical device, and allows the creation of hybrid technology that utilizes the advantages of the new system, without greatly altering current designs. Furthermore, communication between optical-based devices and semiconductor-based devices will not face any complications.
5. Conclusion
We presented a polarization-based binary-logic representation that employs any polarization state and its negation, orthogonal state, to represent logic 1 and logic 0. That general representation is not limited to the horizontal and vertical polarization states as previously reported in the literature. We also introduce and discuss three architectures to represent XOR, XNOR, and inverter gates, each having two types. In one implementation, we use thin-film structures to do the optical manipulations of the beam carrying the information into, and out of, the gate, allowing complete optical manipulation of the information. For all architectures we discuss the design and cascading of the gates. In one, we also discuss the wave magnitude as an added information-carrying element. The only previously reported case in the literature is a special case of one of the two types of one of the three architectures. We close by a brief discussion of simultaneous cascading, multiple-input designs, and integrated optical architecture.
Acknowledgments
The authors would like to thank the two anonymous reviewers for their careful reading of the manuscript and for their constructive comments and suggestions to improve the manuscript.
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