1. Introduction

All-optical (AO) logic gates are envisioned as key building blocks in the next generation of advanced photonic networks [1]. We recently introduced a novel all-optical logic architecture [2], whereby the gates may be readily reconfigured to implement (N)AND / (N)OR / X(N)OR logic, i.e. a single gate structure may be repeated throughout the logic circuit to implement multiple truth tables, facilitating gate array manufacturability. In contrast to prior research in reconfigurable AO logic [3–5], our approach emphasizes cascading of multiple such gates into larger logic arrays, aiming towards an all-optical FPGA. Moreover, the AO circuit may coherently operate at a single wavelength. Gate reconfiguration is effected by an optical reference signal, which may be adapted to an arbitrary Boolean complex-valued alphabet at the gate logic inputs, and calibrated to correct gate imperfections.

Remarkably, our AO gate structure is partitioned into an interferometric linear front-end (LFE), and a nonlinear back end (NLBE). In the LFE, two lightwave logic inputs and a reference signal linearly interfere. The NLBE implements a phase-erasure (or “reset”) function, realizable either as a SOA (semiconductor optical amplifier), saturable absorber, HNLF (highly non linear fiber), EDFA (Erbium doped fiber amplifier) or through other potential optical nonlinearities (any phase-insensitive logical NOT) [2]. The gate reconfiguration and recalibration capabilities, along with its functional decoupling of the linear and nonlinear sections, facilitate the potential aggregation of large gate counts into logic arrays over photonic integrated circuit (PIC) platforms.

In this paper we elaborate on the novel architecture and principle of operation, experimentally demonstrating for the first time, by means of RF photonics, the reconfigurability and rudimentary cascadability of nine gate pairs operating at low clock rate. Since feasibility study on an integrated chip is highly challenging and since bulky free space/fiber interferometery schemes arise difficulties of phase stability control over long distances, non-relevant to the miniature chip implementation, our demonstration is conducted in the optical envelope rather than in the optically coherent domain. Finally we discuss prospects for large-scale photonic integration based on recently emerging opto-electronic repeater technology [6], and the implementation of the presented scheme is examined based on the recently outlined criteria for practical optical logic [1].

2. Theory of reconfigurable linear-nonlinear gate operation

We first illustrate how simple linear optics (e.g. cascaded Y-junction combiners as simulated in Fig. 1(a) ) may “almost” realize the logic operation, yielding a 3-level signal, with two of the signals being antipodal; the non-linear termination (phase erasure) provides the final touch, an essential non-invertible mapping that collapses the two antipodal signals into a single one, yielding a two-level logic output. The logic inputs X and Y are selected from the complex-valued set $\left\{A,B\right\}=\left\{\left|A\right|\angle {\phi }_A,\left|B\right|\angle {\phi }_B\right\}$. Here we assume real-valued logic: φ_A=φ_B=0. In the gate LFE, a first combiner generates the sum X+Y, while a second combiner adds up a reference signal, -R, with:$R\in \left\{R{}_a,R{}_b,R{}_c\right\}=\left\{1.5A+0.5B,0.5A+1.5B,A+B\right\}$yielding the interim output U = X + Y – R; in the NLBE, U is passed through a “phase eraser”, namely a nonlinear element with transfer characteristic V = |U| (or any monotonic function of |U| e.g. |U| ²). The three logic truth tables of the reconfigurable gate are established in Table 1 .

 

Fig. 1 (a). OptSim^TM simulation of optically coherent operation of a single NOR gate [1]. (b). Reconfigurable two-gate logic circuit realizing nine possible truth tables, as set by R ₁,R ₂, and its implementation using linear-nonlinear reconfigurable gate structures.

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Table 1. The AO gate functions as either AND, NOR or XNOR, as selected by the value of R. Reversing the logic polarity yields the complementary logic functions NAND, OR, XOR.

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3. Experimental demonstration of the gates

In this section we show the experimental demonstration of gates reconfigurability and rudimentary cascadability using RF photonics. As initial proof-of-principle, we experimentally prototyped the above concept, albeit with incoherent RF-modulated, direct-detection lightwave envelopes, using incoherent addition of optical powers, rather than operating in the optically coherent domain as envisioned in ultimate realizations of ultra-high-speed large-scale PICs. Notice that the mathematical model of gate operation discussed in Table 1 applies “as is”, provided the coherent optical carrier is conceptually replaced by an RF-modulated lightwave envelope, further modulated by NRZ Boolean signals; the photo-detected lightwave envelope is passed through an electronic high-pass filter (HPF) in order to offset its average value, yielding a real-valued bipolar signal. The LFE consists as before of a pair of optical combiners, though now optical powers are added up rather than complex amplitudes.

A super-luminescent source is used to effect power superposition. The O-E-O repeater effecting a regenerative phase erasure operation is realized incoherently in our demonstration, consisting of the cascade of a photo diode (PD), HPF, electronic envelope detector, two-stage Butterworth LPF, comparator (to subtract the reference R while regenerating the electronic signal, removing source noise, imperfections in the LFE and current spikes from the PD), and finally an RF phase shifter (to adjust the phase of the RF envelope prior to injection into the next stage optical modulator). Once these principles are understood, the experimental block diagram of Fig. 2(a) is readily identified as implementing the abstract functions of Fig. 1 and Table 1. Figure 2(b) presents a picture of the constructed experimental configuration including the setup itself in the center and the required characterization equipment such as EDFA, digital scopes and fibers at the lower right and upper left corner of the picture. The only parts of Fig. 2(a) requiring further clarification pertain to the generation of sufficiently rich test combinations {I₁,I₂,I₃} = {000,001,011,111,110,100} of logic input signals, by means of power addition of three NRZ (non return to zero) signals successively optically delayed by 1/3 of a period (Fig. 3 ). The signals that were experimentally measured at the first and second gate outputs are shown in Fig. 4 . I₁ (green), U₁ (blue), V₁ (yellow) and U₂ (purple) are the signal waveforms for all possible gate combinations (by manually changing the VOA settings), each for 6 of the 8 possible input triplets.

 

Fig. 2 (a). Low-speed experimental demonstration of reconfigurable two-gate circuit using RF photonics. MZM denote Mach-Zehnder Modulators operated in a quasi-linear region around quadrature; Variable Optical Attenuators (VOA) are used to adjust the optical powers of the logic signals and the references to the correct mutual ratios. Suitable fiber delays are used to synchronize the RF carrier and logic waveform phases of the various signals. The RF subcarrier modulation frequency is 232kHz; the NRZ logic signals are clocked at 1.5 KHz. (b). Picture of the constructed experimental configuration including the setup itself in the center and the required characterization equipment such as EDFA, digital scopes and fibers at the lower right and upper left corner of the picture.

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Fig. 3 Test inputs to the logic circuit: (a). Successively delayed inputs. (b). Power addition in first gate. (c). Power addition in second gate.

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Fig. 4 Signal waveforms in the experiment of Fig. 3: I₁ (green), U₁ (blue), V₁ (yellow) and U₂ (purple) for all possible gate combinations (by manually changing the VOA settings), each for 6 of the 8 possible input triplets. (a) AND-AND, (b) AND-NOR, (c) AND-XNOR, (d) NOR-AND, (e) NOR-NOR, (f) NOR-XNOR, (g) XNOR-AND, (h) XNOR-NOR, (i) XNOR-XNOR. Comparing the measured Boolean signals with those predicted in Table 2, it is apparent that the two-gate opto-electronic logic circuit indeed functions as designed.

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In Fig. 4 one obtains the experimental realization of the following Boolean functions for the two logic gates G₁ and G₂ respectively as they appear in the schematic sketch of Fig. 1(b): in Fig. 4(a) AND-AND, in 4(b) AND-NOR, in 4(c) AND-XNOR, in 4(d) NOR-AND, in 4(e) NOR-NOR, in 4(f) NOR-XNOR, in 4(g) XNOR-AND, in 4(h) XNOR-NOR and in 4(i) XNOR-XNOR. Comparing the measured Boolean signals with those predicted in Table 2 , it is apparent that the two-gate opto-electronic logic circuit indeed functions as designed.

Table 2. Truth table for cascaded gates G₁ and G₂ and logic inputs {I₁,I₂,I₃} (red = untested).

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Note that in the presented experimental scheme the energy consumption of the modulator is relatively high and it doesn't reflect the real consumption for the integrated scheme. The fan-out of the proposed configuration may be estimated as follows; for an external laser modulated at the output of each gate, any number of output gates could be cascaded as long as the number is known in advance and is similar for all gates. For the RF scheme the fan-out should be limited by the noise at “0” logic level and on the threshold of the PD detection (which affects the error probability).

4. Large-scale O/E/O photonic integration of reconfigurable logic circuits

The cascadability of multiple AO reconfigurable gates into integrated coherent photonic logic circuits was addressed in Ref [2].

Here we propose and discuss a novel alternative opto-electronic architectural approach, amenable to large scale integration of photonic logic arrays of the gates [2], based on recent advances in Silicon and InP photonic platforms [6–11].

The resulting large-scale logic circuits would no longer be all-optical, as they would require the integration of passive optics, PDs and modulated optical sources. With the advent of digitally regenerating photonic circuits [6], this architecture bears potential for very large scale integration and ultra-high-speed logic operation.

An opto-electronic gate with optical inputs and electrical output (Fig. 5 ) may be implemented based on two stages of optical combining (e.g. realizing its LFE as in Fig. 1(a)), however now the NLBE terminating the LFE output is no longer AO, but is realized as square-law photo-detection. A PD is used to generate the phase-erasure operation (V = |U|²) in the mixed optical-electrical domain (O/E conversion), improving the noise margin and enabling the gate to meet the criteria of cascadability and logic-level restoration. The photocurrent is E/O-converted back to the optical domain by having the PD output drive a modulated optical source, e.g. an electro-absorption modulated laser (EML), providing a complete input/output isolation and preventing critical biasing. A single laser source (“optical power supply”) may be shared among multiple electro-absorption modulators (EAMs), and optical pre-amplification may be used with the PDs. This structure realizes reconfigurable cascadable gates with optical I/Os but with internal electronic phase-erasure and thresholding (slicing) inserted between the PD and the EML, attaining a regenerative characteristic. Such reconfigurable gates may be in principle indefinitely cascaded and fanned out/in by means of optical interconnects. Novel III-V based modulators with ultra-low energy consumption are recently emerging [13,14], enabling our scheme to approach the desired energy consumption per bit [15, 16].

 

Fig. 5 O/E/O reconfigurable gate – the recurring element in large-scale reconfigurable photonic logic arrays leveraging the PIC platform [5].

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Notice that compact O/E/O repeater arrays were recently large-scale integrated, in the context of optical transmission applications, by companies such as Infinera [7]; those mass-produced PIC platforms are evidently not currently directed towards photonic logic, but rather their target application is large-scale opto-electronic integration of conventional optical transceivers, O/E/O digital regenerators, add-drop multiplexers [6], optical switches [11] and integrated PD and EAM on a chip [12].

Nevertheless Si and InP platforms as well as hybrid wafer-bonding technologies for compound Si-InP platforms [7–10] have progressed and will continue to mature to the point where they would enable large-scale photonic logic circuits arraying the recently discovered linear-nonlinear reconfigurable gates [2].

The issue of cascadability of the proposed approach may be attained by two means including introducing a calibration and tuning procedure in the linear module of each gate as well as by endowing in the nonlinear phase-eraser module with a regenerative characteristic.

An important enabler of the cascadability of the proposed logic devices is the property of logic level restoration. The gate output should have less spread of its logic supports than the analog representations of the Boolean inputs do – ideally the analog output should remain constant (its logic support should be a single point) in the wake of small variations of the analog inputs over their respective logic supports. To attain logic-level restoration, the transfer characteristic $V=M\left(\left|U\right|\right)$of the phase erasure module should have abrupt transitions between the LOW and HIGH input states, and should be as flat as possible over the domains of the inputs outside the transition, providing tolerance in the wake of small deviations in the input signal levels over their logic supports. Then, the relatively narrow supports resulting for the L and H outputs may be used as well-conditioned inputs to the next gate, curbing error accumulation and allowing cascadability. Thus, it is clear that imposing the regenerative characteristic additional constraint on the shape of the transfer function$M\left(\left|U\right|\right)$, may significantly improve cascadability.

The ideal solution is to have the phase erasure nonlinear characteristic further endowed with a limiter or ideal-switching amplitude transfer characteristic, either straight (ID gate) or inverted (NOT gate):

The smaller the absolute values of the slopes of the two limiter branches, the more precise the gate operation, as each input logic support gets well compressed when propagating through a mildly-sloped limiter branch. Ideally the slopes of the two branches should be zero. If there are small deviations remaining, i.e. the output logic supports are (small but) finite, rather than consisting of two discrete points$V_L,V_H$, then cascadability is still feasible.

To substantially increase the length of the logic cascades, it is highly desirable to insert, at least every few gates if not in every gate, high quality switching characteristics effecting restoration of the logic signals.

5. Conclusions

In this paper we have experimentally demonstrated the realization of cascadable and reconfigurable photonic logic (N)AND, (N)OR and X(N)OR gates based upon a combination of linear lightwave interference followed by a non-linear phase erasure module.

In our experimental investigation we demonstrated the operability of pair of linear-nonlinear all-optical logic gate structures using RF photonics. Although demonstrated with fibers and at low operation rate, the operation principle proven in this paper may enable realization of large-scale of such reconfigurable arrays being operated at optics communication rates (e.g. 40GHz) if the operation principle of such gates is applied over the highly integrated O/E/O repeaters over Si/InP hybrid platforms.