1. Introduction

The packet switching network has been advanced to process the immense amount of packet data at a very high speed due to the explosively increasing packet-based multi-media services. All-optical packet switching networks (AOPSNs) where the packet switching and routing are implemented with the photonic signal processing have been investigated intensively to fulfill the required performances of the fast optical packet processing [1].

Optical packet classifier in AOPSN is one of the key technologies related to QoS provisioning at a packet router. The packet classifier determines a service level of information carried by a packet regarding on bandwidth, jitter, delay, loss, etc [2]. In the conventional IP-over-WDM networks, the packet processor has been implemented using electronic devices, which has posed operational limitations due to relatively slow electronic devices [3]. Such speed-limit problem becomes more serious when complicated logical functions are required in packet processing, like in the packet classifier. In an effort to realize high-speed optical packet processing, various schemes and architectures of the optical packet processor have been reported up to now [4–7].

In this paper, for the first time, we proposed an all-optical packet QoS level classifier which is based on the sequential binary priority comparison. Optical logics in the proposed scheme are realized utilizing semiconductor optical amplifiers (SOAs) operating in the cross-gain modulation (XGM) regime. Since the structure of the proposed packet QoS level classifier only rely on a feedforward control scheme, it can provide a high speed operability at 1 Gbps or even higher as well as a great flexibility in the packet length to be processed.

2. Proposed packet QoS level classifier structure

In a priority queuing scheme, a packet is assigned to one of the predetermined queues, for example, high, medium, normal, and low priority queues according to the service class of the packet. During transmission, a higher priority queue holds an absolute preferential treatment over low priority queues. The priority is specified by priority bits in the packet header. As an example, packets in the IP differentiated services (diffserv) are marked by a Differentiated Services Class Point (DSCP) in 6 bits of Type of Service (ToS) of an IP packet header to identify their classes.

A packet level classifier processes the incoming packet priority bits to determine the service priority level of the packet. In the packet level classifier shown in Fig. 1 , an incoming packet priority bit pattern (A) is compared with the pre-determined four classifying level patterns, B1, B2, B3 and B4. The classifier is designed to produce a noticeable output at the one of the 5 output ports, each of which corresponds to one of the 5 priority levels, for example highest, high, medium, low and lowest levels.

 

Fig. 1 Packet level classifier based on packet priority-bits.

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The proposed packet level classifier is shown in Fig. 2 . It is presumed in the figure that the optical priority bit pattern was extracted from the packet header, being ready to be provided to the packet classifier. In addition, it is assumed that a triggering pulse per packet is produced and supplied to the bit pattern generators. The packet level classifier in Fig. 2 has 4 classifying bit-pattern generators, each of which produces a bit pattern representing one of the 4 classifying values B1, B2, B3 and B4. A bit pattern generator can be readily implemented by using fiber delay lines, optical splitter and combiner. Each classifying bit pattern is synchronized in time with the incoming priority bit pattern (A). The value of the incident packet priority pattern is compared with each of the classifying bit patterns in order. The result of comparison in an optical comparator block is a packet level decision, otherwise it is fed to the AND logic gate to make the next level decision process. In the following section, we will describe the optical priority comparator that is to be used in the proposed all-optical packet level classifier.

 

Fig. 2 Proposed all-optical packet level classifier model.

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3. All-optical binary packet priority comparator

3.1 Binary comparison algorithm

A binary comparison algorithm is shown in Fig. 3 , where two numbers A and B are to be compared to find which is greater. For a binary comparison, A and B are expressed by binary summations respectively as follows.

 

Fig. 3 Binary packet priority comparison algorithm.

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3.2 SOA-based counter-propagating XGM logic gates

The implementation of the binary packet priority comparator in this paper is based on logic gates exploiting the XGM effect of SOA. The XGM is a nonlinear effect that occurs in an SOA when two signals pass simultaneously through the device. If a high optical input power, called the pump signal, is injected into the SOA, it causes carrier depletion in the active region through the stimulated emission resulting into a gain reduction of the SOA. In Fig. 4 , pump signal B causes carrier depletion in the SOA, which leads to a gain saturation causing the marked intensity reduction of the low-power signal, probe signal A, resulting into no signal at the SOA output port. When the pump signal is not present, the low-power signal is amplified by the SOA and its logic state is transferred to the SOA output. This operation can be summarized as $A•\overline{B}$ as shown in the Table 1 . The counter-propagating configuration has the merit of capable of using the same or different wavelengths for the pump and probe input signals. It is however known that the speed of the XGM-based logic gate is limited by the SOA length [6]; operation at 25Gps is allowed with 2 mm SOAs, and further advancement with shorter SOAs could be expected with advent of advanced PLC (Planar Lightwave Circuit) technologies.

 

Fig. 4 Counter-propagating configuration of the SOA-based basic logic.

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Table 1. Truth table of logic function based on XGM

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3.3 Implementation of binary packet priority comparator

Figure 5(a) shows a digital gate level architecture of the proposed packet priority comparator, which consists of two functional blocks, a bit-comparator and a bigger-value indicator. The inputs to the bit-comparator are two input bit patterns, A (packet priority bit pattern) and B (classifying bit pattern). Two outputs of the bigger-value indicator, O1 and O2 represents two comparison results, $A>B$ and $A\le B$, respectively. It means that “1” will appear at either output port O1 or O2 as the comparison result depending on $A>B$ or $A\le B$.

 

Fig. 5 Proposed all-optical binary packet priority comparator, (a) digital gate-level architecture of packet priority comparator; (b) optical packet priority comparator corresponding to (a); (c) operation timeline of proposed scheme.

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The bit-comparator is to compare binary bits A[i] and B[i] of A and B sequentially in order. This comparison operation can be described by two logic functions $\overline{B[i]}A[i]$ for G1 gate and $\overline{A[i]}B[i]$ for G2 gate. As shown in the logical truth table of the bit-comparator in Table 2 , U port will have “1” if A[i]>B[i]. On the other hand, bit “1” will appear at L port for the case of A[i]<B[i]. In order to take care of the case of A = B, an extra bit is added after the bit sequence of B.

Table 2. Truth table for bit-comparator

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The operation timeline of the proposed priority comparator scheme is shown in Fig. 5(c) for the example of A = 11011 and B = 100011. There will be two bits on the time-slots $t_0$ and $t_1$ at U, and one bit in the time-slot $t_2$at L. Such bits indicate the results of the comparisons made on each coefficient of the binary expressions of A and B, as described in Eq. (1). The bit at $t_0$ represents that the second significant coefficient $a_1$of A is greater than the second significant coefficient $b_1$of B, resulting that A is larger than B. Therefore, the further comparison result bits at U and L are no longer needed, and thereby should be ignored. Such action is carried out by the bigger value indicator block following after the bit comparator block as shown in Fig. 5(a) and 5(b). The clearing bit generator in the bigger value indicator block generates a chain of N bits (where N is the bit-length of A and B), starting from the time instant where the first decision of inequality between the significant coefficients of A and B is found. The clearing bit streams is delayed by one bit interval and applied to AND gates G3 and G4 in order to prohibit any influence from the next comparison result bits to the first comparison result bit that is the bit on $t_0$ at U in the given example. Consequently, only the first “1” of the bit comparison result is forwarded to either O1 or O2, representing $A>B$ or $A\le B$. Optical implementation of bit clearing is realized by using SOAs, SOA3 and SOA 4 as in Fig. 5(b). The SOAs operate as AND logic gates based on XGM effect [8]. Strong pump signal a is supplied to the right port of the SOA and saturates the device whereas weak probe signal b is applied to the left port of the SOA. Consequently, SOA works as the logic function $\overline{a}b$, where a is the pump signal that is the bits from a clearing bit stream, and b is the bit from a probe signal that is the comparison result bits in Fig. 5(b).

4. Experiment and discussions

Figure 6 shows the experiment setup to demonstrate the performance of the proposed optical binary comparator for 4 bit-length binary numbers. A pulse pattern generator (PPG) generates the binary number A (packet priority bits). The binary number B (classifying value) is generated by one-bit delaying A for the experimental simplicity. The generated two priority bit patterns are now A = 1011 and B = 0101, and B has a one additional bit to form 01011 as explained before. The experiment was carried out at 1Gb/s. The optical intensity modulator used in our experiment is a 2x2 LiNbO₃ interferometric switch. The laser source operates at 1550nm. The clearing bit generator employs four delay lines with 1-bit, 2-bit, 3-bit, and 4-bit delay respectively.

 

Fig. 6 Experiment setup for all-optical packet priority comparator.

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Two packet priority bit patterns, A and B are shown in Fig. 7(a) and Fig. 7(b), respectively. The SOA1 and SOA2 are biased by 100mA, and the pump and probe signal powers are 0.97dBm and −6.8dBm, respectively. The signals measured at U and L obtained with A = 1011 and B = 0101 are shown in Fig. 7(c) and 7(d), which are then applied to SOA3 and SOA4 respectively as probe signals. The signal in Fig. 7(e) is the clearing bit stream, starting from the first bit at U port with one-bit delay, which is used as the pump signal to both SOA3 and SOA4. Figure 7(f) and Fig. 7(g) show the decision result measured at O1 ($A>B$) and O2 ($A\le B$), respectively. Since $A>B$, we have only one pulse at O1 while there is no bit found at O2. The extinction ratio of the output signal at O1 is about 6.4dB.

 

Fig. 7 Experiment result of comparison for A = 1011 and B = 01011, (a) input signal A; (b)input signal B; (c) signal at U when A[i]>B[i]; (d) signal at L when A[i]<B[i]; (e) clearing bit stream at C; (f) output at O1 when A>B; (g) output at O2 when A≤B.

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From the experiment results, we have shown that the proposed optical binary comparator operates accurately as expected enough to be used in the all-optical packet level classifier shown in Fig. 2. The proposed optical binary comparator was examined at the speed of 1Gb/s, and it can be modified to work at a higher data rate because only a timing-sensitive device, XGM-based SOA logic device is involved in the proposed scheme [6,8].

5. Conclusion

In this paper, we proposed an optical packet level classifier structure, for which a new all-optical packet priority comparator structure was proposed and examined experimentally to demonstrate its practical validity. The proposed packet priority comparator is expected to operate at a higher date rate because there is no speed-limiting device employed except the XGM-based SOA logic gates and no timing-sensitive structure such as a feedback loop control mechanism. The proposed all optical comparator is also flexible in the bit-length of packet priority bit pattern because only the length of delay lines in the bit pattern generator should be adjusted if necessary.