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A hybrid plasmonic waveguide with double low-index nano-slots is introduced. The fabrication is simple and compatible with the standard processes for SOI wafers. The theoretical investigation shows that the present hybrid plasmonic waveguide has a low loss and consequently a relatively long propagation distance (at the order of several tens of λ). For TE polarization, there is a strong field enhancement in the double nano-slots. More power is confined in the low-index nano-slots for a smaller core width. For a 50nm-wide hybrid plasmonic waveguide with double 10nm-wide slots, the power confinement factor in the nano-slots is as high as 85% and the effective area is as small as 0.007μm2 at 1550nm. Consequently, the power density in the nano-slots becomes very high, e.g., >120μm–2, which is very desired for many applications. For the present hybrid plasmonic waveguide, the lateral dimension could be less than 50nm and the calculated decoupled separation for two parallel identical waveguides is only 0.62μm, which is helpful to realize photonic integration circuits with ultra-high integration density.
©2010 Optical Society of America
1. Introduction
In order to realize nanophotonic integrated circuits (PICs) with high-integration density, we need to develop nano-scale optical waveguides. It is well known that Si-on-insulator (SOI) nanowires with an ultra-high index-contrast ∆ [1,2] and photonic crystal waveguides [3] could provide sub-μ scale optical confinement. However, these pure dielectric nanophotonic waveguides are still subject to the optical diffraction limit, which prevents the reduction of the waveguide dimension to the order of 100nm. In contrast, surface plasmon (SP) waveguides [4–12] pave a way to obtain optical confinement in the scale of 100nm or less, which makes it attractive as a potential candidate for a true nano-scale waveguiding and confinement of light. Furthermore, surface plasmon (SP) waveguide has the ability of sending both electric and photonic signals along the same circuit, which creates a bridge to connect optics and electronics naturally.
In the past years several three-dimensional structures have been reported to support highly localized fields, e.g. narrow gaps between two metal interfaces [5–8,11–13] and V-grooves in metals [9,10]. Unfortunately, such nano-scale optical waveguides are usually pretty lossy and consequently the propagation distance is usually at the scale of several micrometers.
Recently, hybrid plasmonic waveguides have attracted lots of attention due to the relatively long propagation distance, e.g., the structure with a dielectric cylinder above a metal surface [14], metal-GaAs-gap structure [15], a lossy dielectric nanowire adjacent to a metallic surface [16,17], and a Si nanowire with a metal cap [18,19]. The concept of the hybrid plasmonic waveguide was also used to lower the propagation loss of metal stripe optical waveguides [20]. In our previous work [19], our proposed Si-based hybrid plasmonic waveguide with a metal cap provides a nano-scale optical confinement as well as a long propagation distance when it operates at quasi-TM polarization. Recently the coupling between this type Si-based hybrid plasmonic waveguide and a SOI nanowire was investigated [21]. Some experimental results have also been demonstrated in Ref [22]. for this type Si-based hybrid plasmonic waveguide.
In this paper, we introduce a novel low-loss hybrid plasmonic waveguide with low-index double nano-slots. The present hybrid plasmonic waveguide works for TE polarization. By introducing double low-index nano-slots, the present hybrid plasmonic waveguide provides a very high power density in the region of low-index slots due to the field-enhancement resulting from the effects of electric-field discontinuity and surface plasmonics. Due to the field enhancement in the low-index nano-slots, a small effective area is achieved. The high power density in the low-index nano-slots is also helpful for some applications, e.g., nonlinear optics, optical sensing, etc. The present hybrid plasmonic waveguide has very small decoupled separation for two parallel identical waveguides, which is helpful to realize high density of photonic integrations. The theoretical investigation also shows that a relatively long propagation distance can be achieved. More importantly, the fabrication for the present hybrid plasmonic waveguide is simple and CMOS-compatible.
2. Waveguide Structure and Analysis
Figure 1 shows the cross section of the present structure, which consists of a silicon-on-insulator (SOI) rib and metal cladding. There is a thin SiO2 layer between the Si region and the metal cladding. In this way, double nano-slots are formed at both sides of the Si rib. The SiO2 layer at the top of the Si rib is relatively thick to minimize the metal absorption. For such a structure, the fabrication is simple and CMOS-compatible.
Figure 2 (a)-(d) show the proposed fabrication process flow for the present nano-scale hybrid plasmonic waveguide. As shown in Fig. 2 (a), one could use a standard SOI wafer. An alternative way is to use the PECVD (plasma enhanced chemical vapor deposition) technology to deposit the SiO2 and alpha-Si thin films on a Si substrate. The next step is to form a SiO2 thin film with a thickness of 100~200nm by using the PECVD technology or the process of thermal oxidation, as shown in Fig. 2 (a). The photoresist thin film is then formed on the SiO2 layer and the waveguide patterns are defined by using an E-beam lithography to have a high resolution. A dry etching process is then used to etch through the layers of SiO2 and Si (see Fig. 2 (b)). Then a very thin SiO2 layer (5~50nm) is formed at the sidewall of the Si rib by using thermal oxidation (see Fig. 2 (c)). The thickness of the SiO2 layer at the sidewall can be controlled very well by controlling the thermal-oxidation time. Due to the thermal oxidation, the Si rib will become narrower slightly (reduced by about 2w SiO2/2.7). Finally a metal film is deposited on the top, as shown in Fig. 2 (d). With the present waveguide structure, there is no need for metal patterning/etching, which makes the fabrication much easier.
Fig. 2 The proposed fabrication processes: (a) Form a ~100nm-thick SiO2 film; (b) E-beam lithography and dry etching; (c) Thermal oxidation: 10~50nm-thick SiO2; (d) Metal deposit: 100~200nm-thick.
When the SiO2 layer at both sides of the Si rib is thick (e.g., 0.5μm-thick) and the Si rib is relatively wide (e.g., 400nm), the fundamental mode field is confined well in the Si region and consequently the metal layer will hardly influence the mode field distribution. In this case, the present structure behaves like a regular SOI nanowire. However, the metal layer will give a significant influence to the guided mode when the SiO2 thickness becomes small (e.g., <50 nm). As an example, we choose the following geometrical dimensions: the Si rib width w co = 50nm, the metal thickness h m = 200nm, the SiO2 slot width w SiO2 = 20 nm, the Si rib height h Si = 340nm, and the SiO2 upper-cladding thickness h SiO2 = 300nm. We choose the wavelength λ = 1550nm and the corresponding refractive indices for all the involved materials as n metal = 0.1453 + 11.3587i (Ag) [14], n SiO2 = 1.445, and n Si = 3.455. By using a full-vectorial finite-element-mothod mode solver (COMSOL), we calculate the field distribution of the major-component Ex(x, y) for the quasi-TE fundamental mode, as shown in Fig. 3 . In our calculation, the computational window is large enough (–1μm≤x≤1μm, –1μm≤y≤1μm,) and the perfect-electric-conductor boundary-condition is used. In order to see the profile more clearly, we also plot the field distributions Ex(x, y 0) and Ex(x 0, y) (the coordinate system is shown in Fig. 1). Here x 0 = w Si/2 + w SiO2/2 and y 0 = h Si/2. It can be seen that the present hybrid plasmonic waveguide provides a very good confinement for the optical field even when the waveguide core is as small as 50nm (or even smaller).
Fig. 3 The calculated field distribution for the major component Ex(x,y) of the quasi-TE fundamental mode of the present hybrid plasmonic waveguide with w co = 50nm and w SiO2 = 10nm. Here the field distributions Ex(x 0, y) and Ex(x, y 0) are also shown. It can be seen that the optical field at the 10nm-SiO2 nano-slots is enhanced greatly.
From the curve of Ex(x, y 0) in Fig. 3, one sees that the field at the two 10nm-SiO2 nano-slots is enhanced greatly, i.e., the electric field in the SiO2 region is much higher than that in the Si region. For a pure-dielectric nano-slot waveguide, there is a similar field enhancement in the low-index region because of the strong discontinuity of the normal component of the electric field at the high-index-contrast interface [2,19]. For the hybrid plasmonic waveguide, the principle is different partially [19]. At the Si-SiO2 side interface, there is a strong discontinuity of the normal component of the electric field, which is the same as that in a pure-dielectric vertical slot waveguide. On the other hand, at the SiO2-metal interface, surface plasmon (SP) wave is excited. The electric field of the excited SP wave decays exponentially at both sides of the interface and has a peak at the interface. In the thin SiO2 nano-slots, the field distribution could be regarded as the sum of two exponential functions. When the SiO2 layer is very thin (smaller than the evanescent penetration depth), the field at SiO2 layer is enhanced greatly, as shown in Fig. 3. In the present hybrid plasmonic waveguide, the double nano-slots help to achieve a very high power confinement factor at the low-index regions even when the slot area is very small (discussed below).
First we consider the case with a relatively thick SiO2 upper-cladding, e.g., h SiO2 = 300nm, which is helpful to reduce the metal absorption at the top. Figure 4 (a) shows the real part of the effective refractive index of the present hybrid plasmonic waveguide as the core width w co varies. Here the thickness of SiO2 nano-slot is chosen as w SiO2 = 50, 30, 20, and 10nm. For a given waveguide width w co, one has a larger effective index n eff for the case with a thinner SiO2 layer. When the core width w co decreases, the effective index decreases. This can be explained by the power confinement factors in SiO2 nano-slots and Si region. Figures 4 (b) and 4(c) shows the percentages of the powers confined in the SiO2 nano-slots and Si region, respectively. From these figures, one sees that as the core width w co decreases the power confinement factor Г SiO2 in the SiO2 nano-slots increases while the power confinement factor Г Si confined in the Si region decreases. When the core width decreases to sub-100nm, the power confinement factor P SiO2 can be as high as 85%. Consequently, one could have a very high power density in the SiO2 nano-slots, as shown in Fig. 4(d). Here the power density is normalized with the total waveguide optical power [2]. For the case of w SiO2 = 10nm, the normalized power density is higher than 120μm–2. Even when the core width decreases to 30nm (see the curve for w SiO2 = 10nm in Fig. 4(b)), there is still a guided mode supported in the hybrid optical waveguide, which is very interesting to have nano-scale light confinement (similar to the other nano-scale metal waveguides). Due to the enhanced field distribution, the present hybrid plasmonic waveguide could have an ultrasmall effective area, as shown in Fig. 4(e). The effective area A eff is defined as [14]
where P(x, y) is the energy flux density (Poynting vector). of the quasi-TE fundamental mode, and P(x, y) = E(x, y) × H(x, y).Fig. 4 For the cases of w slot = 10nm, 20nm, 30nm, and 50nm, (a) the real part of the effective index of the quasi-TE fundamental mode; (b) the power confinement factor in the low-index slots P SiO2; (c) the power confinement factor in the Si rib P Si; (d) the normalized power density; (e) the effective areas A eff; (f) the propagation distance L prop. Here we choose a relatively thick SiO2 up-cladding h SiO2 = 300nm and h Si = 340nm.
From Fig. 4(e), one sees that a smaller effective area A eff is obtained when choosing a thinner SiO2 slot. For example, the effective area A eff is only about 0.007μm2 for a 50nm-wide waveguide with double 10-nm slots. It is possible to reduce the effective area further if reducing the thickness of SiO2 nano-slots. This is very useful for nonlinear optical applications or optical modulations.
On the other hand, for the realization of plasmonic waveguide devices, it is very important to allow a long propagation distance, L prop, which is defined as the distance that the amplitude of the field attenuates to 1/e, i.e., L prop = 1/(n im k 0), where n im is imaginary part of the effective refractive index n eff and k 0 is the wave number in vacuum (k 0 = 2π/λ). The effective refractive index n eff is obtained by using an FEM-based mode solver in this paper. A pure plasmonic metal waveguide usually has a propagation distance of several micrometers (e.g., 3~5 μm). For the present hybrid structure, the calculated propagation distance is shown in Fig. 4(f) as the core width w co varies. From this figure, one sees that the propagation distance usually ranges from several tens of microns to 200 microns, which is similar to those reported hybrid plasmonic waveguides [14].
From these figures, one sees that the thickness w SiO2 of the SiO2 nano-slot plays an important role for the propagation distance. For the case with a thinner SiO2 layer, the propagation distance becomes smaller. This is because the field amplitude at the interface between the SiO2 nano-slot and the metal layer becomes higher when the SiO2 nano-slot is thinner. We should note that there is a trade-off between the dimension of the plasmon waveguide and its propagation distance. Since it is easy to realize a propagation distance over 104 μm by using a singlemode SOI nanowire when the core width w co > 300 nm, we focus on the potential of the present hybrid plasmonic waveguides for a relatively long propagation as well as a nano-scale (~100nm) optical confinement (which is beyond the ability of conventional pure dielectric optical waveguides, e.g., SOI nanowires).
In the above analysis, a relatively thick SiO2 upper-cladding is considered to prevent the absorption from the metal at the top. A thick SiO2 upper-cladding will introduce a high aspect ratio especially for a very narrow waveguide, which makes the etching not easy. Thus, a thinner SiO2 upper-cladding is preferred for easy fabrication. Figure 5(a) shows the propagation distance for the present hybrid plasmonic waveguide with different thicknesses h SiO2 for the SiO2 upper-cladding. Here the slot width is fixed to w slot = 20nm and the Si rib height h Si = 340nm. It can be seen that the propagation distance for a wider waveguide (e.g., w co = 400nm) decreases greatly as the thickness h SiO2 decreases. On the other hand, the propagation distance does not change much for a narrow waveguide (e.g., w co = 100nm), which is more interesting for nano-photonic integration. In Fig. 5(b), the propagation distances for the waveguides with w co = 200, 150, 100nm are shown as the thicknesses h SiO2 decreases. One sees that the propagation distance decreases around 10% when the thicknesses h SiO2 decreases from 300nm to 20nm. In the following part, we choose h SiO2 = 150nm to make a trade-off.
Fig. 5 (a) The propagation distance L prop as the core width wco varies for the cases of h SiO2 = 20, 50, 100, 150, 200, 250, and 300nm; (b) the propagation distance L prop as the thickness h SiO2 varies for the cases of w co = 100, 150, and 200nm. Here the slot width is fixed to w slot = 20nm and the Si rib height h Si = 340nm.
When considering the integration density, it is important to examine how closely two adjacent parallel waveguides can be placed on a chip so that the cross talk (XT) between them due to coupling is negligible (e.g., XT<XT 0 = –25dB) after a propagation distance l 0 [23]. The crosstalk due to the evanescent coupling between two parallel waveguides is given by [23]
where L c is the coupling length and z is the length of the coupling section. For two identical parallel optical waveguides, the coupling length can be easily estimated with formula L c = π/(β o–β e), where β o and β e are the propagation constants of the odd and even supermodes of the two parallel waveguides, respectively, and can be calculated by using a full-vectorial FEM mode-solver.According to the requirement of XT<XT 0 after a propagation distance, the coupling length L c should be large enough, i.e.,
For example, one obtains L c(min)≈27.9l 0 when XT0 = –25dB. According to the propagation distance, usually length l 0 of the parallel part of two plasmonic waveguides in a chip is no more than 50μm and thus it is enough to neglect the coupling when the coupling length is larger than 1395μm (for XT0 = –25dB), i.e., L c(min) = 1395μm. The separation s dc which gives a coupling length L c(min) = 1395μm is defined as the decoupling separation.Figure 6(a) shows the calculated coupling length L c of two parallel hybrid plasmonic waveguides as the core width varies from 300nm to 50nm for some given separations s = 800, 700, …, 100nm. The other parameters are given as follows: h Si = 340nm, w SiO2 = 10nm, and h SiO2 = 150nm. The coupling length is given by L c = π/(β o–β e). From Fig. 6(a) one sees that there is an optimal core width for maximal coupling length when the separation is large (this is similar to the case of pure-dielectric evanescent coupling [23]). Figure 6(b) shows the coupling length as the separation increases for a fixed core width w co = 50nm. It can be seen that the coupling length increases almost exponentially as the separation D increases. This is also similar to the case of a conventional dielectric optical waveguide. According to the above definition, the decoupling separation s dc is as small as 620nm, which is helpful to have very dense photonic integration. On the other hand, the coupling length is only several micron when a small separation is chosen (e.g., s = 100nm). This is good for an ultracompact directional coupler (which is a basic element for nanophotonic integration circuits).
Fig. 6 (a) The cross section for a coupling system with two parallel identical hybrid plasmonic waveguides; (b) the calculated coupling length L c as the waveguide core width w co varies for different separations s between the two waveguides (s = 200, 300, 400, 500, 600, 700, and 800nm); (c) the calculated coupling length L c as the separation s increases for a fixed core width w co = 50nm; The decoupled separation s dc is as small as 620nm.
3. Conclusion
We have studied a Si-based hybrid plasmonic waveguide with double low-index nano-slots for nano-scale light confinement as well as relatively long propagation distance (several tens of microns). Due to the field enhancement in the low-index nano-slots for TE polarization, an ultrasmall effective area is achieved (e.g., 0.007μm2 or less at 1550nm). When the core width decreases, there is more power confined in the low-index nano-slots. The power confinement factor could be as high as 85%. In this case, the power density in the nano-slots becomes very high, e.g., >120μm–2, which is very desired for some application like optical manipulation, optical nonlinearity, etc. It has also shown that the lateral dimension of the present hybrid plasmonic waveguide could be as small as 50nm. And the coupling between two adjacent waveguide is very small even though they are placed very closely. It has shown that the decoupled separation for two parallel identical waveguides is only 0.62μm. This is very helpful to realize photonic integration circuits with ultra-high integration density. Furthermore, as the proposed fabrication flow, the fabrication of the present hybrid plasmonic waveguide is simple and compatible with the standard processes for SOI wafers.
Acknowledgment
This project was partially supported by Zhejiang Provincial Natural Science Foundation (No. R1080193) and the National Nature Science Foundation of China (No. 60688401).
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