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Reduced dark counts in optimized geometries for superconducting nanowire single photon detectors

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Abstract

We have experimentally compared the critical current, dark count rate and photo-response of 100nm wide superconducting nanowires with different bend designs. Enhanced critical current for nanowires with optimally rounded bends, and thus with no current crowding, are observed. Furthermore, we find that the optimally designed bend significantly reduces the dark counts without compromising the photo-response of the device. The results can lead to major improvements in superconducting nanowire single photon detectors.

© 2012 Optical Society of America

1. Introduction

Single photon detectors are essential components in diverse fields including quantum optics and information [1], quantum key distribution [2], lunar laser communication [3], diagnosis of integrated circuits [4] and characterization of single photon sources [5]. Superconducting nanowire single photon detectors (SNSPDs) outperform other detectors in merits such as infrared quantum efficiency, dark count rate, timing jitter [6], and maximum count rate [7]. Thus, they are considered as a promising technology for demanding photon counting applications [8].

SNSPDs are typically made of current biased meandering superconducting nanostrips (usually ∼100nm wide) with 180-degree turns. The photons are focused on the parallel nanostrips that form the active area, while the turns only serve the purpose of electrical connection. The closer the bias current is to the critical current of the nanostrips, the higher the detection efficiency, but also the higher the dark count rate [8]. Although the turns are typically placed outside the photon absorbing area, and thus do not directly contribute to the photon detection, they can degrade the overall performance of the detector by acting as current bottlenecks or by generating dark counts.

Recently, Clem et al. [9] recaped the possible impact of sharp turns on SNSPDs: the current crowds at the inner edge thus reducing the measured critical current of the meander. Also, the current bottleneck in wide superconducting strips (300nm to 1μm wide) with sharp bends has been experimentally demonstrated [10, 11]. However, an open question remains on the impact of current crowding on present SNSPDs that feature much narrower strips (∼100nm wide), in which both increased ratio of the bend curvature (due to inherent finite fabrication resolution) to nanowire width, and reduced width to coherence length ratio make the expected effect smaller [9, 11].

Here we present experiments that probe the current crowding effect on the critical current of superconducting nanostrips with a width comparable to the commonly used width in modern SNSPDs. We also report on the effect of sharp bends on the observed photo-response and dark counts.

2. Devices and setup

A typical device presented in this paper is illustrated in Fig. 1(a). A nanowire, 100nm wide and 8nm thick, is bent either 90-degree or 180-degree, and connected to large pads (not shown) by a gradual transition to wider strips. The nanowire length is ∼0.5μm on either side of the bend. Our bends fall into two categories: optimally designed with no current crowding and thus no expected critical current reduction, and traditional bends made without optimal considerations.

 figure: Fig. 1

Fig. 1 Scanning electron microscope images of the nanowires explored in this paper. (a) A typical nanowire structure examined in this paper and its connection lines. (b) and (c) two optimized 90-degree bends. (d) and (e) sharp and 45° 90-degree bends. (f) and (g) optimized and sharp 180-degree turns with 200nm spacing. (h) optimized 180-degree turn with 300nm spacing. (i) and (j) sharp and circular (radius = 50nm) 180-degree turns with 100nm spacing. The circles are eye guides with 35nm radius. Blue and red dashed lines are current streamlines calculated for a superconductor thin film enclosed by solid white lines. All the parts, except (a) share the same length scale.

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Figure 1(b) shows an example of our optimum bends. To find the optimal bend design, we numerically solve · K = 0 and × K = −d/λ2H ≈ 0 within the area enclosed by the white lines [9], where K is the sheet current density, d is the nanowire thickness and λ is the magnetic penetration depth. The boundary conditions are n · Kl = 0, and n × Ki = 0, where n is a vector normal to the edge, Kl is K on the lateral boundaries (solid white lines) and Ki is K on the input boundaries (dotted white lines). Next, we find the streamlines of the vector field K (dashed blue and red lines). Any two streamlines (dashed red lines) that enclose a surface within which |K| remains less than or equal to |Ki|, form an optimized bend (because K within them satisfies the same above boundary value problem, and |K| in the bend does not exceed |K| within the nanowire).

The approximation × K ≈ 0 used in above calculations is valid as long as wλ2/d, where w is the width of nanowire (see [9] for a thorough discussion). For typical SNSPD designs, w is less than ∼100nm while λ2/d is larger than tens of μm [10]. Therefore the condition wλ2/d is satisfied and the optimal designs remain independent of the exact values of λ and d. This brings robustness to the fabrication and also scalability of designed bends (as long as the condition wλ2/d is kept valid).

Four different 90-degree bends have been investigated: (i) optimized bend with the smallest possible footprint, (ii) optimized bend twice as big as the smallest one (to make it more tolerant to fabrication errors), (iii) sharp bend and (iv) 45° bend (as a structure between worse and best case scenarios) (see Figs. 1(b) through 1(e)). The smallest possible optimum 180-degree turn (200nm spacing) is shown in Fig. 1(f). It will be compared with a sharp 180-degree turn (200nm spacing) and a bigger optimum turn (300nm spacing) as shown in Figs. 1(g) and 1(h). Finally, Figs. 1(i) and 1(j) present a commonly used bend in present SNSPDs (sharp bend with 100nm spacing) and the same but circularly rounded (radius = 50nm).

The devices are made of 8nm thick NbTiN films deposited on oxidized silicon chips. Hydrogen silsesquioxane resist was spin-coated on top and pattered using 125keV electron-beam lithography. The write parameters were carefully tuned to achieve nanostructures as identical as possible to the designed curvatures (see red dashed lines in Fig. 1 overlayed on the nanowire images). The resist was developed in a tetra-methyl ammonium hydroxide solution, and the pattern was transferred into the film using ion beam milling with Argon gas. The critical temperature of the film before and after nano-patterning was measured to be ∼8.4K. 8nm is the total deposited material and the effective superconducting thickness might be smaller due to surface effects.

The critical current, dark count and photo response of a nanowire is a function of its dimensions (thickness and width), as well as the superconducting thin film quality. Therefore, when investigating the effect of bend design, it is essential to keep the nanowires identical except at the bend. In our experiments, we only compare a set of different bends from the designs in Fig. 1 that satisfy the following conditions: (i) the bends in a set are either 90-degree or 180-degree, and (ii) they are fabricated few μm apart on the same chip. The first condition keeps the geometries as similar as possible and therefore minimizes slight width changes when different geometries are exposed by the electron-beam. The second condition assures the nanowires share the most identical film thickness/quality as well as equivalent fabrication processing (to make effects of many factors including resist variations, proximity dose effects, and others less significant).

The nanowires on any given chip share a common electrical ground. Each of the other terminals connects to a 490nH inductor (placed next to the chip) and then to a room temperature bias-T by a coax cable (50Ω impedance). A computer controlled voltage source that measures its output current (Keithley 2400) is connected to the DC port of the bias-T via a low-pass filter (to reduce high frequency noise and interference). The high frequency response of the nanowire (after room temperature amplification) is monitored through the RF port on an oscilloscope or a programmable counter. A single mode fiber, placed several centimeters away from the chip uniformly radiates the nanowires with 1310nm photons from an attenuated pulsed laser source (width ∼200ps, repetition rate 20MHz). The 50Ω impedance together with the inductor make a large enough time constant to observe relaxation oscillations in all our current-voltage curve measurements, thus ensuring the peak current is the (experimental) critical current [12]. The measurements have been done by installing the samples in a dipstick probe and immersing it in liquid Helium (monitored temperature ∼4.2K).

3. Results and discussions

Figure 2 summarizes the critical current (Ic) measurements on 38 nanowires with different designs that were fabricated on 12 chips. The horizontal axis specifies the type of device using the characters that name the bends in the insets of Fig. 1. It divides the bends into three categories: 90-degree (black squares), 180-degree with a big enough footprint to support the optimized design (blue circles), and 180-degree smaller than the minimum size to support the optimized design (red triangles). It also sorts the bends in each category in accordance to their optimality from left to right. The symbols that are connected by solid lines show the critical currents of the nanowires within the same chip. We have confirmed satisfactory operation of our measurement setup by measuring the critical current of our devices several times and finding negligible mean normalized error (equal to ∼0.4%).

 figure: Fig. 2

Fig. 2 Measured critical currents of the nanowires. The horizontal axis specifies the type of bend design by using labels that correspond to the insets of Fig 1. The data points for the devices that were on the same chip are connected by solid lines.

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We start by looking at the data for the optimum bends for which we expect no variation in critical current due to current crowding. The average Ic of devices c and h fabricated on all chips is 16.1μA with standard deviation (σ) of 3.2/16.1=20%. For devices on the same chip, the Ic of device b compared to the Ic of device c shows an average value Icb/Icc=97% with σ = 2.0%. Also, for devices on the same chip Icf/Ich=98% with σ = 1.3%.

Little improvement from the smallest optimum design to the bigger one shows the validity of our design approach. The 2–3% improvement can be attributed to smaller current density at the inner edge of the bigger designs and therefore their improved tolerance to fabrication errors. The small deviations (2.0% and 1.3%) show reliability of the fabrication within a chip. However, the larger deviation (20%) suggests variation of parameters from chip to chip. Investigating the devices under scanning electron microscope, we have not observed significant dimension changes. Therefore, an optimum design remains optimum on all chips, and the 20% is most probably due to slight film thickness/quality change from chip to chip.

Restricting the comparison to the devices that are on the same chip, a trend becomes clearly visible on Fig. 2 for almost all the samples: the more optimal the bend, the higher the critical current. For devices on the same chip: Icd/Icc=88% with σ = 3.6%, Icg/Ich=91% with σ = 3.9%, and Ici/Icj=92% with σ = 8.5%. The average numbers show the sharpest bends considerably reduce the critical currents.

Another observation is an increase in σ when comparing two optimal bends (2.0% and 1.3%), to higher values when comparing a sharp bend with an optimum bend (3.6%, 3.9% and 8.5%). We attribute this to the uncontrollability of the radius of curvature (∼35nm, see yellow circles of Fig. 1) for sharp bends. For the devices i and j the variation is big enough to almost change device i to j (compare images in Fig. 1(i) and Fig. 1(j)). This can justify the only exception (marked by an arrow in Fig. 2) in all the data, in which contrary to the general trend a rounded bend in device j shows slightly lower Ic than a sharp bend in device i. This can also be a possible explanation for small fabrication yield of SNSPDs [8] where the large number of serially connected 180-degree turns in a meander makes having at least one very sharp bend quite possible.

We have also measured the dark counts and photon counts generated by the nanowires. The room temperature end of the fiber was blocked by a shutter for dark count vs bias current measurements. Photon counts are measured by exciting the nanowires with weak laser pulses and subtracting the expected dark counts at the same bias. We ensure single photon sensitivity by checking the linear proportionally of the photon counts with the number of incident photons [13].

Figure 3(a) shows the result for a pair of 90-degree bends (d and b) (circles), and also a pair of 180-degree bends (g and f) (squares). The sharper bends are shown by filled symbols. The photo-response of the bends that make a pair is almost similar for their common range of bias. This is expected as the devices in a pair are identical except at the small bending area. However, at the same bias current, and therefore at the same quantum efficiency, utilizing an optimum bend can reduce the dark count rate by orders of magnitude, a significant result for SNSPDs. We also note that the optimum bends allow a device to be biased with a greater absolute current value, since the current density bottleneck in sharp bends is mitigated. This enables operation at higher quantum efficiency (or longer wavelength).

 figure: Fig. 3

Fig. 3 (a) Photo-response and dark count measurements for samples of devices d/b and g/f. These samples are marked on Fig. 2 by filled symbols. (b) Dark count measurements for more samples. Each symbol is for devices on the same chip. The letters refer to insets of Fig. 1. All the lines are for eye guide.

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Illustrated in Fig. 3(b) are dark count measurements for some of the nanowires fabricated on different chips (each symbol is for devices on the same chip). Variations for critical current measurements of our optimum bends on different chips can be seen. However, on each chip the trend is the same: the sharper the bend the smaller the critical current, and the higher the dark counts.

At the inner edge of a sharp 90-degree turn with radius of curvature equal to ∼35nm, we calculate the density of the sheet current, |K|, ∼1.7 times higher than the same density for an optimized bend (smallest possible footprint). So, a vortex at the edge of a sharp turn faces almost the same barrier as a vortex at the edge of an optimum bend but at a bias current ∼1.7 times smaller (neglecting radius of curvature effects [9] which is reasonable because ∼35nm is bigger than the coherence length). Therefore, assuming vortices overcoming an edge barrier is the origin of dark counts [14], we expect having the dark count vs bias current of a sharp turn to be approximately shifted to smaller currents by ∼1/1.7. However, in none of our nanowires have we observed such a large shift. The trend of disagreement with this theory is nevertheless the same as what has been observed for critical current measurements on wider strips [10, 11]. The other possible explanations for the origin of dark counts: phase slips and unbinding of vortex-antivortex pairs [14], still need further theoretical development before application to the bending area where the edges of the strip are not straight and the current distribution is not uniform.

4. Conclusion

To conclude, we have explored the possible adverse impact of sharp turns on SNSPDs through (i) limiting their bias current and thus limiting their quantum efficiency, and (ii) generating excess dark counts not generated by straight nanowire segments where photons are detected. We expect the utilization of optimally designed bends to further push SNSPDs to more efficient single photon detection at longer wavelengths while generating less dark counts.

Acknowledgments

We acknowledge the financial support of OCE, NSERC and IQC. The authors would like to acknowledge Robin Cantor for helpful comments. This work was performed in part at the Center for Nanoscale Systems (CNS), a member of the National Nanotechnology Infrastructure Network (NNIN), which is supported by the National Science Foundation under NSF award no. ECS-0335765. CNS is part of Harvard University.

References and links

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Figures (3)

Fig. 1
Fig. 1 Scanning electron microscope images of the nanowires explored in this paper. (a) A typical nanowire structure examined in this paper and its connection lines. (b) and (c) two optimized 90-degree bends. (d) and (e) sharp and 45° 90-degree bends. (f) and (g) optimized and sharp 180-degree turns with 200nm spacing. (h) optimized 180-degree turn with 300nm spacing. (i) and (j) sharp and circular (radius = 50nm) 180-degree turns with 100nm spacing. The circles are eye guides with 35nm radius. Blue and red dashed lines are current streamlines calculated for a superconductor thin film enclosed by solid white lines. All the parts, except (a) share the same length scale.
Fig. 2
Fig. 2 Measured critical currents of the nanowires. The horizontal axis specifies the type of bend design by using labels that correspond to the insets of Fig 1. The data points for the devices that were on the same chip are connected by solid lines.
Fig. 3
Fig. 3 (a) Photo-response and dark count measurements for samples of devices d/b and g/f. These samples are marked on Fig. 2 by filled symbols. (b) Dark count measurements for more samples. Each symbol is for devices on the same chip. The letters refer to insets of Fig. 1. All the lines are for eye guide.
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