1. Introduction

Silicon photonics benefits from the wealth of experience and the infrastructure of the Si electronics industry, and the compatibility of Si photonic circuits with CMOS electronics allows for mass production of low cost integrated photonic/electronic circuits [1,2]. Silicon-on-insulator (SOI) substrates [3] are an attractive medium for making silicon photonic integrated circuits (PICs). For Si PICs, switching and modulation devices are indispensable components. Thermo-optic effect is one of the preferred options for optical switching in compact SOI photonic devices. Photonic crystal structures can be incorporated into these devices to help shrink the interaction length based on the slow light effect [4]. In recent research, thermo-optic switching and modulation in ultra-compact photonic crystal structures have been studied [5–10]. However, the performance of these structures varies widely. For example, the power consumption of most of these structures ranges from 2mW to tens of milliwatts. As these structures vary widely in their size, design, and the group velocity of light, it is not always clear what physical factors are crucial to their performance. A theory that can describe the thermo-optic characteristics of an SOI photonic crystal structure as explicit functions of various parameters is desired. Note that the understanding of such thermo-optic characteristics could also help control the thermo-optic effect in photonic crystal electro-optic modulators and other active devices [11–13].

A photonic crystal thermo-optic device on an SOI chip comprises structural components whose scales differ by orders of magnitude, such as small holes of ~200nm in diameter and thick substrates of hundreds of microns. Simulations of such a multi-scale structure can be time-consuming and challenging. Such simulations may be performed for a small number of structures. However they are not efficient for systematically studying a large ensemble of structures in which many parameters such as the hole diameter and the buried-oxide thickness vary over a large range. Here we develop an efficient and accurate approach to analyze the thermo-optic characteristics of an SOI photonic crystal structure. The effective thermal conductivity κ_eff for a silicon photonic crystal slab is determined through the lateral thermal spreading length. Physical properties such as the spatial temperature profile and the power consumption required to induce a π phase shift can be described semi-analytically based on a quasi-1D model with numerically determined κ_eff. The results agree well with 3D simulations based on the finite element method (FEM). The theoretical results also explain the low switching power observed in an air-bridge structure [6]. The analytic formulas offer insight into the key factors governing the thermo-optic characteristics of SOI photonic crystal structures.

2. Analysis of SOI photonic crystal thermo-optic structures

Figure 1 illustrates two common configurations of active photonic crystal waveguide (PCW) structures on an SOI wafer. A heat source of width W and length L is assumed to be embedded in the top silicon layer. Such a heat source can be formed by a lightly doped (e.g. ~10¹⁴cm⁻³) Si strip surrounded by a relatively highly doped (e.g. ~10¹⁷cm⁻³) silicon on both sides [6]. Passing current laterally through this structure produces concentrated ohmic heating in the center strip.

 

Fig. 1 Configurations of Si active PCW structures. (a) SOI; (b) Air-bridge (membrane).

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The heat conduction process in a photonic crystal slab can be effectively modeled by that of an equivalent hole-free homogeneous slab with an effective thermal conductivity κ_eff. This is valid because the temperature varies spatially on a scale much larger than the typical photonic crystal lattice constant a. To determine κ_eff, the heat transfer process is simulated using the finite element method for one period of the PCW structure, as shown in the inset of Fig. 2 . The thicknesses of the top Si layer and buried oxide layer are t_Si = 250 nm and t_ox = 2 μm respectively. The hexagonal lattice has a lattice constant a = 400nm. The simulations indicate that the vertical temperature variation in the top Si layer and the in-plane temperature variation in each unit cell are small. The temperature of the top Si layer varies significantly only along the x axis, as plotted in Fig. 2. Outside the heater (centered at x = 0), it closely follows an exponential form

 

Fig. 2 Temperature profiles in the top Si layer of a PCW (center: x = 0) for various hole radii and in a homogenized slab with κ_eff(r). Inset: 3D temperature profile in a PCW with r/a = 0.25. One period of the PCW along the y axis is shown.

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For a photonic crystal slab, X_spr(r) depends on the hole radius r and it can be obtained from an exponential fit of the lateral temperature profile in the slab. The effective thermal conductivity of a Si photonic crystal slab can then be calculated from

The values of κ_eff/κ_Si and X_spr determined from the plots are given in Table 1 . To further verify the results, homogenized slab structures with the tabulated κ_eff(r) are simulated, with all other parameters unchanged. The lateral temperature profile in the homogenized slab is generally in good agreement (within 6%) with that of the original photonic crystal slab, as shown in Fig. 2.

Table 1. Values of X_spr(r) and κ_eff(r) for Various Hole Sizes

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For an SOI structure, the heat conduction can generally be described by a quasi-1D model predicated on the vertical heat conduction in the buried oxide [14,15]. Note that the thermal spreading increases the effective heat flux cross-section to A_eff = L[W + 2X_spr]. For the photonic crystal structure in Fig. 1(a), this model yields

 

Fig. 3 ΔT_ox/Q vs. waveguide length L (for t_ox=2μm). Inset: 3D temperature distribution in a chip obtained from finite element simulation for a PCW structure having t_Si=250nm, W=400nm, t_ox=2μm, κ_eff(r=0.25a) on a 200μm×200μm substrate with a thickness of 100μm.

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Due to the small thermal conductivity and natural convection coefficient of air [16], the heat dissipation from the top and side surfaces of the chip is negligible, hence adiabatic boundary conditions are used for the top and side surfaces [7,17]. The bottom surface is kept at 300 K. The simulated ΔT_ox per unit heating power Q and the results based on Eq. (4) agree well (within 3%), as shown in Fig. 3 for various lengths of the heat source.

3. Thermo-optic characteristics and switching power for SOI and air-bridge structures

To study the thermo-optic characteristics, we note that the phase shift induced in a PCW is given by [4]

Because$X_{spr}~\sqrt{t_{ox}}$, the power Q_π actually scales as $1/\sqrt{t_{ox}}$ for heater width W<<X_spr. Figure 4 shows the results for σ = 0.9, λ = 1.55μm and dn/dT = 1.86 × 10⁻⁴ K⁻¹ with different values of oxide layer thickness. For n_g = 60, r/a = 0.25 and t_ox = 2μm, Q_π is less than 2.5mW.

 

Fig. 4 Q_π vs. group index (n_g) for r/a = 0.25 for an SOI PCW structure (for various t_ox), and the estimated 3dB-propagation-loss length for a membrane PCW structure. Inset: The thermal enhancement for a membrane PCW with t_ox = 2μm.

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This approach can also be applied to an air-bridge (membrane) structure shown in Fig. 1(b). Here the heat conduction consists of two steps in series: (1) the lateral heat conduction in the suspended membrane; and (2) the quasi-1D heat conduction in the SOI region. Based on the continuity of heat flux, one readily finds for the left (or right) half membrane

For the same power Q, the membrane structure may enhance the temperature rise by a factor

Correspondingly, Q_π of the membrane structure is reduced by this factor. The enhancement factors obtained from Eq. (9) agree very well (within 6%) with the simulation results, as shown in Fig. 4 inset. Based on Fig. 4, the attainable power consumption for a Si air-bridge PCW thermo-optic Mach-Zehnder switch is estimated between 1~2mW for n_g~60 and t_ox = 2μm, which agrees well with the experimental result [6].

4. Discussions

The scaling of the thermo-optic characteristics of an SOI photonic crystal structure with various parameters is of significant interest in device design. The analytic formulas enable us to study such scaling over a wide parameter range. The heater location is an important factor in determining the power consumption. Here we consider two options: in the PCW core [6], at the lateral edge of the PCW [8]. The temperature profile given in Eq. (1) shows that the temperature rise in the silicon layer decreases exponentially with the lateral distance from the heater. Compared to a heater embedded exactly in the PCW core, a heat source located at Δx = 6μm from the core has an efficiency reduction by exp(−6μm/X_spr)≈0.3~0.4 for r/a = 0.25~0.35. The buried oxide thickness is another crucial factor. Generally, a thicker oxide is preferred for lower power consumption according to Eqs. (6) and (8). However, the thermal time constant of an SOI chip increases with the oxide thickness. Therefore, some trade-off must be made in realistic device design to balance power consumption and speed. For the membrane structure, the enhancement factor in Eq. (9) is found to weaken the scaling of Q_π with t_ox due to X_Si ~$\sqrt{t_{ox}}$. Thus, Q_π scales slower than $t_{ox}{}^{-1/2}$, particularly for a large W_membrane. Ultimately, the reduction of Q_π based on the slow light effect is limited by optical loss, which increases with n_g. The optical loss of a PCW can be attributed to a number of factors, such as random variation of hole positions due to fabrication tolerances, sidewall roughness, and the input/output coupling. The random variation of the hole positions in fabricated PCWs can be controlled to be within a small range (<1nm) with high-end e-beam lithography tools [18]; and the corresponding loss is usually small. Sidewall roughness of the holes depends on the lithography tool, resist, and etching process and is more difficult to control. Such roughness could induce substantial loss at large n_g. The estimated PCW length for 3dB propagation loss is plotted against n_g in Fig. 4 based on theoretical calculations with experimentally achievable rms roughness σ = 3nm and correlation length l_c = 40nm [19]. To further address the effect of the input/output coupling loss, we consider two prior experiments [6,20]. In an earlier experiment [6], the insertion loss of well-fabricated PCWs is about 10~13dB at n_g~110 for L = 50μm and 250μm and shows weak dependence on the PCW lengths. This indicates that most of the observed loss is due to input/output coupling [6]. A more recent experiment based on group index tapering has shown that the coupling loss can be significantly reduced throughout the spectrum of the defect-mode, including the slow light region near the band edge [20]. To summarize, with the best fabrication tools and best design, optical loss due to random hole position variation and input/output coupling can be very small, but the roughness induced loss [19] (especially the backscattering loss, which scales roughly as n_g²) will be a primary limiting factor. Hence the roughness-induced loss (including backscattering and out-of-plane scattering loss) is considered in Fig. 4 to explore the limit of Q_π in connection with n_g. Considering all the factors discussed above, a practical lower limit of Q_π is estimated on the order of 0.5mW for a reasonable t_ox~5μm, L~10μm, and n_g~110. Our calculation also shows that for n_g~60, Q_π already enters the sub-milliwatt regime for the t_ox~5μm case.

It should be noted that this theory indicates that many factors are insignificant. For example, Q_π is insensitive to the choice of the heater width W as long as W<<2X_spr(~12μm). Also, Q_π varies only ~20% for the typical radius range of r/a = 0.25~0.35. Note that typical silicon photonic crystal waveguides used for the 1550nm communications window have a = 380nm to 440nm. As the lattice constant is much smaller than the scale of temperature variation (a<<X_spr), this approach works well for this range of a. For a given lattice structure, when a and r vary simultaneously while maintaining a fixed ratio of r/a, X_spr is essentially invariant. Note that the power Q_π given above is for switching and steadily holding a state. This is pertinent for most optical switching applications that require holding a switching state steadily over an extended period. The thermal time constant of an SOI structure is $\tau ~t_{ox}^2{\rho }_{ox}{c}_{ox}/{\kappa }_{ox}$ (~μs for t_ox = 1~2μm), where ρ_ox is the density and c_ox the specific heat capacity of SiO₂. Our simulations confirm that τ is relatively insensitive to the details of a photonic crystal structure. Although the heating transient can be shortened [7,14], the overall performance of a switch over an extended period is limited primarily by Q_π and τ given above. The effect of the temperature drop in the substrate is less than 10% for all cases we simulated. Note that κ_eff used in this work is obtained based on the structured “porosity” of materials within the framework of classical heat transfer theory, neglecting quantum mechanical effects such as phonon scattering in a periodic structure [21]. When quantum effects are considered, most formulas in this work remain useful, except κ_eff values from quantum mechanical calculations will be used.

5. Summary

In conclusion, the thermo-optic characteristics of active photonic crystal structures on an SOI platform are investigated semi-analytically. The power consumption Q_π and spatial temperature profile are given as explicit functions of structural, thermal, and optical parameters. The results agree well with FEM simulations and also explain the low switching power in air-bridge structures. The scaling of Q_π with key physical parameters is analyzed. The practical limit of Q_π is estimated on the sub-milliwatt level considering all key factors.