1. Introduction

Photonic analog to digital converters (PADC) have been intensely researched over the last three decades, motivated by the slow improvement trend in bandwidth-resolution performance of electronic ADC, and spurred by the unique advantages of photonics. Starting with the early 70’s, researchers provided proof-of-concept of PADC systems, taking advantage of various optical properties, in order to photonically accomplish sampling and/or quantization [1–40].

The objective of this paper is two-fold: (i): To identify a common phase-domain-zero-crossings principle underlying photonic quantization ADC schemes [25–30] including our own contribution [30], further interpreting these schemes as equivalent to a generic Flash ADC structure. (ii): To introduce and analyze a novel Spatially Distributed Successive Approximation Register (SDSAR) PADC with improved performance and reduced complexity relative to the prior Flash PADC structures.

Briefly surveying the PADC field, we note that significant PADC advances in the last 30 years have mainly occurred in the field of photonic sampling [1–6], [31–38]. This field has nicely progressed, capitalizing on the availability of fast electro-optic modulators, in order to effect high precision sampling by mixing the optical sampling combs with RF electrical signals under-test. In particular the very low aperture jitter, of the order of low tens of fsec or lower, was exploited, as attainable with time-domain optical combs generated by mode-locked-lasers (MLL) [41, 42]. In the photonic-sampled-electronically-quantized approach, the intensity of each optical pulse is modulated by the time-samples of the voltage-under-test, while the detected electrical signals are further quantized by means of a conventional electronic ADC. This approach does not directly address the difficulty inherent in performing electronic quantization at high speed. However, various all-optical parallelization techniques have been proposed, based on time and/or wavelength interleaving enabling to “divide-and-conquer” the quantization task. An ultra-fast stream of optical samples is de-multiplexed into multiple tributaries to be processed by multiple slower quantizers, such as a bank of electronic ADCs with sufficient amplitude resolution. An alternative emerging approach allowing to effectively sample and quantize ultra-fast waveforms with slower ADCs, is the time-stretch photonic data conversion technique. Spectacular performance was demonstrated up to the TeraHz range (e.g [7–10].), albeit requiring bulky optical-bench lab-room systems, not amenable to photonic miniaturization. The time-stretch approach may nevertheless be used as a bandwidth extension front-end for any other electronic or photonic ADC system.

In our assessment, the most practical PADC approach to date is the real-time photonic-sampled-electronically-quantized one [1–6], based on the so-called ‘phase-encoded optical sampling’. In this approach, the sine non-linearity arising in the modulation and interference processes is mitigated by digital post-processing, following electronic A/D conversion. The combination of this “phase-encoded” approach with all-optical parallelization methods produced opto-electronic ADCs exceeding the performance of their purely electronic counterparts. Notable is also the emerging trend towards Silicon integration of the electronic and photonic circuits [11–14]. We further remark that photonic sub-sampling of bandpass narrowband signals, e.g [32], [43, 44], enabled by the high precision down-sampling using the ultra-low jitter optical combs, is a useful technique for applications requiring digitization of bandpass RF signals. However, this passband configuration is less demanding than wideband photonic sampling around baseband. This indicates that the Effective Number of Bits (ENOB) performance of various PADC systems quoted in the literature should be meaningfully compared referring to the passband bandwidth, rather than the electrical carrier frequency.

Further to photonic sampling with its well-established ultra-low jitter advantages, it would be advantageous to direct perform the high-speed quantization in the photonic domain, which is our interest in this paper. There has been a plethora of photonic quantization research papers published on the topic [15–30], starting with Taylor’s pioneering paper [15], based on parallel processing by a bank of modulating interferometers with free spectral ranges forming a binary {1,1/2,1/4,…} geometric sequence. Variations on the original Taylor scheme [19–24] have kept appearing in recent years. Unfortunately, the various real-time high-speed photonic quantization approaches, as proposed, analyzed and demonstrated over three decades, for broadband (say $\ge 5$GHz) signals are yet to exceed 3-4 Effective Number Of Bits (ENOB). Notice that new types of photonic quantizers, operating on different principles than the Taylor scheme, were proposed and demonstrated [25–30]. However, the various PADC proposals were typically presented in a fragmented way, each paper focusing on its own specific physical circumstances. No attempt was made at identifying a systematic unified theme underlying the various schemes. Moreover, the fundamental limits of performance for these classes of PADC systems were not clarified, and some speculative claims were occasionally stated regarding projected ENOB performance.

In this paper we pursue a structured approach to analysis and synthesis of PADC systems, electing to single out the optical phase as the relevant quantity to be sampled and linearly quantized (rather than quantizing the optical intensity and possibly linearizing it as is the “phase encoded” approach). We adopt electronic ADC architectures heretofore never introduced to PADC, such as the Successive Approximation Register (SAR). The rationale for electing optical phase as the quantity to linearly encode the voltage-under-test into, is that interferometry excels at generating comparisons between optical phases, and the technology motivation is that stable interferometers may be realized onto photonic integrated circuits (PICs). However, we must still devise a method to prevent the sinusoidal interference non-linearity, mapping optical phase to intensity, from being manifested as ADC non-linearity. Notice that our stated goal of direct photonic quantization precludes digital post-correction of the sine non-linearity, as per ‘phase-encoded’ techniques [1–6], which rely on electronic quantization. In fact such a method has already been implicitly resorted to, in the photonic quantizers [25–30] published in recent years, including our own contribution [30]. Our ‘paradigm shift’ consists of identifying an alternative mechanism extracting phase information in a way avoiding the sinusoidal non-linearity, underlying these works. The key concept is making multiple binary decisions whether the phase-under-test is to the left or right of the zero-crossings of multiple phase-to-intensity transfer characteristics. If the zero-crossings are evenly spread, the overall PADC transfer characteristic becomes linear (regular staircase), despite the basic sine non-linearity of each of the horizontally shifted transfer characteristics. It is the uniform positioning of the shifted zero-crossings of the sinusoidal characteristics along the phase axis that determines the overall linearity of the A/D conversion process. We may generally refer to our PADC approach as phase-domain-zero-crossings based (this approach is distinct from the prior ‘phase-encoded’ approaches in the literature, as reviewed above).

The first step in our structured approach is to identify fundamental optical building blocks acting as phase comparators (1-bit ADCs), based on interferometric comparison of phases in well-known balanced photo-detection configurations, as well as interpreting phase modulation with a bipolar electrical pulse as an optical 1-bit DAC basic building block. Once equipped with these basic building blocks, we proceed to the next level, synthesizing compound systems, namely multi-bit PADCs. We follow a structured approach systematically porting and adapting known electronic ADC quantization architectures to photonic ADC, namely the Flash and Successive Approximation Register (SAR) classical ADC structures. We construct more complex PADC systems out of the basic aforementioned phase-domain building blocks, namely the 1-bit ADC and 1-bit DAC elements. We essentially mimick the known electronic ADC architectures, albeit with certain adaptations taking advantage of unique photonic strengths.

We already introduced a photonically quantized Flash ADC in [30]. Here we briefly indicate that that structure indeed falls in the phase-domain-zero-crossings PADC class. We also briefly indicate that additional recent PADC quantization proposals [25–30] are also equivalent to our Flash PADC.

Having developed the phase-domain-zero-crossings paradigm shift, the remaining key objective of the paper is to propose and numerically evaluate a novel SAR-like photonic ADC integrated-optic structure, to which we refer as Spatially Distributed SAR (SDSAR), as it is reminiscent of a classic Successive Approximations Register (SAR) ADC. Actually, for those versed in electronic ADC architectures, our new SDSAR structure amounts to a hybrid between a classic SAR structure and a pipelined ADC with unity inter-stage gains. This unique PADC structure, making use of both the 1-bit ADC and DAC building blocks, is not equivalent to any of the previous photonic ADC schemes in the literature. Remarkably, it is significantly more optical-power-efficient than prior Photonic Flash architectures (including ours) [25–30], especially for a large number of bits.

After describing the principle of operation of the new PADC system, the paper proceeds to work out upper bounds on the resolution performance (ENOB) for both the Flash and SDSAR PADC schemes, analytically as well as by means of extensive Monte-Carlo numeric simulations of the photonic quantization process. Our model incorporates the quantization noise, the shot noise, and the receiver thermal and DAC thermal voltage noise sources. Our findings indicate that the previous Flash structures [25–30] may be virtually limited to <6 ENOBs whereas the novel SDSAR structure performance would be in principle bounded to <12 ENOBs with an optical comb generator (OCG) generating an average optical power of 50-100 mW (which is within state-of-the-art of commercial MLL).

We must qualify our ENOB statements above as representing upper bounds on performance, likely to be dragged down by additional higher-order opto-electronic impairments and imbalances, in particular PIC and photo-diode non-linearities, hence there is little point speculating on the final projected performance of the SDSAR. Nevertheless, a key conclusion is that the novel proposed SDSAR is, in principle, substantially more optical-power efficient and less complex than the Flash PADC [25–30]. Also, it is less complex than the Taylor-like devices [15], [17–24], thus the SDSAR will relatively realize more ENOBs than existing Flash and Taylor schemes, whatever the final ENOB numbers might be.

The paper is structured as follows: Section 2 introduces the Phase Comparator as building block of interferometric phase-domain PADCs. Section 3 introduces our novel SDSAR PADC and its principle of operation. Section 4 discusses the resilience of phase-domain PADCs to opto-electronic impairments. Section 5 compares between the Flash, SDSAR and prior photonic-quantized PADCs systems. Section 6 develops the theoretical modeling of our SDSAR PADC system. Section 7 develops the numerical simulation model. Section 8 presents the resulting ENOB performance plots of the Flash and SDSAR PADCs – both analytic and numeric. Section 9 analyses the PADC impairment due to mode-locked-laser optical source timing jitter. Following the concluding remarks of section 10, Appendices A,B elaborate on requisite ADC background, while Appendix C derives the SNR limitation due to jitter. Appendix D lists all abbreviations used in this paper, for the readers’ convenience.

2. Phase comparator as basic building block of interferometric phase-domain PADCs

Surprisingly, the PADC work described in the literature so far has taken little advantage of the art and science of incumbent electronic ADC systems (with which it aims to compete). We initially invested time to assimilate electronic ADC techniques, which has led us a more systematic assessment of prior art PADC work, aiming at identifying the underlying structure, and establishing whether it matches existing electronic ADC generic architectures. We realized that a key enabling PADC element would be a photonic comparator with arbitrarily positioned threshold. Implied in such fundamental building block sub-module is a linear mapping mechanism from the voltage-under test to some photonic quantity.

Overview of phase-domain-zero-crossings encoding and Flash ADC: In some conventional PADCs, the voltage-under-test, $v_{IN}(t)$, is encoded as optical intensity. This encoding is non-linear, as it is typically generated by an electro-optic modulator, which linearly maps $v_{IN}(t)$ into optical phase $\varphi (t)$, and in turn, the phase is non-linearly mapped into intensity by the lightwave interference process – usually according to a sine function: The intensity and detected photocurrent have the functional form $I(t)=I_0+I_1\sin \left[\varphi (t)-\theta \right]$ for single-ended detection and $I(t)\propto I_1\sin \left[\varphi (t)-\theta \right]$for balanced detection. In the so-called ‘phase-encoded’ approach [1–6], which has heretofore achieved the most practical results, the phase is extracted out of the non-linear mapping $i(t)$, by electronically quantizing the photocurrent with multiple bits and applying some digital post-processing to linearize the sinusoidal interference characteristic in the electronic domain. In our approach, we focus on the linear mapping of $v_{IN}(t)$ into optical phase $\varphi (t)$ (referred to as the phase-under-test), the time-samples of which are imparted onto a train of optical sampling pulses, by means of a photonically-integrated electro-optic modulator front-end. Thus the output of the PADC optical front-end may be visualized as a train of equi-amplitude optical pulses, with the optical carrier underneath the pulses envelope being shifted in phase from one pulse to another, such the relative zero-crossing positions in each pulse linearly encode corresponding samples of the voltage-under-test, taken at equi-distant time instants, $T_s=f_s^{-1}$ corresponding to the pulse arrivals at the E-O modulator (here $f_s^{}$is the ADC sampling rate, equal to the optical pulse train repetition rate) The phase-under-test, ${\varphi }_k\equiv \varphi (k{T}_s)$, with k a discrete-time index labeling the samples (optical pulses), may be visualized as a complex point $e^{j{\varphi }_k}$on the unit circle in the complex plane. In our methodology, as ${\varphi }_k$ is mapped photo-current, neither can we avoid the sine non-linearity, which is inevitably generated in the lightwave interference process. However, rather than aiming to reconstruct the amplitude level of the resulting photo-current, we repeat the phase-to-intensity mapping process multiple times, in effect generating multiple copies of $I^{(i)}(t)\propto \sin \left({\varphi }_k-{\theta }^{(i)}\right),i=0,1,2,\mathrm{....},C$, and each of these photo-currents are quantized with a single bit, in order to determine whether ${\varphi }_k$ is to the left or the right of the multiple zero-crossings ${\theta }^{(i)}$of the sine function. It is the role of the PADC backend to measure (i.e. quantize) the optical phase-under-test riding on each pulse, by means of comparisons to the multiple thresholds ${\theta }^{(i)}$, all performed in the angular domain. This effectively localizes the phase-under-test, ${\varphi }_k$, in one of multiple bins $\left[{\theta }^{(i-1)},{\theta }^{(i)}\right]$ along the phase axis.

E.g., for uniform quantization, the unit circle is partitioned into M equal angular sectors by thresholds ${\theta }^{(i)}=i\cdot \pi /M=i\cdot 2\pi /2^B,i=0,1,2,\mathrm{...},M-1$, and the PADC determines which of these angular sectors ${\varphi }_k$ belongs to, by means of multiple phase comparisons. The various PADC types are distinguished by the sequence of angular thresholds used, as well by the means to generate the angular thresholds using diverse optical structures. The Flash PADC scheme we introduced in [30] is a particular example of such phase-domain PADC. In that Flash PADC device, $N=2M=2^B$ thresholds are uniformly spread over the unit circle. “Flash” A/D conversion means that all the phase comparisons are performed in parallel, by splitting the phase modulated optical comb to $M=2^{B-1}$ phase comparators (P-CMP), as shown below. It turns out that some PADC schemes introduced in recent years [25–29] are also mathematically equivalent to a Flash PADC in the phase-domain (thus, are also mathematically equivalent to our prior scheme [30], though the levels of performance and opto-electronic complexities may be different).

In contrast, in the novel SDSAR structure introduced in section 3, it will be seen that a binary search sequence is performed in the phase domain, such that the successive angular displacements of the thresholds from each other form a geometric sequence with ratio ½.

2.1 Phase comparator (P-CMP) as fundamental PADC building block

The Flash schemes [25–30] as well as the SDSAR scheme to be introduced in this paper, and also the Taylor-like schemes [15], [17–24], are essentially interferometric PADC methods, either implicitly or explicitly resorting to multiple phase comparator modules, which are the basic underlying building blocks. One can have either single-ended or balanced phase comparators. It turns out that the P-CMP balanced design (Fig. 1 ) is 3 dB more efficient in SNR and also more resilient to common mode amplitude and phase impairments and will thus be exclusively adopted in this paper, however we note that many prior PADC systems were realized with single-ended P-CMP, mixing two light beams onto a single photo-diode (PD), the electronic output of which is thresholded half-way at the mean photo-current level. In this paper P-CMP will refer to the balanced photo-detection structure described in Fig. 1. Internally, the phase-comparator building block is in turn realized as a phase-detector followed by a 1-bit ADC (The 1-bit ADC is alternatively described as slicer, sign-detector, comparator-to-zero or monobit ADC).

 

Fig. 1 Fundamental PADC building block – the Phase Comparator (P-CMP). (a) The P-CMP block diagram and opto-electronic realization of the Phase Detector as a directional coupler terminated in a balanced photo-diode pair. A sign-detector (slicer) acting on the balanced photo-diodes photocurrent completes the P-CMP function; the two P-CMP effective inputs are the optical phases ϕ, θ and the output is a bit indicating whether or not ϕ>θ. (b) Transfer characteristic of the phase detector (normalized photo-current vs. phase ϕ). The slicer following the Phase-Detector determines which of the two half-circle angular decision regions, delineated by the diameter at angle θ, the phase under test falls in.

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Phase-Detector (PHD): This sub-module essentially consists of a 3-dB Directional Coupler (DC) terminated in a balanced photo-diode (PD) pair (Fig. 1). An extra phase-shift of ${90}^{\circ }$or λ/4 is inserted in one of the DC ports. The PHD then generates a photocurrent proportional to the sine of the difference between the two optical phases $\theta ,\varphi$ at the two DC ports. Upon integration of the photocurrent in an integrate&dump (I&D) electronic circuit (which is considered part of the PHD), the output voltage $V_d$ is proportional to the integrated photo-current current, i.e. to the accumulated charge, expressed here for convenience as the accumulated number of photo-electrons per sample,$K_d=q_d/e$, with e the electron charge, given by the following relation, derived further below, which expression should appear plausible to those cognizant of interferometric principles (The derivation further below, is akin to that for the output of the Q branch of a 90 deg IQ hybrid used in coherent detection):

As the sine is a monotonically increasing odd function of its argument around zero, it follows that the polarity of $\sin (\theta -\varphi )$ coincides with that of $\theta -\varphi$:

Phase wrap-around: At this point it remains to clarify a unique aspect of the phase-domain encoding, which seems to have been first noticed in [25, 26]. The fundamental angular range which the voltage-under-test, as well as the reference phase, are mapped onto, is $2\pi$, e.g. $\varphi ,\theta \in \left(-\pi ,\pi \right)$. Over the $\pm \pi$ angular range, $\sin \left(\varphi -\theta \right)$ has two zero-crossings, distinguished by whether $\sin \left(\varphi -\theta \right)$ is a monotonically increasing or decreasing function of its argument around the zero-crossing point. The description is best carried out onto the unit circle in the complex plane. As indicated in Fig. 1b, upon setting an angular threshold $\theta ={\theta }^{(i)}$ (the i-th PADC level), the corresponding P-CMP Boolean output $b=0,1$ indicates whether the phase under test, $\varphi$, falls onto one of the two half-circles, respectively situated clockwise or counterclockwise from the ray making an angle $\theta ={\theta }^{(i)}$ with the real axis. Indeed, all points $\varphi$ on the half-circle situated clockwise from $\theta ={\theta }^{(i)}$ satisfy $\pi >\theta -{\theta }^{(i)}>0\Rightarrow \mathrm{sgn}\left\{\sin \left(\varphi -\theta \right)\right\}=+1$; all points on the half-circle situated counter-clockwise from $\theta ={\theta }^{(i)}$ satisfy $2\pi >\theta -{\theta }^{(i)}>\pi \Rightarrow \mathrm{sgn}\left\{\sin \left(\varphi -{\theta }^{(i)}\right)\right\}=-1$. Thus, the Boolean variable $b^{(i)}=\mathrm{sgn}\left\{\sin \left(\varphi -{\theta }^{(i)}\right)\right\}$identifies which of the two half-circles we are on.

Equipped with the fundamental P-CMP building block, and recalling that optical phase linearly encodes the voltage-under-test in our approach, we proceed to conceive complete PADC structures, emulating architectures used in electrical ADC systems, with specific adaptations suited to the unique traits of the optical medium.

Signal Analysis for the Phase Comparator: We now derive the P-CMP formula in Eq. (1), clarifying the underlying physics in the process. Let $P_r(t)$be the total optical power received in a single pulse at the two coupler ports. We have equal optical powers $P_r(t)/2$at the two input ports of 3 dB directional coupler (DC). Assume for now zero excess loss in the directional coupler, then the total power at the output pair of ports is $P_{\Sigma }(t)+P_{\Delta }(t)=P_r(t)$, where $\Sigma /\Delta$denotes the constructive/destructive output port of the 3 dB DC. The photocurrents generated in the PDs connected to the $\Sigma /\Delta$ports of the directional coupler are readily derived:

The received effective photo-current is then also rectangular, $i_r(t)=i_{peak}{1}_{[0,{\tau }_p]}(t);i_{peak}=\rho P_{peak}$, thus Eq. (3) yields:

Notice that for the assumed rectangular pulses the I&D is actually the optimal matched filter. This circuit essentially measures the charge in the received pulse $i_d(t)$, yielding a charge sample $q_d={\displaystyle {\int }_0^{{\tau }_p}{i}_d(t)dt}$. The number of electrons in this accumulated charge, to be referred to as the photo- count, is given by $K_d=q_d/e=\frac{1}{e}{\displaystyle {\int }_0^{{\tau }_p}{i}_d(t)dt}$. From Eq. (4) and Eq. (5):

The detected photo-count, $K_d$, represents the charge sample at the matched filter (I&D) output, due to the reception of a single optical pulse, scaled by $\frac{1}{e}$, i.e. expressed in electron units. This completes the derivation of the interferometric relation in Eq. (8), first quoted in Eq. (1).

In the ADC context, conditioned on $\varphi$ falling in the ADC bin (quantization interval) with transition level $\theta$, then $\Delta \varphi \equiv \varphi -\theta \ll 1$ (in each quantization interval the phase-under-test is close to the threshold $\theta$, thus $\Delta \varphi$ is small), and Eq. (8) may be approximated as:

This simple $K_d\cong K_r\cdot \Delta \varphi$proportionality relation may be used to map noise and fluctuations back and forth between the angular ($\Delta \varphi$) and photo-count domains ($K_d$).The P-CMP output is a function of the phase-difference between its two inputs, which was equal to $\varphi$-$\theta$in this example. Later in this paper, $\varphi$ will represent the phase-difference induced by the voltage-under-test and $\theta$ will represent an additional reference phase, thus the input phase-difference to the P-CMP would also be equal to $\varphi$-$\theta$.

3. Novel successive approximation register (SAR) PADC – the SDSAR

By now we have developed sufficient background, including proficiency in phase comparator building blocks, in order to introduce our novel improved Spatially Distributed SAR (SDSAR) PADC in this section. The remainder of the paper is devoted to analyzing and deriving the performance of this new PADC type, mainly comparing it with the Flash PADCs.

A conventional Successive Approximation Register (SAR) ADC [45] implements a binary search in B time-sequential steps (rather than a parallel search in 2^B steps, as in the flash PADC), zooming in by a factor-of-two onto the signal-under-test in each step. Upon porting such SAR scheme into the optical domain, we conceive a major variation on conventional SAR, actually making our scheme a hybrid between the classical SAR and pipeline ADC structures. In a conventional SAR the successive operations are sequentially performed in time, by feeding a single stage output back to the input, whereas in our SDSAR the comparisons and residuum generations will be seen to be sequentially distributed in space, using a feed-forward configuration spatially concatenating B quantization stages as a special case of an ADC pipeline unity gain between its stages. See Appendix B reviewing pipeline electronic ADCs [45] for the particular case of a pipeline with unity gain between its stages – which is what our SDSAR amounts to. In terms of photonic nomenclature, our novel SAR structure, albeit incorporating pipeline-like features, is designated Spatially Distributed SAR (SDSAR).

For the benefit of readers not familiar with either the SAR or the pipeline ADC electronic systems, we shall describe the SDSAR principle of operation independently of electronic ADC theory, in purely physical-optics terms, referring to the opto-electronic integrated SDSAR PADC structure proposed in Fig. 2 , which is amenable to integrated photonic realization.

 

Fig. 2 SDSAR PADC system. P-CMP are phase comparators (with internal structure detailed in Fig. 1), biased by quasi-static phase controls (little filled circles). Following an optical sampling front-end, consisting of an OCG feeding dual phase modulators driven by the voltage under test, cascaded interferometric ‘bit extractor’ measurement stages converge onto the phase-under-test by successively subtracting a binary sequence of phase values from the accumulated phases of the optically sampled pulses along the optical transmission line. The phase subtractions are effected by means of phase rotator modulators with lengths forming a geometric sequence with ratio ½ . The subtracted phase values, as generated by 1-bit DAC voltages, are determined by the phase measurements of the prior stage(s) (XORs of certain prior 1-bit ADC decisions). The 1-bit ADC outputs, c_n, are processed by simple combinational logic in order to generate the B ADC codeword bits b_n. Photonic and electronic matching delays are required to synchronize the successive stages in this feed-forward approach.

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However, prior to doing that, for the benefit of readers who are either versed in or interested in electronic ADC architectures we provide some context in this paragraph. Appendix B reviews the equivalent block diagram of a conventional pipeline ADC, albeit with unity gains between stages and using 1-bit ADC per stage, for all stages starting with the second one (i.e. obtained as a special case of the conventional pipeline ADC by setting the bits per stage and the inter-stage gain to unity, $B_n=1=G_n,n=2,3,\mathrm{...},s$). Such a pipeline structure with unity inter-stage gain is never used in electronics, however it does make sense in optics as we cannot directly implement the inter-stage gains in the phase domain, i.e. we may only have $G_i=1$. Moreover, the high-speed electronic requirements, along with the desire to avoid complex calibration, indicate that it is best to use a single bit, $B_n=1$, per pipeline stage (except for the first stage, which has $B_1=2$ bits). From another viewpoint, the resulting pipeline may also be considered as a spatially-sequential equivalent of the conventional time-sequential SAR structure. In each pipeline stage we perform a 1-bit ADC (i.e. decide whether the signal-under-test is in the upper or lower half of the sub-ADC full scale), and further evaluate the residuum after 1-bit ADC conversion, by subtracting the output of a one-bit DAC, driven by our stage decision, from the input to that stage. The resulting residuum is then presented as input to the next stage, and the procedure is recursively repeated. The residuum generated by each pipeline stage is not amplified to full scale, but is rather passed to the next pipeline stage as is. This corresponds to zooming in onto the signal-under test, first selecting one of four quarters, then successively halving the range, while determining in each stage whether we are on one-side or the other of an angular threshold, then setting the next angular threshold in the selected half-range, and so on.

SDSAR physical description: An optical comb generator (OCG) (typically a Mode Locked Laser (MLL)) provides a train of ultra-low-jitter high repetition rate sampling pulses, feeding a structure akin to the first half of a Mach-Zehnder Modulator (MZM), alternatively described as push-pull phase modulator, consisting of two phase modulators driven in anti-phase. The two waveguides emerging from the half-MZM form a dual optical bus, tapped at various points to feed two-port phase-comparator units terminated in 1-bit ADCs. The phase along the bus is further manipulated by in-line short phase-rotator modulators sections, driven by 1-bit DACs.

The SAR structure requires new optical elements, not present in the flash PADC [30]: B-2 phase modulators, referred to as phase-rotators, 1-bit DACs driving these modulators, inter-stage optical delays. These elements are grouped in stages, referred to as bit extractors, as each such stage extracts one extra bit, based on comparator decision bits, $c_n$, except for the initial stage which is referred to as QPSK P-CMP, as it is not a single bit extractor but rather a 2-bit flash ADC used to measure the quadrant the phase-under-test falls into, realized by means of two P-CMPs, reminiscent of Quadrature Phase Shift Keying (QPSK) detection. As depicted in the figure, each of the subsequent bit extractor stages comprises a short push-pull phase modulator, referred to as phase rotator, applying antipodal voltages onto a pair of electrodes along the optical bus consisting of a pair of waveguides fed from the two optical outputs of the front-end partial-MZM. Each phase rotator is differentially driven by a 1-bit DAC. The phase rotator is followed by a P-CMP sub-module (realized as a directional coupler, balanced detection, and 1-bit ADC), which is fed by tapping the upper and lower waveguides of the optical bus, prior to entering the next bit extractor stage in line. Each phase-rotator modulator is a factor of two shorter in length than the previous one. The 1-bit DAC voltages is a bi-polar electrical pulses of identical shape and peak voltage level, such that first phase-rotator modulator generates phase-shift $\pm \pi /4$ (i.e. its length is a quarter that of the main modulator for the voltage-under test) whereas the subsequent stages generate binary diminishing phase rotations $\pm \pi /8,\pm \pi /16,\pm \pi /32,\dots$. Each 1-bit DAC is driven by a XOR gate in turn fed by the comparator decision $c_{n-1}$ in the previous bit extractor and the quadrature bit decision of the QPSK P-CMP (bit $c_1$).

Principle of operation: The first stage along the bus following the half-MZM, labeled ‘QPSK 2-bit extractor’ is essentially a 2-bit flash PADC, consisting of two phase comparators biased in quadrature. Thus, the system initially determines the phase under test to an accuracy of π/2 (quadrant determination). Using the QPSK 2-bit extractor, generating two bits at once, is more efficient than a sequential two-step process first determining accuracy to π, then to π/2 (in the QPSK approach we reduce the required peak DAC voltage by a factor of two). This QPSK stage is followed by a refined assessment improving the accuracy to π/4 in the next ‘1-bit extractor’ stage which determines which one of the two octant halves of the quadrant the phase-under-test belongs to, then followed by an even more refined assessment improving the accuracy to π/8 in the following ‘1-bit extractor’ stage which determines one of the two halves of the previously determined octant that the phase-under-test actually falls into, and so forth. Starting from the quarter-circle, the SDSAR scheme is seen to perform a binary search, zooming in onto the unknown phase-under-test (visualized as a marker positioned somewhere on the unit circle) to an angular precision of $2\pi /2^B$. This is the first time to the best of our knowledge that such a binary search in the phase domain approach has been proposed for photonic ADC. We later show that this approach is more efficient and provides higher performance than the flash PADC approaches.

Describing the phase quantizing action in detail, the QPSK P-CMP determines the quadrant in which the phase under test resides, generating two bits encoding the measured quadrant (I, II, III or IV) according to the Grey code 10,11,01,00. A XOR logic operation on these two output bits then yields 1 for quadrants I, III and 0 for quadrants II, IV (e.g. for quadrant II represented by 11, we have $1\oplus 1=0$). The phase rotator modulator of the first bit extractor is driven by this XOR signal via the 1-bit DAC, applying the phase rotation (difference between the two phases applied on the two phase rotator modulator electrodes) equal to ${\theta }_{+}^{(1)}=+\pi /4$for quadrants I and III, or ${\theta }_{-}^{(1)}=-\pi /4$for quadrants II and IV (this requires that the two DAC outputs be $\pm V_{\pi }/8$). This phase rotation shows up as an extra additive (or rather subtractive) term added to (or rather subtracted from) the phase difference $\varphi$ between the two optical bus waveguides, generating the phase difference ${\varphi }^{(1)}=\varphi -{\theta }_{\pm }^{(1)}$ at the phase rotator output (note: the minus sign ahead of ${\theta }_{\pm }^{(1)}$ is due to the nominally positive polarity of the DAC differential drive being applied to the lower arm). Note that the angular threshold synthesized in the first bit extractor stage coincides with the bisector ray for the particular quadrant selected by the QPSK P-CMP, corresponding to “zooming-in by a factor-of-two” into the quadrant. The final P-CMP sub-module of the first bit extractor finally measures the sign of phase difference ${\varphi }^{(1)}=\varphi -{\theta }^{(1)}$ between the two waveguides at the first phase rotator output. The P-CMP determines ${\varphi }^{(1)}>0\iff \varphi >{\theta }^{(1)}$, or ${\varphi }^{(1)}<0\iff \varphi <{\theta }^{(1)}$. This effectively bisects the quadrant within which the phase-under-test falls in, and determines the octant (half quadrant) in which the phase-under test actually falls into. Hence, at this point we have zoomed in onto a particular octant sector (π /4 uncertainty), i.e. we have extracted our third bit (if we wished to realize a ${\log }_{2}8=3$ bits ADC, we would stop here). Moreover, the up-down differential phase on the optical bus, passed on to the next bit extractor now equals ${\varphi }^{(1)}=\varphi -{\theta }^{(1)}$, i.e. it amounts to the quantization residuum of the first bit extractor.

It is the next bit extractor stage’s role to slice the half-quadrant sector into two half-octant (π/8) sectors, and phase compare against the new bisector, determining in which of the two half-octants the phase-under-test actually resides. This is accomplished by the phase rotator of the next (second) bit-extractor adding or subtracting an angle of $\pi /8$ to/from the current $\pm \pi /4$ angle of the last angular threshold (as set in the former bit extractor stage), effectively bisecting the target octant, performing the P-CMP function and slicing the result (deciding on our fourth bit). In principle, this process continues with the fifth bit (π/16 uncertainty) and so forth to the desired accuracy, by serially propagating the light through bit-extractor stages, with their phase rotations directly driven by XORs of the 1-bit ADC decisions of the preceding stages and the quadrature bit of the QPSK stage. In a useful alternative equivalent description of the principle of operation, rather than positioning a sequence of bisector angular thresholds (diameters with orientation bisecting two antipodal angular sectors) as illustrated in Fig. 3 , we may rather visualize each antipodal pair of angular sectors being rotated (Fig. 3a), due to the phase rotator modulator action, to have its bisector diameter coincide with the angular origin ($\varphi =0$), as in Fig. 3b. Following the phase rotation, the P-CMP performs a comparison to zero, identifying either the upper or lower half-circle with horizontal diameter, which the phase-under-test falls in. As we know which of the two antipodal sectors we were in to begin with, then, within the next bit extractor, we take those two antipodal sectors and again rigidly rotate the two antipodal sectors, such that their bisector again becomes coincident with the $\varphi =0$ ray, and so forth. Now, the reason for using a XOR $c_1\oplus c_{n-1}$ to drive the n-th DAC is evident: Depending on whether the sector is in the half plane of quadrants I-IV or quadrants II-III, the applied rotations must be opposite in order to bisect the corresponding half of the sector where the phase-under test falls into.

 

Fig. 3 Phase-domain rotations occurring in the SDSAR PADC of Fig. 2, and supports of the phase probability density distributions at the QPSK 2-bit extractor input (a), and at the output of the phase rotator modulator in the first 1-bit extractor (b).

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1-bit DACs and phase-rotator modulators: The 1-bit DACs, driving the phase modulators of the successive bit-extractor stages are essentially precision bipolar pulse generators, each nominally producing a fast electrical pulse $\pm v_{DAC}(t)$(with support less than the sampling interval T), with polarity controlled by a single input bit, the Boolean value of which depends on the digital output of the previous stage (output of XOR operation on the QPSK P-CMP two output bits for the first bit extractor stage). By design, in each successive bit-extractor stage we affect a bipolar phase modulation which is half as large, relative to the previous one. Thus, we must use a phase modulator which is twice as insensitive (in its voltage to phase conversion), i.e., the electrode modulation length is halved, and the modulation switching voltage $V_{\pi }$is doubled, and relative to the phase modulator in the previous bit-extractor stage. It follows that the same voltage should be applied to achieve half the phase-shift, i.e. all monobit DACs are to be made nominally identical and the phase rotator modulators’ lengths should form a geometrically decreasing sequence with ratio $\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$. The pulse-shape of $v_{DAC}(t)$, its peak amplitude, and relative delay are adjusted (once) for each DAC to generate identical and well synchronized voltage pulses of the phase rotator modulator electrodes, such that the relative phase-shift imparted on each pair of optical pulses propagating in the two push-pull branches of the modulator, equals π /4 in the first bit extractor, and forms the geometrically diminishing sequence $\pm \pi /4,\pm \pi /8,\pm \pi /16,\mathrm{...}$, for the differential phase shifts induced in the successive bit extractor stages (small deviations of $V_{\pi }$away from a geometric sequence with ratio $\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$ may be compensated for by slightly tuning the various DAC voltages).

Notice that all the phases applied by the phase rotators are accumulated in the differential phase along the optical bus consisting of the two waveguides leading from the two phase modulators. Hence, so are the angular errors and fluctuations incurred in the successive settings of the angular thresholds in each of the bit-extractors, also accumulated, in the final effective angular threshold of each ADC level. Fortunately, the angular accuracy required in each bit extractor step is not absolute, but is relative to the size of the target sector at that stage (which means that the largest potential inaccuracy is experienced in the first stage, and as successive angular sectors are smaller by a factor of $\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.,$ so are their fluctuations scaled down exponentially as we proceed downstream. In particular, given the geometrically diminishing sequence of modulator switching voltages (with ratio $\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$), the fixed RMS noise and distortion of each DAC voltage noise is also mapped into RMS phase fluctuations forming a geometrically decreasing sequence, exponentially diminishing as we add more bits. The errors and noise contributed by each phase rotator, which are mutually independent between different phase rotators, then add up on an RMS basis, with the geometric series tending to a limit, to be quantified in the SNR analysis to follow in section 6 and Appendix C. Essentially, DAC noise fluctuations and inaccuracies, if any, are dominated by the first DAC stage, with just diminishing smaller corrections due to the subsequent stages.

Optical power allocation: The light propagating along the “optical bus” formed by the two output waveguides of the partial-MZM front-end, is tapped down to the B P-CMPs by means of directional couplers positioned along the optical bus, in each of the bit extractors. For optimal operation, the tapping ratios of these couplers should be adjusted to provide optimized light power to each of the P-CMP, while accounting for the optical losses. For now we shall assume that the taps ratios are adjusted to provide equal light power levels to all stages (at each of the P-CMPs inputs). However, notice that there is an optimal power allocation, favoring the stages further downstream, which is outside the scope of this paper.

Synchronization: In our feedforward SDSAR structure, it is essential to synchronize the optical and electronic paths. The optical sampling pulses (~2 psec) should arrive to each phase rotator modulator simultaneously with the electronic DAC pulses (~20 psec), at 10Gb/s, (100 psec repetition period). As the electronic DAC pulse is an order of magnitude wider than the optical pulse, the sync requirement is not very stringent – a 10% deviation in the arrival of the optical pulse of center of the electrical pulse should not pose a problem. The synchronization may be achieved by coordinated optical and electronic layout design, providing suitable optical delay between the bit extractor stages, and possibly fine-tuning of the electrical delays for precise optical-electronic delays matching. The bit decision from the 1-bit ADC of each bit extractor stage should be propagated to the next 1-bit DAC, an electrical pulse electrical pulse be generated and propagated onto the phase rotator modulator electrodes to arrive in sync with the optical pulse. An inspection of the physical (optical and electronic) and digital propagation delays indicates that such synchronization is feasible, especially on a Silicon PIC platform, which may compactly support low-loss optical delays of the order of several hundred psec.

A key requirement is maintaining an accurate match between the optical and electronic delays, from one bit extractor stage to the next. It is possible to nominally design the optical and electronic paths for nearly equal delays and just apply fine tuning of either the electronic or optical delays. Some degree of optical delay tunability may be readily achieved via the thermo-optic effect in Si PICs. Recent work on electronically tunable true optical delay [46] achieves tuning ranges as high as ~660 ps with a loss of <2.2 dB, though in our case we would need a just a small fraction of our ~100 ps delay to be tunable, implying that the tunable section loss would scale down. For our application, a concern with achieving delay using grating-based devices [46] and other complex optical structures based on coupled resonators and photonic crystals [47], is the potential distortion of the ultra-fast pulses. Thus, it appears that straightforward waveguide propagation is the preferred option for optical delay. Waveguides with compact cores with high confinement have been demonstrated in Si photonics, allowing dense packing of the delay lines in spiral waveguide structures with relatively sharp bends and low propagation losses. For bends larger than 3 um the bend losses become negligible. A key characteristic of an optical delay line is its propagation loss. A delay of 100 ps requires waveguiding along ~1 cm in SOI Si photonics. Earlier work [48] quoted propagation losses of 2.7 dB/cm. Recent advances in silica-over-silicon waveguiding [49] attained record low loss of 0.05 dB/m. This technology was applied to achieving 2 m delay for optical buffering application [50]. Accounting for all practical loss sources thermally tunable delay lines may be fabricated with overall losses of ~0.3 dB/cm. Vigorous research continues in the Si photonics field. It appears that the photonic integration technology is evolving towards making our SDSAR PADC application over the Si platform feasible overall, as all requisite photonic integrated elements are realizable. E.g., the combination of optical waveguiding delays and multiple slow phase-shifts, which is essential in our PADC device, essentially features in optical beam steering phased-array devices such as [51].

At this point it should be mentioned that an electrical master clock for all electronic circuits may be derived from the Mode-Locked-Laser OCG itself (i.e. synchronized to the “optical clock” used for electro-optic sampling) e.g. by tapping a fraction of the light onto a simple analog photo-receiver, and filtering the first harmonic of the photo-detected time-comb.

4. Resilience of phase-domain PADCs to opto-electronic impairments

Striving to attain ultra-fine resolution from any ultra-high-speed A/D conversion process, be it optical or electrical, one finds that a multitude of analog impairments tend to chip away at the system specs. Here we just briefly list the main degradation mechanisms, identifying among them some impairments to which our phase-comparators are inherently resilient to first-order due to their balanced photo-detection design. Notice that these impairments pertain to all PADC structures based on balanced phase-comparators, in particular the flash scheme [30] and the SDSAR of section 3.

Noise: The impact of detection noise - the shot noise and thermal noise sources -will be analyzed in section 6 and simulated in section 7. A beneficial feature of our flash PADC is its inherent resilience to intensity noise (optical pulse to pulse power fluctuations, which may be of the order of a fraction of a percent), due to the balanced photo-detection structure of the phase-comparators, which are phase sensitive but not amplitude sensitive – amplitude variations just stretch the photo-current waveform vertically but do not affect the zero-crossings, to first-order. A similar resilience was experimentally noted in the phase-encoded approach pursued in [2–5], which is also based on balanced photo-detection. Likewise, as the phase detectors essentially measure phase difference ${\varphi }_k-{\theta }^{(i)}$, the system is impervious to phase noise of the OCG optical source; more generally, any common-mode phase fluctuations affecting both interferometer arms, e.g. non-linear phase shifts in both arms will cancel out.

Attenuation variations: In particular, since the system encodes information in phase rather than in intensity, it is insensitive (to first order) to the precise coupling ratio of the integrated optic directional couplers and to the splitting ratios to the multiple comparators. The tolerances on the PIC fabrication are then much relaxed, overall, compared to conventional intensity modulation based PADC schemes.

PD nonlinearity: Since we use balanced photo-detection, i.e. subtract the photocurrents from two photo-detectors (PD), the nonlinearities of the balanced PDs will not matter to first-order (unless the two PDs are mismatched), as when either detector is illuminated with more light, it will generate monotonically more photocurrent (albeit in a NL way), thus the balance point between the two photo-currents will not be affected.

We must qualify these statements as applying to first-order. Imbalances in the various modules might reduce this inherent resilience to PD nonlinearity, intensity and phase noise.

Pulse overlap: The optical pulses traversing both paths are required to simultaneously arrive at the PDs, placing stringent requirements on symmetric layout of the interferometric paths leading to the two ports of each phase-detector. The pulse overlap problem appears more manageable in the guided-wave approach of [30], than in the polarization-interference approach used in the flash PADC design [29], wherein the two interfering paths are not separated, as in principle [30] allows independent control of the two spatially distinct paths.

PD ISI: In order to avoid linear interference between adjacent sampling intervals, namely Inter Symbol Interference (ISI) it is important to use photo-detectors which are a several times faster than the sampling rate. This may be alternatively described as the sample-to-sample memory problem being required to be less than the converter accuracy. To mitigate a photo-detection bandwidth substantially faster than the sampling rate is required.

It turns out that many of the remaining impairments, which are not automatically “self-healed” by the balanced design of the phase-comparators, might still be at least partially tuned out by proper calibration of bias or offset controls, such as analog offsets ${\text{OS}}^{(i)}$provided at each PHD output. Impairments of this sort might include imbalances and mismatches in the half-MZMs, optical splitters, directional couplers and balanced PD pairs, including extinction ratio and polarization dependent modulation and loss. Other impairments, such as frequency-dependent modulation efficiencies for the two polarizations may not be amenable to being calibrated away. Evidently, impairments control is a major issue and non-controllable residual impairments will ultimately limit the attainable performance for any PADC architecture. Beyond this cursory outline, a detailed study of impairments and their calibration is outside the scope of this paper.

5. Comparison between the SDSAR and prior photonic-quantized PADCs systems

In this section we compare our SDSAR with prior photonically quantizing PADC systems in the literature, in particular our flash phase-domain PADC [30] as well as other flash-equivalent schemes [25–29]. We do not consider here the aspects of all-optical parallelization (time/wavelength interleaving). In other words, even when all-optical parallelization is disclosed in any particular paper we refer to from the prior literature, we just focus on the operation of the lowest speed tributary PADC module. Moreover, comparison of the flash and SDSAR schemes with the Taylor-like schemes [15–24] is relegated to future work.

5.1 Comparison of phase-domain flash and SDSAR PADCs

The two phase-domain PADC implementations – flash and SDSAR - share some features and hardware requirements. Both are based on phase encoding onto optical short pulse samples, multiple interferometric measurements with balanced detectors followed by 1-bit logic, integrated-photonics platform for guiding, modulating, and interfering signals, and high-speed digital circuits. However, there are distinct tradeoffs between the two approaches; whereas the former exploits massive parallelism, the latter typically requires substantially fewer stages, albeit more complex ones, comprising phase rotators with DACs fed forward by the previous P-CMPs decisions, requiring tight synchronization, but at greatly reduced component counts.

The phase-domain flash PADCs (either our integrated optic scheme first introduced in [30] or the equivalent systems [25–30]) fully exploit optical parallelism - the A/D conversion can take place with no latency (within a sampling period). Albeit fast, this flash PADC design is hampered by the requirement of 2^B−1 phase measurements for b-bit A/D conversion, splitting out the light to 2^B−1 P-CMPs modules. A key advantage of the proposed SDSAR architecture over the flash PADC is the reduction in P-CMP (phase comparisons) counts, leading to simpler PICs and also to lower optical power requirements - both complexity and required optical power linearly scale with the number of bits B for the SDSAR as opposed to exponential scaling vs. B for the flash. This is particularly significant when a large resolution (number of bits) is sought. E.g., to attain a nominal 12 bit ADC by means of a flash PADC would theoretically require a factor of $2^{B-1}/B=2^{12-1}/12=171$ higher optical power at the OCG output, and higher photonic circuit complexity by roughly the same factor. Moreover, the SDSAR architecture is amenable to ADC pipelining, electrically cascading multiple SDSAR devices, such that increasing the ENOBs beyond 10 might be facilitated.

The SNR simulation presented in section 8 will establish that the flash PADC is limited to at most 6 ENOBs for practically achievable optical powers. In the electronics domain, flash ADCs are almost never used whenever more than 6 bits are needed; In the photonic A/D field, the most complex flash PADC we could practically envision would be a 5-bit flash PADC, requiring 16 P-CMPs and a 16-way optical split (built-in 12 dB optical loss), which might be practically realizable with state-of-the-art PIC technology. However, such system, potentially providing 4 ENOBs at 10 GS/s, would not be a significant contender to directly complete with electronic ADC – though indirectly 4 ENOBs might be useful if extended to ~100 GS/s by all-optical parallelism (time/wavelength interleaving) techniques [31–38]. Nevertheless, the flash PADC has been reviewed in detail here as a conceptual stepping stone towards our more efficient SAR-based PADC versions, introduced next.

6. Theoretical statistical modeling of the SDSAR photonic ADC

In this section and the next one, we take up the statistical modeling of the SDSAR PADC scheme, evaluating the ENOB vs. optical power operating characteristics, analytically in this section and numerically in the next section, providing theoretical and numerical insight into and quantification of the main limiting mechanisms of system performance.

The impairment sources included in our theoretical modeling and the numeric simulations are the quantization, shot and thermal noise sources, and the DAC voltage noise for the SDSAR. Excluded from the analytic analysis and numeric simulation are the following effects: (i): Frequency-dependent impairments, e.g. modulator frequency-response. (ii): the impact of the aperture jitter, which is assumed negligible (<2 fs) with commercially available modern Mode-Locked-Lasers. (iii): The front-end RF amplifier noise figure (its impact may be of the order of a fraction of an ENOB – notice that such an impairment would be common to all PADC schemes). (iv): The differential/integral ADC non-linearity – we assume our PADCs to be perfectly linear (which would require perfect placements of the reference levels, under the AC&C procedure, and that higher-order impairments be negligible – however, notice that if the ADC levels were uneven, the ENOB would also be degraded, as noise excursions taking the phase-under test across a transition-level boundary would be more likely). (iv): Inter-Symbol-Interference, i.e., the sample-to-sample memory of the photo-diodes. (v): Higher-order impairments related to the device imbalances, signal fluctuations, and optical non-linearities of the PIC and the photo-detection process.

Thus, our ENOB vs. optical power characteristics, analytically and numerically derived in this section and the next one, are idealized to exclude the higher-order impairments above, thus essentially provide upper bounds on performance, which are not necessarily tight. Nevertheless, it is still useful to know that our SDSAR system will never exceed these bounds.

It is apparent that it is the 1-bit ADC and 1-bit DAC building blocks, which will ultimately determine the overall performance along with the photonic layouts of the two PADC architectures used here to combine these building blocks, namely the flash and SDSAR architectures. Thus we first develop an analytical signal and noise model for the 1-bit ADC (the P-CMP) and the 1-bit DAC, then proceed to analyze the compound SDSAR system based on our models for the elementary 1-bit building blocks.

6.1 Noise analysis for the phase comparator

In the electronic back-end of the PHD, the two photo-currents in Eq. (3) are subtracted in the balanced receiver, and the currents difference is integrated in the I&D device. For each optical sampling pulse, the generated I&D sample is accompanied by a noise fluctuation, generated as the difference of the shot-noises in the two photodiodes, filtered through the I&D matched filter. Equivalently we can analyze a system in which the I&D is doubled up and placed on both photodiode arms, prior to subtraction, i.e. passing the two photo-currents through two I&D modules prior to subtracting.

Shot noise: The shot-noise variance accompanying the decision variable $K_d$is readily derived. The result is that for any phase settings, $\varphi ,\theta$, the shot-noise induced mean-squared-fluctuations in $K_d$ are constant and equal to the mean received photo-electron count $〈K_r〉$associated with the aggregate light power at the two DC inputs. Indeed, the two effective integrated outputs, $K_{\Sigma /\Delta }$, associated with each PD separately, $K_{\Sigma /\Delta }$, are complementary $K_r=K_{\Sigma }+K_{\Delta }$, summing up to the fixed total power at both DC inputs, and each of $K_{\Sigma },K_{\Delta }$ are independent and Poisson distributed, with respective variances equal to the means:

Taking the square root, we obtain the RMS shot noise contribution:

Thermal-noise: The RMS thermal noise is characterized by $i_{NEC}$ (typically in $pA/\sqrt{Hz}$ units). The thermal noise two-sided spectral density is then given by $S_{i_{TH}}=\frac{1}{2}{i}_{NEC}^2[Am{p}^2/Hz]$. Now, the I&D effective filter, with impulse response $h_{I\&D}(t)=1_{[0,{\tau }_I]}(t)$, has squared norm ${\Vert h_{I\&D}\Vert }^2={\tau }_I$, therefore the RMS charge fluctuations as integrated at the output of the I&D are expressed as:

It follows that the photo-electron count RMS thermal fluctuations are given by

Shot + Thermal noise: The overall detected sample is then expressed as

Quantization-noise: The quantization noise RMS-SNR (square root of the power SNR) in the phase domain is given by

The numerator in the last equation is the RMS value of a reference sinusoidal signal ${\mu }_p\pi \sin {\omega }_{m}t$ in the phase domain, with peak modulation index ${\mu }_p$ such that$1\cong {\mu }_p<1$, slightly backed-off from the full scale in order to avoid end-of-scale effects (in our simulations we shall take ${\mu }_p=0.985$, i.e. the phase range is $\pm 0.985\pi$), while the denominator in Eq. (15) is the RMS quantization noise (QN), i.e. the square root of the QN variance, $Var({\varphi }_{QN})={\Delta }_{\varphi }^2/12$, in the angular domain,

6.2 DAC Voltage Noise

In addition to the Quantization, Shot and Thermal noises associated with the phase comparators, as derived above, there is a new noise source be further considered in the SDSAR analysis (which does not arise in the flash PADC), namely DAC voltage noise.

The additive white Gaussian thermal noise of the DAC circuit induces phase fluctuations in the phase-rotation modulation process, which are then electrically detected by the phase detector prior to 1-bit decision in the P-CMP. Detailed modeling of this noise source has been conducted, analyzing the mechanisms whereby the DAC voltage noise induces phase noise in the first phase-rotator modulator, which in turn generates photo-count fluctuations in the I&D output sample, the RMS value of which given by:

Notice that Eq. (18) describes just the DAC voltage noise contribution of the first phase rotator. For each subsequent bit, the corresponding phase rotator modulator has half the length relative to the length of the previous stage, such that its $V_{\pi }$ is doubled, i.e. $V_{\pi }^{(n)}=2^{n-1}{V}_{\pi }^{(1)}$. Thus the RMS voltage noise induced fluctuation due to the n-th DAC is a factor$2^{n-1}$ smaller than that due to the first DAC. The Voltage-Noise (VN) variance is then reduced by a factor of four from one bit extractor to the next one. As the overall angular threshold for each ADC level is the sum of all interim angular thresholds set in the successive phase rotators (the threshold errors get accumulated) and as the voltage noises of the various DACs are independent, it follows that the final stage VN variance is the sum of the variances of each stage, each reduced by a factor of 4 relative to the previous one. Therefore, the overall VN variance is enhanced by the following factor relative to the variance contributed by the first bit extractor:

Actually the convergence to 4/3 is quite rapid, with$s[4]=1.313;s[6]=1.332$ . Our final formula for the contribution of all DACs to the detected photo-count is then given by:

This formula differs from Eq. (18), which pertains to just the first DAC, by a factor of $\frac{2}{3}/\frac{1}{2}=\frac{4}{3}$ times a correction $1-4^{-(B-1)}$ (which in turn is very close to unity for B>4 bits).

6.3 Phase-domain equivalent noise for the SDSAR

Let us collect the expressions of Eq. (11), Eq. (13), Eq. (17)and Eq. (18) derived so far for the RMS values of the four noise sources in the photo-count domain:

Notice that the last expression pertains just to the contribution of the first phase-rotator DAC.

According to Eq. (9), the photo-count and angular domains are linearly related. Hence, we shall map the photo-count noise sources in Eq. (21) back to the angular domain. For the purpose of first-order angular noise representation, we substitute $〈K_r〉$instead of $K_r$ in Eq. (9), writing

The simple relation in Eq. (22) may be used to map noise and distortion in the detection variable $K_d$ into equivalent phase-domain (angular) representations, providing a more intuitive sense of the various noise mechanisms. Each of the RMS noise-terms listed in (21) are equivalently expressed in radians, as follows:

These quantities are the RMS values of four equivalent noise sources, ${\varphi }_{QN}^{}[k],{\varphi }_{SH}^{}[k],{\varphi }_{TH}^{}[k],{\varphi }_{DAC(1)}^{}[k]$, representing all relevant opto-electronic noise sources, all mapped to the sampled phase domain. The additional noise contributions the DACs driving the phase rotator modulators in the subsequent bit extractor stages) are written in the form ${\varphi }_{DAC(i)}^{}[k]/2^{i-1}$, for i = 1,2,...,B-2, where all the noise signals ${\varphi }_{DAC(i)}^{}[k]$ have identical statistics, and the powers-of-two attenuation factors stem from the geometric sequence (with ratio 2) of the $V_{\pi }^{(n)}$ values for the phase rotator modulators, corresponding to the geometric sequence (with ratio ½) of modulator lengths.

As per Appendix B, the equivalent canonical block diagram of an SDSAR is viewed as a pipelining cascade of stages with unity gains applied to the residuums. The basic stage in a generic pipeline ADC consists of a sub-ADC acting on the input signal followed by a DAC, the output of which is subtracted from the input signal to generate the residuum, which is passed to the next stage of the pipeline. Each stage output is amplified by an inter-stage amplifier, however, in the SDSAR, this amplifier has unity gain, i.e., it is effectively missing. Adapting the generic notation of the canonical block diagram shown in Appendix B, the sub-ADCs are simply described as adders, additively imparting to their input signals internal A/D errors

The theoretical basis for simply representing an ADC as an error-adder is reviewed in Appendix A. So are the DACs described as error-adders, additively imparting to their input signals internal D/A errors given by $2^{i-1}{\varphi }_{DAC(i)}^{}[k]$. Notice that unlike in a conventional pipeline ADC, in the current SDSAR the full-scale FS ranges of the various sub-ADCs are not constant but rather form a geometric sequence with ratio ½. Thus, there is no need to scale the various digital ADC outputs prior to adding them up in order to form the overall binary number representation of the signal-under-test. Hence, all digital gains applied to the sub-ADC decisions are unity. This is also consistent with the inter-stage analog gains being unity.

In the very last stage of a standalone SDSAR, we may discard the last stage DAC (and its associated phase rotator modulator).

Following simple linear block diagram rules, we readily propagate the various sub-ADC and DAC additive error sources, one at a time, all the way to the SDSAR output, ${\varphi }_d^{}[k]$:

(i) The sub-ADC errors ${\varphi }_{ADC(i)}^{}[k]$of the interim stages, i = 1,2,B-2, do not show up at all in the overall device output (each one of them propagates with unity gain positive sign down to the digital adder, but with unity gain and negative sign via the digital adder of the next stage, canceling out overall).

(ii) The only sub-ADC error which does propagate to the output, (as is, with unity gain, given the inter-stage unity digital gains), is one from the very last (B-1-th) stage:

Thus, the only sub-ADC contribution to overall PADC performance is provided by the overall A/D noise of Eq. (25) of the last stage P-CMP. This somewhat surprising conclusion is well-known in pipeline ADC theory [45], and is also consistent with the subsequent numeric Monte-Carlo simulation which makes no assumption but just propagates the signal through the structure.

(iii) We must also add in, to the ADC output, the contribution of the B-2 DACs, all of which propagate to the output with unity gains, but are weighted, to begin with, by coefficients forming a geometric sequence with ratio ½:

Thus, the overall SDSAR PADC I/O transformation is expressed as:

As the DAC noise sequences ${\varphi }_{DAC(m)}^{}[k]$ are all stationary, independent and identically distributed, the DAC variance contributed by the n-th stage is (using Eq. (18)):

Thus, the accumulated DAC noise from all the stages has RMS fluctuations:

The power of the overall SDSAR angular error fluctuation is given by

The quantization-referred noise figure (which will enable us to determine the ENOBs) is then the ratio of the overall SDSAR noise power and the ideal quantization noise power (further scaled up by the inverse peak back-off factor ${\mu }_p^{-2}$ (Eq. (51) of Appendix A):

We shall see that the DAC noise (the last term in the sum) contributes to a small degradation relative to the other (shot + thermal) two terms. The received optical power at each phase comparator (sum of powers at the two directional coupler inputs) determines the equivalent photo-count per optical pulse, and is obtained by B-fold dividing the optical power associated with the OCG optical source (assuming for now equal power division among all B bit extractor stages), also accounting for the excess loss, $L_{exs}$ and for the $f_s$ pulses per sec:

Notice that in the flash PADC the power division was by a factor$2^{B-1}$, rather than by a factor B as here, hence the SDSAR is $2^{B-1}/B$times more power efficient than the flash. The SDSAR effective number of bits is then expressed in terms of Eq. (32) by Eq. (54) of Appendix A, $B_{\text{eff}}^{SDSAR}=B-\frac{1}{2}{\log }_2\left(F_{\text{SDSAR}}^{/QN}\right)$. Combining this expression with Eq. (32) and Eq. (33) provides our final analytic expression for the ENOB vs. optical power characteristic of the SDSAR, parameterized by the sought number of bits:

This tortuously derived analytical expression will be validated by numerical simulation in section 8 – the match will be seen to be very close, except at very high bit counts.

7. Numerical Monte-Carlo model for the SDSAR PADC

We developed a comprehensive SDSAR numerical model, as detailed in the block diagram of Fig. 4 , closely following the physical structure of Fig. 2. The input into the SDSAR model is the voltage-under-test, $V_{IN}$ and the output is a quantized or discretized value denoted ${\widehat{V}}_{IN}$ (quantized estimate of $V_{IN}$). Both these voltage values are mapped into the phase domain as ${\varphi }_{IN}=V_{IN}\cdot \pi /V_{\pi }$ and ${\widehat{\varphi }}_{IN}={\widehat{V}}_{IN}\cdot \pi /V_{\pi }$.

 

Fig. 4 (a): Block diagram of the Monte-Carlo simulation for the SDSAR PADC. (b,c): Detailed block diagrams of the two module types composing the SDSAR (a), with physical gain factors and additive gaussian noise sources.

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We randomly drew $T=5\cdot {10}^6$ independent input voltage sample trials, from either a uniform or a sinusoidal distribution with angular range $[-{\mu }_p\pi ,{\mu }_p\pi ]$, with ${\mu }_p<1$ to prevent end-effects, but close to unity; (the difference between the performances of the sinusoidal and uniform distributions is minute, as will be seen further below).

The input voltage is mapped into the phase-under-test, ${\varphi }_{IN}$, which is propagated through the system, advancing from one bit extractor to the next, starting with the 2-bit QPSK extractor, repeatedly emulating the photo-detection and 1-bit quantization, in the phase-comparators, generating bit decisions $c_n\in \{0,1\}$. For each of the comparator bit decisions, excluding the first two comparators of the QPSK stage, the comparator decisions $c_n,n=2,\mathrm{...},B-1$ are XOR-ed with the quadrature comparator decision $c_1$ to generate the bit-extractor decisions, $b_n$, as well as 1-bit DAC control bits, $d_n$, subtracting rotation phase, ${\rho }_n$, emulating the phase rotator modulators, as detailed below:

The first two QPSK decision bits, $b_0,b_1$, initialize the processing .The totality of 1-bit decisions (including the 2-bit decision of the first QPSK stage) is assembled into an output discrete-valued representation ${\widehat{\varphi }}_{IN}$ of the input phase-under-test:

It remains to define the ${\varphi }_{IN}\to {\widehat{\varphi }}_{IN}$ random “channel”, reflecting the operation of SDSAR structure of Fig. 2, performing Monte-Carlo random drawings of the various noise source samples from zero-mean Gaussian distributions, with variances as specified in section 6. The quantization noise is evidently not to be added in as a separate noise term here, but will rather naturally and emerge in the sign quantizations. The 1-bit quantization in each P-CMP is corrupted by the Shot + Thermal noise terms, added to the detected photo-count at each comparator, which may occasionally induce erroneous decisions, increasing the mean-squared error. We use the accurate representation of the phase comparison process (without making any small argument approximations for the size of sine non-linearity) recursively modeling the phases and 1-bit decisions propagation as follows:

In the absence of shot and thermal noise, or more generally if the excess noises are present but do not cause an error, the two QPSK stage output bits would be given by the following expressions, such that $c_0^{}{c}_1^{}$determines the quadrant according to the 10,11,01,00 Gray code:

Detailing Eq. (38) for n = 2, the XOR $c_0^{}\oplus c_1^{}$of the two QPSK comparators decisions drives the phase rotation ${\rho }_2={\left[c_0^{}\oplus c_1^{}\right]}^{\pm }\pi /2^2=\pm \pi /4$ according to whether $c_0^{}{c}_1^{}=10or01$ (quadrants I,III, $c_0^{}\oplus c_1^{}=1$) or $c_0^{}{c}_1^{}=11or00$ (quadrants II,IV, $c_0^{}\oplus c_1^{}=0$). For $n\ge 3$, the XOR $c_{n-1}^{}\oplus c_1^{}$of the previous and the first comparator decisions drives the phase rotation ${\rho }_n={\left[c_{n-1}^{}\oplus c_1^{}\right]}^{\pm }\pi /2^n\in \left\{\pm \pi /2^n\right\}$: If $c_1^{}=0$, i.e. if the phase-under-test falls in the half-plane defined by quadrants II,III, then ${\rho }_n={\left[c_{n-1}^{}\right]}^{\pm }\pi /2^n$ . If $c_1^{}=1$, i.e. if the phase-under-test falls in the other half-plane (quadrants I,IV), then ${\rho }_n={\left[c_{n-1}^{}\oplus 1\right]}^{\pm }\pi /2^n=-{\left[c_{n-1}^{}\right]}^{\pm }\pi /2^n$, i.e., in this case the rotation is opposite that performed for the half-plane of quadrants II,III.

Figure 3 already illustrated the PDF of the initial phase ${\varphi }_{IN}$ as it enters the first QPSK stage (Fig. 3(a)), as well as the phase ${\varphi }_{IN}-{\rho }_2$ as it enters the P-CMP of the second stage 1-bit extractor (Fig. 3(b)), after having undergone rotation by $-{\rho }_2$ in the phase-rotator modulator of this stage, driven by $c_0^{}\oplus c_1^{}$. If the two P-CMPs of the first stage indicate that $\varphi \in (0,\pi /2)${blue} or $\varphi \in (-\pi ,\pi /2)${cyan} then we rotate ${\varphi }_{IN}$ CW by $\pi /4$, and if $\varphi \in (\pi /2,\pi )$ {red} or $\varphi \in (-\pi /2,0)$ {magenta} then we rotate ${\varphi }_{IN}$ CCW by $\pi /4$. When no errors are committed in the first stage, the input phase ${\varphi }_{IN}-{\rho }_2$ to the P-CMP of the second stage is a random variable with range $(-\pi /4,\pi /4)\cup (3\pi /4,5\pi /4)$. This process similarly continues in the following bit extractor stages, with the P-CMP phase input becoming a successively slimmer two-antipodal-sector shape, bisected by the horizontal axis, similar to the one shown in Fig. 3b. Slicing errors will cause the two antipodal sectors to be rotated by $\pm \pi /2^n$ away from their nominal positions. An analytical analysis of decision errors propagation has been worked out and found to be quite favorable, however, in this paper we are content with empirically measuring the resulting overall numerical performance, which implicitly includes the statistical impact of decision errors and their propagation.