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A new type of CMOS compatible photodetector, exhibiting intrinsic light-to-time conversion, is proposed. Its main objective is to start the time-to-digital conversion directly at its output, thereby avoiding the cumbersome analog processing. The operation starts with an internal charge integration, followed by a positive feedback, and a sharp switching-current. The device, consisting of a deeply depleted MOS structure controlling the conduction of a forward-based PN diode, is presented and its operation explained. TCAD simulations are used to show the effects of semiconductor parameters and bias conditions. The photodetector and its detection circuit are designed and fabricated in a 0.18µm CMOS process. Measurements of this new device under different biasing and illumination conditions show highly promising properties in terms of linearity, internal gain, and noise performances.
© 2014 Optical Society of America
1. Introduction
Photodiode-based optical technologies have experienced a tremendous growth over the past decade. This trend has been particularly strong for 2-D and 3-D image sensors with applications to areas as diverse as medical imaging, security vision, real-time polarization imaging, industrial machine vision, virtual reality, etc.
Historically, photodetector design has been dominated by high speed and compound semiconductors [1–3]. Nevertheless, CMOS technology played major role in this evolution, principally by enabling low-power, low-cost and fully-integrated imaging products [4–8]. In fact, the high volume of data handled by image processing systems makes them too complex for an implementation with discrete components. This is especially true for the imagers that use a large array of sensors and where each individual pixel is followed by bulky circuits for signal processing [9,10]. Miniaturization and circuit simplification techniques are therefore of prime importance for such large matrix topologies. Beyond size and cost optimization, monolithic CMOS-integration of imager systems eliminates the problems of losses, mismatches, and parasitic elements that characterize the multi-package implementations.
However, voltage supply diminution and size shrinking in advanced CMOS technologies bring a new set of challenges for the design of the photodiode and its associated circuits [7,8]. Particularly, the limited voltage headroom at the output of the photodiode pushes toward a time domain representation of the signal. This explains the growing success of pulse modulation imaging (PM) [6,11]. A Typical PM sensory processing element (SPE) is shown in Fig. 1. The voltage resulting from the integration of the photocurrent is converted to pulses information by the comparator and converted using a time to digital converter (TDC) [6,11,12]. Operational transconductance amplifiers (OTA) are the best and the most widely used circuits for the implementation of these comparators [13,14], principally because they enable a better control of the mismatch thereby minimizing the associated fixed pattern noise (FPN). This noise improvement comes, however, at the cost of significant power consumption, due to the static currents of the OTAs especially as large matrixes of SPEs are required to build the imaging system. The comparator, even for simple applications, occupies a non-negligible silicon area of the pixel (at least 20%) [9]. In the case of low-light application, such as fluorescence or bioluminescence, the analog processing is even more complex, requiring higher amplification, and sophisticated noise cancelation technics [15,16]. These problems are exacerbated in deep-submicron (DSM) CMOS processes, where the shallow junctions, high doping concentrations, and the limited voltage headroom available for the reverse biasing of the diode result generally in very small depletion regions and thus, low photo-sensitivity. The weak performance of the photodiode must then be compensated by sophisticated analog circuits, which makes their design very difficult and power hungry [6,7].
The principal motivation of this work is to design a photodetector for PM imaging that allows for elimination of the analog processing, as illustrated in Fig. 1. This will pave the way to a fully digital CMOS image sensor that would be cheaper, more compact, power-efficient, and less sensitive to noise. The proposed photodetector exhibits device-level light-to-time conversion. It consists of a deeply depleted MOS structure controlling the conduction of a forward-based PN diode. Under illumination, this light sensor integrates the photo-generated charges up to a certain level before turning into its conductive state. The positive feedback process between the MOS and PN parts of the device guarantees a fast switching with a large current.
Section 2 presents the structure and operation of the proposed device. The concept is experimentally demonstrated in section 3, and the final conclusions are made in Section 4.
2. Hybrid MOS-PN photodiode diode principle and operation
2.1 Structure of the device
The structure of the proposed photodetector, shown in Fig. 2, consists of a combined MOS and PN diode structure on a p-type substrate. As for the standard diode, we call the p + and n + diffusions, anode and cathode, respectively. The dynamic operation of the device relies on a conjunction of the transient phenomena that occur in the MOS and PN junction as will be illustrated by TCAD “Sentaurus-Synopsis” simulations. For these simulations, and without loss of generality, we consider a distance of 7µm between anode and cathode, a gate length of 2µm, a depth of n + and p + diffusions of 0.2 µm, and an oxide thickness of 4nm.
2.2 Operating principle
The dynamic behavior of the device is summarized in Fig. 3. These transient simulations are obtained after switching at the same time Vp from 0V to 0.8V and Vg from 0V to.2V while keeping the cathode grounded. As illustrated, the device does not react immediately to bias switching. However, when conduction is triggered, the anode current increases sharply by several orders of magnitude. We call the delay of reaction Self-triggering time. This time increases when the substrate doping concentration (NA) decreases, as shown in Fig. 3.
Fig. 3 Anode current versus time after switching Vp and Vg from 0 V to 0.8 V and 1.2 V respectively. The transient simulation is repeated for different substrate doping.
In order to explain the origin of this dynamic behavior, the charges and current densities are visualized at the three stages highlighted in Fig. 3, i.e. (a) immediately after bias switching, (b) when conduction starts and finally, (c) when the current reaches its maximum. The results are depicted in Fig. 4 for space charge and Fig. 5 for current densities. Figure 4(a) shows the space charge regions in the structure just after the voltage step (i.e. at point (a) of Fig. 3). As we see, majority carriers (holes) drift away from the gate under the action of the positive gate voltage. Therefore, the MOS part of the device enters deep depletion; the space charge region engulfs the p + diffusion practically isolating it. Therefore, even if a positive voltage Vp is applied on the anode, the cathode-to-substrate junction remains depleted, and the corresponding potential barrier continues to block the electrons. Since the anode is practically isolated, only a negligible hole current flows between the two electrodes in this first stage, as illustrated in Fig. 5(a).
Fig. 4 Space charge (Qs) at the different times highlighted in Fig. 2 (i.e. (a) 10ns, (b), 30ns, (c) 100ns).
Fig. 5 Electron (left) and hole (right) current densities at the times highlighted in Fig. 4 (i.e. (a) 10ns, (b) 30ns, (c) 100ns)
After a certain time, the accumulation of holes in the p region next to the n + diffusion lowers the potential barrier, and the cathode starts to emit electrons that drift under the gate [Fig. 5(b)]. These electrons create an inversion layer that shields the electric field coming from the gate, thereby decreasing the MOS depletion region and gradually de-isolating the anode [Fig. 4(b)]. This in turn increases the hole current and further lowers the cathode barrier. In this way, the positive feedback is triggered, thus turning the device into its conductive state with a high current between the anode and the cathode, as shown in graphs (c) of Fig. 5.
Note that the voltages needed to trigger the device are quite low (around 1V), which is particularly suitable for modern CMOS technology.
As previously stated, a strong dependence on substrate doping levels is observed [Fig. 3]. In general, the lower is the doping of the substrate; the longer is the triggering time. The reason for this is twofold. First, the weakly-doped substrates result in a deeper MOS depletion and thus, a better anode shielding. Second, a lower doping increases the potential barrier at the PN junction, near the cathode. Hence, the injection of electrons from the cathode is more efficiently blocked.
A similar behavior is obtained if we increase the gate voltage or the distance between anode and cathode. Figure 6 shows the anode current after switching Vg from 0 to 1V (black line, on the left and from 0V to 2V (blue line on the right). In both cases, Vp is switched from 0 to 0.8 V while keeping the cathode grounded. As illustrated, the self-triggering time increases from 0.1 µs to 0.5 µs. Here also, the reason is the deeper MOS depletion region and the better anode shielding when Vg switches to 2V, as illustrated by the simulated space charge extensions, depicted in Fig. 7.
Fig. 6 Anode current versus time after switching Vp from 0 to 0.8 V and Vg from 0 to 1 or 2 V respectively. The transient simulation is repeated for different light intensities.
2.3 Effect of light
Figure 5 shows the effect of light on the device triggering time. The simulations are carried out using Transfer Matrix Method (TMT) implemented in the optical solver of Sentaurus. As illustrated in Fig. 7, the photo-generated electron-hole pairs in the depletion region are separated by the electric field. The electrons quickly drift under the gate, while the holes are ejected from the depletion region and participate to the hole-current towards the cathode. The electron-hole pairs generated near the cathode also participate in the currents in the same way. The conjunction of these two phenomena results in the acceleration of the triggering shown in Fig. 6.
Note that for graphical clarity, the minimum time shift of the digital current shown in this example is 20 ns. It corresponds to an illumination of 1 mW/cm2. Modern time-to-digital converters (TDC) can go well beyond this time resolution (e.g. 1.2 ps with a 0.18 m CMOS in [17]), so a much smaller light intensity can be processed. For instance, if a TDC with a resolution of 10 ps is used, an intensity of light as small as 0.5 µW/cm2 could be theoretically detected. The principal limitation is the noise of readout circuits, which is expected to be very small in the case of fully-digital implementations. The first measurements show a relative noise in the order of 1‰ (see section 3).
3. Proof of concept
In order to validate experimentally the concept, the photodetector with its driver and readout circuits were designed and fabricated in 0.18µm CMOS process. The complete ASIC contains several devices with different geometries, each connected to its detection circuit. The complete detection system consists of a STM32F4 microcontroller unit (MCU) connected via USB to a computer. Figure 8 shows a photograph of the fabricated ASIC and a simplified schematic of one of its photodetectors.
Logic inverters are used for the drivers and readout circuits. The driver switches the anode and the gate of the photodetector from ground to a positive voltage Vforward (0.9 V in this setup), putting the device in photo-sense mode. In order to achieve such a low-voltage operation and without loss of generality, a long device with a distance between the anode and the cathode of 100 μm was chosen. When the device is illuminated, the triggering current discharges the input capacitance of the read-out inverter and changes its logical state (from 0 to 1). The output of the detection circuit is fed to the MCU which can use its high frequency clock and internal counters to measure the triggering time and communicate it to the computer. The light source is a Thorlabs S1FC635 fiber coupled laser with a wavelength of 635nm.
The light sensitivity of the device is illustrated by the measurements of Fig. 9 where a significant acceleration of the triggering under light is observed. The experiment is repeated for different light intensities, and results are reported on Fig. 10.
Fig. 9 Light-modulated pulse width measurements. Ch.1: Clock signal from MCU, Ch.2: ASIC Output signal.
The results reveal that the inverse of triggering time (1/T) is proportional to light intensity (Ilight). Therefore, we can define the relation between 1/T and Ilight in Eq. (1).
with α a constant with units [cm2/J] and T0 the self-triggering time in darkness.As expected, this relation confirms that a fixed amount of carriers N must be generated in order to de-isolate the anode and turn on the device. The time needed to reach this amount of charge depends on the intensity and the wavelength of the light. Indeed, Eq. (2) shows that for the same intensity, the smaller the wavelength (λ) is, the smaller the number of photons per second and unit area (n) is.
The time needed also depends on the photoactive area of the sensor (A) and on the quantum efficiency (QE) of the process (expected to be between 30% and 40%). The relation for the determination of N can thus be written as Eq. (3).
Figure 11 shows the measured normalized jitter of the triggering signal (σT/T) versus light intensity. As illustrated, this ratio depends weakly on light intensity.
This is the typical characteristic of the shot noise (or Poisson Noise), where the expected value of the distribution is equal to its variance. This measurement shows that the system is shot noise dominated even in low-light conditions. The implemented digital circuits can be considered as practically noiseless for the system. In fact, the anode-gate voltage is the principal noise source in this circuit, and this noise is easily filtered out by decoupling capacitors, which are external in this first prototype. This experiment gives an insight into the benefits of the switching behavior of the photodetector and the elimination of the noisy analog processing.
4. Conclusion
A new type of photodetector fully compatible with CMOS technology has been presented. The positive feedback, triggered by a combined dynamic action of the MOS and PN diode parts of the device, has been explained and illustrated using TCAD simulations. A first prototype has been fabricated and tested, and shown to validate the proposed concept. The measurements show an intrinsic light-to-time conversion with a high internal gain, linear input-output characteristic, and low noise operation. The dynamic behavior of this photodetector under low-voltage paves the way for a new generation of fully-digital image sensors that will be more compact, power-efficient, and less sensitive to noise. It was demonstrated the device performances are strongly correlated with the basing conditions and the physical implementation. As for classical photodetector, process parameters such as triple well, layout, geometry or the use of special technology like SOI, Ge and compound semiconductors are expected to have significant impact on the performances of this new device and thus open interesting investigation topics. At system-level, the integration of this photodetector in a real-world imager is also an exciting and challenging research subject. Principally, the study of the spatial and time multiplexing, the size, the distribution of the pixel arrays, and their impact on performance is of prime interest.
Acknowledgments
This Research is supported by the Swiss National Science Foundation. (Founding No: 200021_140447).
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