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Digital chemical etching is used to trim the output mirror thickness of wafer-fused VCSELs emitting at a wavelength near 1.5µm. The fine control of the photon cavity lifetime thus achieved is employed to extract important device parameters and optimize the combination of the threshold current, output power, and direct current modulation characteristics. The fabrication process is compatible with industrial production and should help in improving device yield and in reducing manufacturing costs.
© 2014 Optical Society of America
1. Introduction
The great advantages of vertical cavity surface emitting lasers (VCSELs) over edge-emitting diode lasers stem from their vertical cavity design. This design leads to better emission wavelength selectivity, circular beam shapes, lower power consumption and reduced manufacturing costs [1]. At the same time, the short cavity and reduced round-trip optical gain also require more precise design of the VCSEL structure and better control on the epitaxial growth and device processing involved. Progress in VCSEL technologies has indeed allowed the establishment of growth and processing techniques suitable for the commercial manufacturing of both short wavelength [2] and longer wavelength VCSELs [2, 3] with adequate performance and yield. However, the increasing challenges in producing VCSELs with precise wavelength settings, lower power consumption, and higher modulation bandwidths, especially for optical fiber communication applications, require the introduction of new techniques for the further improvement of device manufacturability. A useful approach could involve the fine-tuning of selective device parameters after processing is completed. A particular post-processing technique of interest is the adjustment of the reflectivity of the output-coupling distributed Bragg reflector (DBR), so that the VCSEL’s photon cavity lifetime is chosen to enhance the output power and the modulation bandwidth of the device. This approach has been demonstrated with short-wavelength VCSELs emitting at 850 nm [4], where the top-DBR was etched using a standard reactive ion etching process.
Here, we report the implementation and the impact of the adjustment of the cavity photon lifetime of industrially fabricated wafer-fused VCSELs emitting in the 1.5 µm waveband. This adjustment is accomplished by precise, “digital” removal of a prescribed thickness of the top DBR layer with nm-scale precision. By optimal cavity lifetime adjustment, we demonstrate significant enhancement of both the continuous wave (cw) and the dynamic performance of the VCSELs. In addition, the analysis of the devices yields internal device parameters of the VCSELs investigated, important for further improvement of their performance.
2. VCSEL fabrication
The VCSEL emitting at a peak wavelength of about 1490nm were fabricated by metal-organic vapor phase epitaxy (MOVPE) and wafer fusion technology [5, 6]. The wafer fusion assembly process consists of three separate epitaxial growths, two on GaAs substrates for the top and bottom DBRs and one on an InP substrate for the quantum well (QW) active region, tunnel junction (TJ) carrier injector, and surrounding InP intracavity Ohmic contact layers. The InP-based layers are subsequently fused to the bottom DBR and the InP substrate is removed. Next the top GaAs-based DBR is fused to the InP-based layers, and its GaAs substrate is removed.
The active region incorporated six 6.5 nm ~1 compressively strained InAlGaAs QWs with PL emission at 1440 nm surrounded by 7 nm-thick InAlGaAs barriers with ~-0.8% of strain. A highly doped p+/n + 30 nm-thick InAlGaAs tunnel junction (TJ) was inserted in the node of optical field intensity of the fundamental (LP01) mode. The InAlGaAs layers contain approximately 10% of aluminum in order to further minimize the absorption and the optical cavity length was 2.5 λ. The n-type InAlGaAs was doped with silicon with a hole concentration value of 5 × 1019 cm−3 while the p-type was doped with carbon with a hole concentration of about 2 × 1019 cm−3. Undoped and ungraded Al0.9Ga0.1As/GaAs and Al0.95Ga0.05As/GaAs DBRs were used for the top and bottom mirrors, respectively. The thickness of the upper GaAs layer of the top DBR was dGaAs = 110 nm. The top DBR contained 19.5 λ /4 optically-thick mirror pairs, while the bottom DBR consisted of 35 mirror pairs. The investigated VCSELs had a nominally 7-μm diameter TJ mesa and a 20-μm diameter top DBR post. An 1.8-μm-thick Si3N4 deposition was used for DBR sidewall protection prior to the top DBR “digital etching” described next. Figure 1 shows a schematic cross-section of the wafer-fused VCSEL structure.
Fig. 1 Schematic crossing section of the VCSEL device (left) and enlarged view of the topmost GaAs DBR layer and its adjacent AlGaAs DBR layer with an indication of the thickness of the GaAs (dGaAs) and the depth of the “digital etching” t (right). The GaAs substrate is undoped.
Previously, via standard wet etching, we reported the impact of shallow DBR surface etching on the output coupling of similar VCSELs [7, 8]. However, we found it difficult to control the etching depth accurately (on the nanometer scale), which prevents obtaining reproducible results. In the present study, we have developed and applied a more precise procedure of shallow etching of the topmost top DBR GaAs layer, using hydrogen peroxide and citric acid, to achieve a “digital etching” process [9]. In this process, the oxidation of the GaAs surface and the etching of the subsequent oxide are performed separately, in two steps. During each etching cycle, the removed thickness of GaAs is determined by the amount of GaAs consumed in the oxidation step. Special attention should be paid to completely rinsing the hydrogen peroxide before applying the citric acid, and vice versa. This process was implemented on pieces (2.5 × 3.5 mm2) of a fabricated VCSEL wafer containing 10 × 10 arrays of VCSELs glued with epoxy onto a silicon wafer. We measured an average of 4 nm/cycle of GaAs removed for a minimum of 10 seconds exposure to each agent, in good agreement with the data published in [9].
The size of the etched aperture is equal to the top DBR diameter, thus 20 μm that is much larger than the mode size defined by the diameter of the TJ mesa (7 µm).
Several values of etch depth t (see Fig. 1) were obtained, each followed by a full device characterization at two temperatures (20 and 70°C). First, static characteristics were recorded on a semi-automatic probe station for all devices on a given wafer piece. Almost all of the investigated VCSELs showed a similar behavior. The few devices that showed anomalous behavior exhibited deterioration of the top DBR surface and were not considered in the subsequent analysis.
More rigorous analysis of the deterioration of the surfaces was done during a failure analysis project and will be reported in detail elsewhere. Here, it is important to mention that the main root cause of the deterioration was due to residues of organics on the surface before first cycle of digital etching. The quality of the digital etching was dramatically improved by adding a first step of digital etching as described using Oxygen plasma and citric acid. It turns out that Oxygen plasma is effectively burning the residual organics and at the same time is forming an oxide layer then is removed by citric acid. With this improvement, mass production should be efficient.
For small signal modulation measurements, the VCSEL light was coupled to a single mode (SM) optical fiber, which was connected first to a network analyzer (Agilent N5230A PNA-L). The VCSEL current was directly modulated using the network analyzer through a high frequency bias-T and fed to the VCSEL by means of a high-speed 25 GHz RF probe (Picoprobe 40A-GS-150-P from GGB Industries Inc.). For large signal modulation tests, the VCSEL emission was coupled into a SM optical fiber patch-cord without an optical isolator. No special effort for additional heat-sinking was taken. The VCSEL light was detected by a high speed photo detector (XPDV2020R with 50GHz BW at ~1.5 μm from u2t GmbH) combined with an oscilloscope (Agilent 83434A) using a non-return to zero (NRZ) data modulation format with a pseudorandom binary sequence (PRBS) of word length 27-1 in a standard back-to-back measurement configuration (bit pattern generator Luceo Technologies GmbH XBERT/ ParalleXTM). Small and large signal modulation experiments were carried out on 5 devices, 4 of which showed similar results. In the following, we present and discuss the measured results for one of these typical VCSELs.
3. VCSEL analysis
3.1. Static characteristics
The cw light output power–current (L-I) characteristics of one VCSEL after each etch step with different etch depths t are shown in Fig. 2. The digital etching process did not have any detrimental impact on the I-V characteristics (not shown). As expected, an increase in threshold current, slope efficiency and maximum emitted power was observed with increasing values of t, due to the increasing cavity losses. In the inset of Fig. 1, the emission spectra of an un-etched VCSEL (t = 0) operating at a driving current of 14 mA is shown. The un-etched device exhibits single mode operation with a side-mode suppression ratio (SMSR) exceeding 40 dB up to 14 mA driving current. By increasing the etch depth, the single-mode operation regime was extended up to higher bias currents. All devices emitted around a wavelength of 1490 nm.
Fig. 2 Room temperature light output power-current characteristics of ~1490 nm VCSELs with a 7- μm-diameter tunnel junction current source with different etch depth t values. The inset shows a typical emission spectrum of an un-etched VCSEL (t = 0) at I = 14 mA.
The investigated devices were tested only at a current up to 20 mA in order to minimize the risk of any possible degradation, because the rollover current is higher than 30 mA and we were afraid to loose samples during tests. In total, each sample was tested at least 50 times up to 20 mA in a temperature range from 0 to 70°C, 10°C step 6 times for the initial un-etched device and after 5 etching cycles, then the spectral and speed measurements. The bulk of the accumulated data is yet to be analyzed and will be reported elsewhere.
These devices show a promisingly high output power compared to the data published in [10]. Such investigation of the identification of a reproducible algorithm of etching related to the maximum power is planned and will be reported later.
The L-I characteristics for the same VCSEL with different values of top DBR mirror reflectivity enabled to extract the internal quantum efficiency, ηi (unitless) and the internal optical losses rate, αi (in inverse time) following the procedure described in [4]. The differential quantum efficiency is written:
where is the slope efficiency (W/A) measured from a given L-I characteristic for a given etch depth t. The top and bottom mirror loss rate parameters αmT and αmB (in inverse time) are calculated numerically using the effective index method along with the 2x2 transfer matrix method to determine the reflectivity of the DBRs [11, 12]. The term αmT is a function of t where αmT increases as t increases from 0 to ~110 nm (the thickness of the topmost λ/4-thick GaAs DBR layer). We assume ηi and αi are independent of etch depth t.The plots of the inverse of the differential quantum efficiency values ηd (unitless) versus the inverse of the calculated top DBR loss, for each value of t, fit well a linear dependence, as observed on Fig. 3(a). The linear fit and Eq. (2) allow the extraction of the internal VCSEL parameters, yielding an internal quantum efficiency ηi of 92% at 20°C and 58% at 70°C, and an internal optical losses αi of 0.078 ps−1 at 20°C and 0.120 ps−1 at 70°C.
Fig. 3 (a) The inverse of the measured differential quantum efficiency of ~1490 nm VCSELs with a 7-μm-diameter tunnel junction current source with different values of etch depth t versus the inverse of the calculated top DBR losses at two different temperatures. (b) The calculated photon lifetime at different etch depth values t at room temperature.
We note that the increase in internal losses with increasing temperature, which are coupled to Auger recombination process, lead to an increase in the carrier density with temperature and a stronger increase in the Auger current at threshold. The increase in internal optical loss with temperature is most likely attributed to Inter-Valence-Band-Absorption (IVBA), which affects the differential quantum efficiency [13].
The reduced quantum efficiency at higher temperatures may be attributed to the larger, temperature dependent Auger recombination in AlGaInAs/InP QWs [14].
Using the extracted internal cavity loss rate and the calculated loss rates into both DBRs, the photon lifetime can be calculated using [4]:
Figure 3(b) presents the calculated photon lifetime τp versus the etch depth, at room temperature. By increasing the etch depth t, the photon lifetime decreases, reaching minimum local at ~110 nm corresponding to a quarter wavelength, then increases again. This change in τp with t illustrates the use of the DBR trimming for increasing the differential efficiency () and hence increasing the SM output power of the VCSEL. Although this is achieved at the expense of an increase of the threshold current (as can be seen in Fig. 2), an overall optimum of the VCSEL’s cw performance can be obtained by adjusting t (for given starting top DBR design with a specific number of original DBR periods), where the definition of “optimum” here depends on the desired VCSEL application.
3.2. Small signal modulation
The impact of shallow etching on the VCSEL dynamic characteristics was investigated by measuring the small signal response of the devices. The s21 response of the devices, for the current values at which the maximum cutoff frequency was observed for a given etch depth t, is presented in Fig. 4(a). The un-etched VCSEL device shows a maximum −3-dB cutoff frequency of 7 GHz obtained at a driving current of 10 mA. With increased etch depth t, a higher bandwidth value is obtained at higher operation current. A −3-dB cutoff frequency of 9 GHz is reached for t = 80 nm, for a bias current of 14 mA.
Fig. 4 (a) The measured small-signal modulation response (s21) for different values of etch depth t, at room temperature (doted curves) at the bias current (I) giving a maximum −3 dB bandwidth frequency. The fits (solid curves) to the 3-pole transfer function are also plotted. (b) Plots of the extracted K-factor and the maximum −3 dB frequency versus the etch t, at room temperature.
From the fitting of the measured s21 curves with the standard 3-pole transfer function for laser diodes, one can extract the relaxation resonance frequency , the parasitic cut-off frequency , and the damping factor . The damping factor rises with the square of the relaxation resonance frequency through the relation [4]:
with a slope given by the K-factor and a damping offset given by . To improve a given VCSEL’s modulation performance, it is generally desirable to reduce the damping. We note however that to obtain optimal eye diagrams for error-free data transmission with minimum jitter some damping is beneficial at moderate bit rates whereas generally the damping should be minimized for the highest bit rates [15].The improvement of the bandwidth obtained in Fig. 4(a) is linked to the dependence of the K-factor on the photon cavity lifetime τp, given by [4]
where vg is the group velocity, dg/dn the differential gain, ε the gain saturation coefficient, and χ is the transport factor. Using the procedure outlined above, we have extracted the K-factor values versus the etching depth t and plotted the result in Fig. 4(b). We observe more than a 40% decrease of the K-factor by etching 80 nm of GaAs from the top DBR, as expected from the photon lifetime reduction. As in the case of the static performance, one can select the optimal depth of etching by considering the trade-off among the different VCSEL parameters.3.3. Large signal modulation
We have performed data transmission experiments with our cavity-adjusted ~1490 nm VCSELs using a 10.3 Gb/s pseudo-random binary sequence (PRBS) of word length 27-1 with a 0.49V peak-to-peak nonreturn-to-zero (NRZ) modulation signal. The room temperature back-to-back (BTB) optical eye diagrams for VCSELs with t = 0 nm and t = 80 nm, recorded under the same driving conditions and with the same VCSEL bias current value of 9 mA, are shown in Fig. 5. The ~1490 nm-emitting VCSELs with t = 80 nm exhibit an open eye diagram, as expected from the improved small-signal modulation response and the increased slope efficiency demonstrated above.
Fig. 5 Room temperature BTB data transmission experiment with the cavity-adjusted 1490 nm VCSELs, showing optical eye diagrams for t = 0 nm (a) and at t = 80 nm (b).
When operated at the same driving conditions, the optical eye diagram results indicate that the VCSEL with reduced damping (t = 80 nm) shows a larger overshoot, a higher signal to noise ratio (SNR) of 11.21 dB and a fast rise time of 38 ps comparing to the un-etched VCSEL with an SNR of 9.09 dB and a rise time of 43 ps.
4. Conclusion
We have developed a digital chemical etching technique for selectively reducing the thickness of the topmost GaAs layer of a DBR with nm precision, and used this technique to adjust the cavity photon lifetime of a wafer-fused VCSELs emitting at a wavelength of about 1490 nm. This fine adjustment of the cavity photon lifetime resulted in an improvement of both the static (increased L-I slope efficiency) and the dynamic performance of the VCSELs (reduced K-factor and increased −3 dB bandwidth). The cavity adjustment procedure is compatible with full-wafer, industrial fabrication of these VCSELs. The procedure should allow the post-processing and thus fine-tuning of the VCSEL performance parameters before device thinning and dicing. The net results should be an increase in wafer yield, device uniformity, and a reduced production cost. The performance of our VCSELs is in line with that needed for applications in high-speed optical fiber networks for fiber-to-the-home applications.
Acknowledgments
This work has been partly funded by CTI project (12874.1 PFNM-NM).
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