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Design and characterization of a p+/n-well SPAD array in 150nm CMOS process: erratum

Hesong Xu, Lucio Pancheri, Gian-Franco Dalla Betta, and David Stoppa

Open Access Open Access

Abstract

An erratum is presented to correct a reference mistake in Table 1 in Sect. 4 of [Opt. Express 25, 12765 (2017)].

© 2017 Optical Society of America

In our paper [1], we discovered a reference error. The error is in Table 1, which is on page 12778. In the last column of Table 1, the technology is “65nm CMOS Imaging Process” instead of “65nm CMOS Technology”; The PDP peak is “27.5%(@640nm)” instead of “27.5%(@425nm)”.

References and links

1. H. Xu, L. Pancheri, G.-F. D. Betta, and D. Stoppa, “Design and characterization of a p+/n-well SPAD array in 150nm CMOS process,” Opt. Express 25(11), 12765–12778 (2017). [CrossRef]  

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