1. Introduction

Recently GaN-based light-emitting diodes (LEDs) have attracted considerable interest for their usefulness in disinfection, automotive front lighting, solid-state lighting and full-colour displays because of their high luminous efficiency, low energy consumption, long operation lifetime, and broad spectral range spanning from ultraviolet to red wavelengths [1–8]. Increasing the luminance necessitates reaching higher current densities, and this calls for innovative new LED designs that are capable of operating at high power and offering low thermal resistance. One possible way to solve this problem is to use flip-chip technology [9–12]. In flip-chip LED (FCLED) configuration, the light-emitting chip is inverted compared to top-emitting LEDs, so that photons could be emitted freely from the substrates. The disadvantage of this configuration is that a substantial amount (about 50%) of light propagates downward, which does not contribute to useable light output. One should be able to obtain a much higher light extraction efficiency (LEE) of FCLED by depositing a reflector onto p-GaN layer so that downward photons can be reflected upward. Accordingly, achieving p-type ohmic contact with high reflectivity and low contact resistance plays a pivotal role in the realization of high-efficiency FCLEDs.

Indium tin oxide (ITO) in combination with a distributed Bragg reflector (DBR), which is made of an array of alternating dielectric layers with high and low refractive indices, have been used as highly reflective p-electrodes in FCLEDs [13–16]. However, the dielectric DBR, used primarily to reflect a narrow range of wavelengths, exhibits strong angular dependence. As an alternative approach to DBRs, metallic reflectors including aluminium (Al), magnesium (Mg) and silver (Ag), which exhibit high reflectance over a broad range of wavelengths of incident light from arbitrary angles, is a potential highly reflective p-electrode that can be used in FCLEDs [17–21]. Compared to metallic Al, Ag is a particularly attractive candidate reflector for use in the visible regime due to its large optical reflectance in this wavelength range and superior electrical and thermal conductivity. However, Ag suffers from insufficient adhesion properties and poor thermal stability, leading to the agglomeration of Ag during high-temperature thermal annealing process [22]. For this reason, an interlayer such as Ni beneath Ag film has been used to overcome these issues [23,24]. The drawback of using such additional layers is that they degrade the reflectivity of the electrode and thus the extraction efficiency due to strong absorption of light by these interlayers. Recently, Zhou et al. reported that the deposition of a thin TiW barrier diffusion layer (80 nm) onto Ag can suppress Ag agglomeration and thus maintain a high reflectance during high-temperature thermal annealing process [25]. However, the thin TiW barrier layer (80 nm) cannot effectively prevent Ag from diffusing into insulating SiO₂ layer at high temperatures (above 400°C), which is detrimental to device operation and reliability.

When operating FCLEDs at high current densities, the current crowding effect is still a challenging problem limiting the further improvement in device performance [26]. Therefore, another critical factor in the design of high-power LEDs is achieving uniform current spreading without compromising light absorption or light extraction at high current densities. Previous work proposed that current spreading in LEDs can be improved by adjusting the conductivity of the n-GaN layer [27]. However, to obtain a low sheet resistance and achieve excellent lateral current spreading, a silicon (Si) doping-level greater than 1.5 × 10¹⁹ cm⁻³ in the n-GaN layer is required, which results in some cracks and pits in the grown n-GaN layer [28]. Therefore, it seems unrealistic that superior current spreading can be obtained by only increasing the conductivity of the n-GaN layer. Moreover, several analytical models have been proposed to evaluate the impact of the geometric electrode pattern on current spreading [29]. It has been shown that an optimized electrode pattern can improve optical and electrical characteristics of LEDs by facilitating uniform current spreading [30]. However, in these schemes, finger-like n-electrodes reduced the active light-emitting area and caused light absorption, which decreased the LEE.

In this work, we investigate the impact of incorporating an Ag-based metallic reflector and an ITO/DBR on the optical and electrical properties of FCLEDs. The DBR is composed of two TiO₂/SiO₂ stacks, with each DBR stack comprised of seven pairs of alternating TiO₂/SiO₂ dielectric layers. The Ag-based metallic reflector is constructed by stacking three pairs of TiW/Pt bilayers periodically on an Ag film, which significantly suppresses the agglomeration of Ag and effectively prevent Ag from diffusing into dielectric TiO₂/SiO₂ DBR during high-temperature thermal annealing process. We demonstrate low-resistance ohmic contact to p-GaN using pure Ag, which offers a reflectance of approximately 95.0% at normal incidence and 460 nm. As a result of replacing the ITO/DBR with the Ag-based reflector, the light output power of the FCLED increases by 6.0%. Replacing the finger-like n-electrodes with 3D vias n-electrodes results in further 5.2% improvement in the efficiency of the FCLEDs.

2. Experimental methods

2.1. Growth and device fabrication

GaN epitaxial layers were grown on a c-plane (0001) patterned sapphire substrate by metal-organic chemical vapour deposition in a VEECO K465i (Veeco, NY, USA) reactor. The GaN-based LED structure was composed of a 25-nm-thick low-temperature GaN nucleation layer grown at 510°C, a 3.0-µm-thick undoped GaN buffer layer grown at 1025°C, a 2.5-µm-thick Si-doped n-GaN layer (Si doping = 1 × 10¹⁹ cm⁻³) grown at 1025°C, a 201-nm-thick InGaN/GaN superlattice grown at 820°C, an InGaN/GaN MQWs active region including nine pairs of 3-nm-thick InGaN well layers at 760°C and 11-nm-thick GaN barrier layer at 830°C, a 10-nm-thick Mg-doped p-In_0.05Ga_0.95N layer (Mg doping = 5 × 10¹⁹ cm⁻³) grown at 780°C, a 20-nm-thick Mg-doped p-Al_0.2Ga_0.8N electron-blocking layer (Mg doping = 1 × 10²⁰ cm⁻³) grown at 910°C, and a 110-nm-thick Mg-doped p-GaN layer (Mg doping = 5 × 10¹⁹ cm⁻³) grown at 950°C (see Fig. 9 in Appendix). The peak wavelength of FCLEDs is 460 nm. The chip dimensions of FCLEDs are 45 × 45 mil². The detailed processing steps of FCLED-I, FCLED-II, FCLED-III and conventional lateral LED are presented in Figs. 10–12 in Appendix.

2.2. Materials and device characterization

The structural properties of the FCLEDs were analysed using SEM in combination with focused ion beam milling (FEI Nova 3D). HAADF-STEM (FEI Tecnai F20 system) was combined with EDX spectroscopy to further analyse the structural features of the FCLEDs. The optical properties of the Ag-based reflectors were analysed using a UV-Vis spectrophotometer (Lambda 750 S, PerkinElmer, USA). The reflectance spectra of ITO/DBR and Ag/TiW/Pt/TiW/Pt/TiW/Pt at different incident angles were analysed using a variable-angle spectroscopic ellipsometer (W-VASE, J.A. Woollam, USA). The chemical analysis of the samples was carried out in an X-ray photoelectron spectroscopy (XPS, ESCALAB 250Xi, Thermo Fisher, UK). The current–voltage (I–V) characteristics were measured at room temperature by using a semiconductor parameter analyser (Keithly 2400). The light output power–current (L–I) characteristics of LED were determined using a calibrated integrating sphere.

2.3. First principles calculations

The first principles calculations were carried out using projector-augmented wave (PAW) method based on density functional theory (DFT) [31]. The generalized gradient approximation (GGA) in the Perdew-Burke-Ernzerh (PBE) form was taken into account as exchange-correlation energy functional [32]. The plane-wave expansion of the electronic wave function was set to 300 eV energy cutoff. For k-point sampling in calculations of the interfacial structure, 8 × 8 × 1 Monkhorst-Pack grid were used. Ag/GaN interface were modelled using the periodic heterostructures formed by a slab of four atomic planes of the Ag(111) metal and a slab of four bilayers of GaN(0001). The overall thickness of the supercell was 25 angstroms.

3. Results and discussion

Figure 1 shows top-view scanning electron microscopy (SEM) images of Ag (100 nm), Ag (100 nm)/TiW (120 nm), Ag (100 nm)/TiW (300 nm), and Ag (100 nm)/TiW (120 nm)/Pt (10 nm)/TiW (90 nm)/Pt (10 nm)/TiW (90 nm)/Pt (100 nm) films before and after annealing at 600°C. All samples appear similar in the surface morphology before thermal annealing process, as shown in Figs. 1(a), 1(b), 1(e) and 1(g). However, the sample shows voids and agglomeration in the Ag film after annealing at 600°C, as shown in Fig. 1(b). We note that voids and agglomeration in Ag film are suppressed by adding a TiW cladding layer, as shown in Figs. 1(d) and 1(f). Due to the large difference in thermal expansion coefficient between TiW (4.6~10.8 × 10⁻⁶/°C) and Ag (20 × 10⁻⁶/°C), the tensile stress generate in the Ag/TiW layers upon cooling down from the annealing temperature. The amount of strain within the Ag/TiW layers depends on the thickness of the TiW layer. To effectively prevent Ag from diffusing into dielectric layers, the thickness of TiW diffusion barrier layer need to be greater than 300 nm. However, when the thickness of the TiW layer exceeds 300 nm, cracks appear in the Ag/TiW layers upon cooling down from the annealing temperature, as shown in Fig. 1(f). The insertion of several thin Pt layers into the thick TiW layer was found to avoid crack formation in the Ag/TiW layers after annealing at 600°C, as shown in Fig. 1(h).

 

Fig. 1 Top-view SEM images of the films before and after annealing at 600°C: (a, b) Ag (100 nm), (c, d) Ag (100 nm)/TiW (120 nm), (e, f) Ag (100 nm)/TiW (300 nm), and (g, h) Ag (100 nm)/TiW (120 nm)/Pt (10 nm)/TiW (90 nm)/Pt (10 nm)/TiW (90 nm)/Pt (100 nm) films. Nanoindentation tests on samlpes at 25°C before and after annealing at 200°C: (i) Examples of nano indents, (j) Comparison between hmax from Ag (100 nm)/TiW (120 nm), Ag (100 nm)/TiW (300 nm), and Ag (100 nm)/TiW (120 nm)/Pt (10 nm)/TiW (90 nm)/Pt (10 nm)/TiW (90 nm)/Pt (100 nm).

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Nanoindentation with a sharp indenter could be utilized for the evaluation of residual stress (see Fig. 13 in Appendix). To elucidate the underlying mechanism of crack-free Ag/TiW/Pt/TiW/Pt/TiW/Pt films after high-temperature annealing, stress within deposited films was estimated by nanoindentation tests at 25°C before and after annealing at 200°C. Berkovich indenter was used, and tests were carried out in load-control mode with depths of nano indents reaching approximately half of the thickness of each film, for instance, 60 nm in Ag/TiW (120 nm), 150 nm in Ag/TiW (300 nm) and 150 nm in Ag/TiW/Pt/TiW/Pt/TiW/Pt. To be more representative and compelling, 7~8 indents were made in each sample for repeatability. Topography of typical indent was illustrated in Fig. 1(i). Maximum depth (h_max) from different samples were summarized in Fig. 1(j) before and after annealing at 200°C. In comparison to h_max from other two samples, h_max from Ag/TiW (120 nm) is much lower, and this is a result of more evident effect from GaN/sapphire substrate. Moreover, a noticeable rise in h_max can be observed in Ag/TiW (300 nm) after annealing with a value of 15.3 nm. However, increase of h_max in Ag/TiW (120 nm) and Ag/TiW/Pt/TiW/Pt/TiW/Pt were relatively much smaller, 1.3 nm and 3.1 nm, respectively. It has been frequently reported that tension stress within sample can notably increase the maximum depth [33,34]. Higher increase in h_max from Ag/TiW (300 nm) indicates much severer tension stress within TiW (300 nm) after annealing. Accordingly, the formation of crack-free Ag/TiW/Pt/TiW/Pt/TiW/Pt is attributed to the fact that the introduction of such thin Pt layer decreases the tension stress within the films.

Figure 2(a) shows the reflectance spectra of Ag (100 nm), Ag (100 nm)/TiW (300 nm), and Ag (100 nm)/TiW (120 nm)/Pt (10 nm)/TiW (90 nm)/Pt (10 nm)/TiW (90 nm)/Pt (100 nm) films before and after annealing at 600°C, where the nm dimensions give the thickness of each layer. The reflectance of the as-deposited Ag film and 600°C-annealed Ag film at 460 nm were measured to be 90.6% and 83.7%, respectively. The reduction in the reflectance of Ag after thermal annealing was mainly attributed to the agglomeration of Ag. The reflectance of as-deposited Ag/TiW and 600°C-annealed Ag/TiW was measured to be 91.9% and 89.1%, respectively. The reflectance of Ag/TiW exhibited a slight decrease caused by cracks on the surface of Ag/TiW after annealing at 600°C. However, due to the reduced Ag agglomeration, the reflectance of Ag/TiW shows a 5.4% enhancement compared with the pure Ag after annealing at 600°C. The as-deposited and 600°C-annealed Ag/TiW/Pt/TiW/Pt/TiW/Pt had almost the same reflectance of approximately 95.0% at 460 nm. This shows that the TiW/Pt/TiW/Pt/TiW/Pt stacks effectively prevented Ag from degrading during the high-temperature annealing process, in good agreement with the observed surface morphologies in Fig. 1.

 

Fig. 2 (a) Reflectance spectra of the as-deposited Ag (100 nm), Ag (100 nm)/TiW (300 nm), and Ag (100 nm)/TiW (120 nm)/Pt (10 nm)/TiW (90 nm)/Pt (10 nm)/TiW (90 nm)/Pt (100 nm) films at normal incidence. (b) Optical microscopy image of the Ag CTLM pads. (c) I-V characteristics of the Ag contact to the p-GaN layer when annealed at different temperatures. (d) I-V curves of measured for different gap spacings of the CTLM patterns for the Ag contacts deposited on p-GaN after annealing at 600°C. (e) The XPS depth profile of Ag/p-GaN contact without annealing treatment. (f) The XPS depth profile of Ag/p-GaN contact with 600°C annealing treatment.

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To investigate the ohmic contact between the Ag film and p-GaN, circular transfer length method (CTLM) patterns with an inner-dot radius of 50 μm and gap spacing of 5-35 μm were defined using optical photolithography to measure specific contact resistance, as shown in Fig. 2(b). The effect of the annealing temperature on the Ag contacts to p-GaN is shown in Fig. 2(c). At annealing temperatures of 400 and 500°C, the Ag contacts with p-GaN showed nonlinear I-V characteristics. However, after annealing at 600°C, the Ag contact with p-GaN exhibited excellent ohmic contact. Figure 2(d) shows the CTLM plot of an as-deposited Ag contact with a p-GaN sample annealed at 600°C. The specific contact resistance was determined from the plots of the measured resistance as a function of spacing between the CTLM pads. The least squares method was used to fit a straight line to the experimental data. Here, the specific contact resistance of the 600°C-annealed Ag contact with p-GaN was measured to be 7.33 × 10⁻² Ω cm².

It has been reported [35] that Ga migrates into the Ag reflector and that Ag in turn diffuses into the p-GaN layer due to their different growth temperatures and thermal-annealing temperatures. These elemental diffusion phenomena will impact the optical and electrical properties of LEDs. We investigated the elemental inter-diffusion phenomenon at the Ag/GaN interface by performing XPS measurements. Figure 2 compares the XPS depth profiles obtained from the Ag/p-GaN contact before and after annealing at 600°C. After annealing treatment, the thickness of pure Ag layer reduced and the intermixing region of Ag, Ga and N atoms became larger, demonstrating improved intermixing at the Ag/GaN interface. The XPS depth profiles ambiguously revealed that the interface between the Ag and GaN layers was diffused: (1) Ga and N migrate into the Ag reflective layer and (2) Ag migrates into p-GaN layer.

High-temperature annealing and non-negligible kinetic energies of impinging species for Ag film deposition by ion beam sputtering result in intermixed interfaces, as evidenced in Fig. 2(e). Moreover, atomic structure of the metal-semiconductor (MS) interface is expected as a factor that impacts contact performance [36]. To elucidate the ohmic contact mechanism between the Ag and p-GaN, first principles calculations were performed to investigate the effect of interfacial diffusion on electronic properties of Ag/GaN interface. Different interfacial composition was studied by exchanging various Ag atoms to the Ga atoms. Five interfacial composition configurations were considered and corresponding atomic structures of Ag/GaN interface are shown in Fig. 14 in Appendix.

The layer density of states (LDOS) projected on each atomic layer were calculated by summing over all atomic sites for the respective atomic bilayers in the interface. The LDOS of the GaN side of the MS interface are plotted in Figs. 3(a–f). For non-diffusion interfacial condition, Figure 3(a) shows noticeable band gap in layer1 of GaN bilayer and the band gap slight reduces in layer2 and layer3 of GaN bilayer. A key feature in Fig. 3(a) is that layer4 shows non-zero electronic states in the band gap, indicating that interface region of GaN becomes metallic. For the case of Ag atom diffuses from layer5 to layer4, as shown in Figs. 3(b) and 3(c), the energy states in the band gap of layer4 increase as the number of diffused Ag atoms increases from one to two. Furthermore, as the diffusion interface is thickened, as shown in Figs. 3(d) and 3(e), the band gap significantly reduces in layer3, resulting in a more conductive contact interface between Ag and GaN. A further comparison is shown in Fig. 3(f). The energy states increase in the band gap of layer4 as the number of the diffused atoms increases and the depth of the diffusion increases. The Schottky barrier height (SBH) between metal and semiconductor can be computed from first-principles supercell calculations using the macroscopic averaging method [37,38]. The p-type SBH may be written as:

 

Fig. 3 The LDOS projected on each atomic layer of the GaN side. (a) Non-diffusion condition. (b) One Ag atom diffuses from layer5 to layer4. (c) Two Ag atoms diffuse from layer5 to layer4. (d) One Ag atom diffuses from layer6 to layer4 and from layer5 to layer3. (e) Two Ag atom diffuses from layer6 to layer4 and from layer5 to layer3. (f) Detailed LDOS in layer4 of GaN bilayers with different interfacial composition. (g) SBH and the change in average electrostatic potential across the interface ($\Delta V$) for difference diffusion interfacial condition.

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The bandwidth of a high reflectance (>90%) region for a single DBR stack composed of quarter wavelength layers of TiO₂ and SiO₂ can reach up to 145 nm. But reflectance from a DBR exhibits an angular dependency. As the incident light deviates from normal incidence, the width of the high reflection band is narrowed and blue shifted (see Fig. 15(a) in Appendix). Therefore, some loss of high-angle green and yellow photons will be incurred for DBR optimized for central wavelength at 460 nm blue light wavelength. The low reflectance of the conventional single DBR stack in the green and yellow light wavelength regions may decrease the luminous efficiency of packaged LEDs. It is worth noting that the reflective bandwidth of the single DBR stack redshifts as the thickness of the TiO₂ and SiO₂ increases (see Fig. 15(b) in Appendix). The redshift toward the long wavelength with increasing thickness of TiO₂ and SiO₂ can counteract the blueshift toward the short wavelength when the incident light deviates from normal incidence. Thus, to maximize the redirection of all emitted photons upwards and obtain wide reflectance bandwidth, we combined two single TiO₂/SiO₂ DBR stacks, each optimized for different central wavelength, into a double DBR stacks. The first DBR stack contained seven pairs of TiO₂/SiO₂ (46.4 nm/78.8 nm) dielectric layers optimized for a central wavelength of 460 nm; the second DBR stack included another seven pairs of TiO₂/SiO₂ (60.4 nm/102.7 nm) dielectric layers optimized for a central wavelength at 600 nm. Therefore, taking an angle-induced blue shift into account, this structure should be most efficient in the blue, green and yellow wavelength regions. We measured the reflectance of ITO/DBR and Ag/TiW/Pt/TiW/Pt/TiW/Pt at different incident angles by using a variable-angle spectroscopic ellipsometer. At normal incidence, the reflectance of the DBR was 3.0% higher than that of the Ag metallic reflector. As the angle of incidence became increasingly oblique, the reflectance of the metallic reflector was almost constant while the reflectance of the ITO/DBR decreased significantly. The reflectance of ITO/DBR decreased from 97.9% to 65.8% at 460 nm when the incident angle increased from 0° to 80°, whereas the reflectance of Ag/TiW/Pt/TiW/Pt/TiW/Pt remained roughly constant at 95.0%. As a result, the average reflectance of ITO/DBR was approximately 79.4%, which is 15.6% lower than that of Ag/TiW/Pt/TiW/Pt/TiW/Pt films, revealing that the FCLED with Ag-based reflector can obtain higher LEE. Figures 4(c) and 4(e) show magnified cross-sectional TEM images of the Ag/TiW/Pt/TiW/Pt/TiW/Pt films and the TiO₂/SiO₂ DBR, respectively. Figures 4(d) and 4(f) reveal the compositional fluctuations in the Ag/TiW/Pt/TiW/Pt/TiW/Pt films and the TiO₂/SiO₂ DBR along the dotted lines in Figs. 4(c) and 4(e), respectively.

 

Fig. 4 (a) Measured reflectance of ITO/DBR as a function of the wavelength at normal, 20°, 40°, 60°, and 80° angles of incidence. (b) Measured reflectance of ITO/DBR and Ag/TiW/Pt/TiW/Pt/TiW/Pt as a function of the incident angle at a wavelength of 460 nm. (c) Magnified cross-sectional TEM image of the Ag/TiW/Pt/TiW/Pt/TiW/Pt films. (d) EDX line-scan performed vertically along the Ag/TiW/Pt/TiW/Pt/TiW/Pt films in (c). (e) Magnified cross-sectional TEM image of the 14-pair TiO₂/SiO₂ double DBR stacks. This design contains two single TiO₂/SiO₂ DBR stacks; each single DBR stack includes seven pairs of alternating TiO₂/SiO₂ dielectric layers that are optimized for different central wavelength. (f) EDX line-scan performed vertically along the TiO₂/SiO₂ DBR in (e).

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Figures 5(a–i) show the top-view and cross-sectional SEM images of three types of FCLEDs (labelled as FCLED-I to FCLED-III). The cross-sectional SEM images were obtained using focused ion beam (FIB) milling along different directions, as marked in Figs. 5(a), 5(d), and 5(g). In FCLED-I (Fig. 5(a)), transparent ITO in combination with 14-pair TiO₂/SiO₂ double DBR stacks was used as a highly reflective p-type ohmic contact, and finger-like p- and n-electrodes (Cr/Al/Ti/Pt/Au) were distributed uniformly over the whole chip, which can reduce the lateral current spreading distance between the p-electrodes and n-electrodes. Since the sheet resistance of the as-deposited ITO layer (40 Ω/sq) is much larger than that of the as-grown n-GaN layer (12 Ω/sq), the current crowding occurs around the p-electrode in FCLED-I. To alleviate current crowding around the p-electrode, a SiO₂ current blocking layer was inserted underneath the p-electrode (Fig. 5(c)) to prevent the current from being concentrated in regions adjacent to the p-electrode where any light emanated from InGaN/GaN MQWs active region would be absorbed by the opaque p-electrode.

 

Fig. 5 (a) Top-view SEM image of FCLED-I. (b) Cross-sectional SEM image of FCLED-I milled by an FIB along the A-A direction. (c) Cross-sectional SEM image of FCLED-I milled by an FIB along the B-B direction. (d) Top-view SEM image of FCLED-II. (e) Cross-sectional SEM image of FCLED-II milled by an FIB along the C-C direction. (f) Cross-sectional SEM image of FCLED-II milled by an FIB along the D-D direction. (g) Top-view SEM image of FCLED-III. (h) Cross-sectional SEM image of FCLED-III milled by an FIB along the E-E direction. (i) Cross-sectional SEM image of FCLED-III milled by an FIB along the F-F direction.

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In FCLED-II, Ag-based metallic reflector (Ag/TiW/Pt/TiW/Pt/TiW/Pt) instead of ITO/DBR was used as highly reflective p-type ohmic contact (Figs. 5(e) and 5(f)). Owing to the superior electrical conductivity of Ag (6.301 × 10⁷ S/m), current crowding around the p-electrode can be alleviated. In FCLED-III, 3D vias n-electrodes instead of finger-like n-electrodes were arranged uniformly across the whole n-GaN surface (Fig. 5(g)). The current access to the n-GaN layer is provided by metallic electrodes (Cr/Al/Ti/Pt/Au) passing through an array of 3D vias etched through the epitaxial structure up to the n-GaN layer, leading to a reduction in the loss of InGaN/GaN MQWs area and an improvement in current spreading over the entire active region. The inclined sidewalls of the 3D vias were covered by insulating TiO₂/SiO₂ double DBR stacks to avoid short-circuit in the p-n junction and to minimize the light absorption by the opaque n-electrodes, as shown in Figs. 5(e) and 5(h). Compared with the vertical sidewalls of 3D vias, the inclined sidewalls of 3D vias can improve the step coverage ability of the deposited DBR and provide a higher LEE with a broad incident angles.

A superior current spreading can lead to uniform light-emitting intensity and improved device reliability [39–41]. To investigate the effects of electrode geometry on current spreading of FCLEDs, 3D numerical simulations of the current density were performed using SimuLED commercial software package from STR. Figures 6(a–c) show the simulation results for the current density distribution in the active region of the three types of FCLEDs at 750 mA. As a result of current crowding, high current densities occurred near the electrode edge. Current crowding occurred around the p-electrodes in FCLED-I, due to the smaller sheet resistance of the n-GaN layer (12 Ω/sq) relative to that of the ITO layer (40 Ω/sq). However, the current crowded around the n-electrodes in FCLED-II and FCLED-III, as a result of the higher sheet resistance of the n-GaN layer (12 Ω/sq) relative to that of the Ag reflector (0.16 Ω/sq). We found that replacing the finger-like n-electrodes with 3D vias n-electrodes resulted in a significant improvement in current spreading. As a consequence, the root-mean-square (RMS) value of current density in FCLED-III was 36.6% lower than that of current density in FCLED-II. Table 1 summarizes the current density distribution in active region of three types of FCLEDs at 500, 750 and 1000 mA. It can be clearly seen that the current crowding effect was effectively alleviated on moving from FCLED-I to FCLED-III.

 

Fig. 6 Simulated current density distributions in the InGaN/GaN MQWs active region of (a) FCLED-I, (b) FCLED-II, and (c) FCLED-III at 750 mA.

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Table 1. Current density distribution in the active region of the FCLEDs at 500, 750, and 1000 mA.

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Since light-emitting intensity distribution of FCLEDs is correlated with current density distribution in InGaN/GaN MQWs active region, the light-emitting intensity distribution can be used to represent the current density distribution. We measured the light-emitting intensity distributions of the three types of FCLEDs at different injection currents of 500, 750, and 1000 mA, as shown in Fig. 7. We found that the light-emitting intensity concentrated near the p-electrodes in FCLED-I, while the light-emitting intensity concentrated near the n-electrodes in FCLED-II and FCLED-III. These trends seen experimentally are consistent with those of current spreading in the simulation. Although the overall emission intensity of FCLED-I was the lowest among the three types of FCLEDs, FCLED-I presented the strongest emission intensity around the pad area, which was associated with more severe current crowding around the pad area. The introduction of a continuous metallic layer (Cr/Al/Ti/Pt/Au) in FCLED-III allowed the 3D vias n-electrodes to be arranged uniformly across the entire n-GaN layer, leading to more uniform light emission compared to that seen with FCLED-II. The area of higher light-emitting intensity in FCLED-III was larger than that in FCLED-I and FCLED-II, especially at a high injection current (1000 mA), indicating that Ag-based highly reflective p-electrode in combination with 3D vias n-electrodes is capable of high-power operation with superior current spreading.

 

Fig. 7 Measured intensity distributions of the light emitted from FCLED-I, FCLED-II, and FCLED-III at injection currents of (a,d,g) 500 mA, (b,e,h) 750 mA, and (c,f,i) 1000 mA.

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Figure 8(a) shows the current-voltage (I-V) characteristics of the FCLEDs, and the inset is the electroluminescence spectrum of the FCLED. At 750 mA, the forward voltages of FCLED-I, FCLED-II, and FCLED-III were 3.15, 3.04, and 3.00 V, respectively. Due to the negligible spreading resistance of the Ag-based p-type ohmic contact, the forward voltage of FCLED-II was lower than that of FCLED-I. By replacing the finger-like n-electrodes with 3D vias n-electrodes, the forward voltage of FCLED-III was further reduced owing to the use of 3D vias n-electrodes that spread the injection current uniformly over the entire active region. Figure 8(b) shows the light output power (LOP) and external quantum efficiency (EQE) as a function of injection current for the three types of FCLEDs under continuous-wave current operation. At 750 mA, the LOPs of FCLED-I, FCLED-II, and FCLED-III were 878.6, 914.2, and 965.2 mW, respectively. The corresponding EQEs of FCLED-I, FCLED-II, and FCLED-III were determined to be 42.0%, 44.5%, and 46.8%, respectively. Replacing ITO/DBR with the Ag-based ohmic contact increased the LEE and improved current spreading. As a result, the EQE of FCLED-II was 6.0% higher than that of FCLED-I. In addition, an increase in the EQE of 5.2% was observed when the finger-like n-electrodes were replaced with 3D vias n-electrodes. Figure 8(c) shows the far-field emission pattern of the FCLEDs at 750 mA injection current. Similar variation trends as the LOPs and EQEs are found for the far-field emission intensity of FCLED-I, FCLED-II, and FCLED-III. The FCLED-III presents improved emission intensity in all directions among the three types of FCLEDs. For the high-temperature accelerated life tests, the FCLEDs were placed in the high-temperature chamber which was controllable from room temperature to 100°C and FCLED samples were stressed at the condition of 85°C using an injection current of 1000 mA. The FCLED samples were removed from the chamber at specific intervals to measure the LOP at 700 mA. Figure 8(d) shows the optical degradation of the FCLEDs aged at 85°C under the current of 1000 mA. The LOPs increase in the early aging stage owing to the positive factors of dopant activation and the annealing effect. Even after 1000 h of aging, the FCLED-III shows negligible degradation, demonstrating superior stability than the FCLED-I and FCLED-II. The excellent stability of FCLED-III can can be attributed to two aspects: (1) the Ag-based reflector is better thermal conductor than the ITO/DBR; (2) perfect current spreading performance was achieved by taking advantage of the 3D vias electrodes.

 

Fig. 8 (a) I-V characteristics of the three FCLEDs: FCLED-I, FCLED-II, and FCLED-III. The inset figure shows the electroluminescence spectrum of the FCLED (b) LOP and EQE as a function of injection current for FCLED-I, FCLED-II, and FCLED-III. (c) Far-field emission pattern of the three FCLEDs: FCLED-I, FCLED-II, and FCLED-III. (d) Optical degradation test of the FCLEDs aged at 85°C under the current of 1000 mA.

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4. Conclusion

In summary, we have demonstrated high-power FCLEDs that incorporate a highly reflective Ag-based metallic reflector, a dielectric TiO₂/SiO₂ DBR, and a 3D vias electrodes. We showed that the deposition of alternating stacks of TiW/Pt/TiW/Pt/TiW/Pt on Ag film effectively suppresses the agglomeration of an Ag during high-temperature thermal annealing. In this way, we established an Ag-based reflector with a high reflectance of 95.0% at a wavelength of 460 nm after annealing at 600°C. Owing to the smaller spreading resistance and higher reflectance of this Ag-based reflector, a FCLED with the Ag-based reflector exhibited a higher LEE and better current spreading than the FCLED with ITO/DBR. As a result, the EQE of the FCLED with the Ag-based reflector was 6.0% higher than that of the FCLED with ITO/DBR under 750 mA injection current. Moreover, the EQE of the FCLED with the Ag-based reflector was further improved by 5.2% when finger-like n-electrodes were replaced with optimized 3D vias n-electrodes. This improvement was mainly attributed to the use of an optimum electrode pattern, which gives rise to superior current spreading and reduces the area loss of the active region. In addition, pure Ag ohmic contact combined with 3D vias-based contact scheme has the potential in future design of high-speed, high-efficiency plasmonics LED for applications in visible light communication. On the other hand, using a highly reflective double DBR stack can be beneficial for vertical-cavity surface-emitting laser (VCSEL).

Appendix

A.1. Epitaxial structures of GaN-based LEDs

Figure 9 shows the epitaxial structures of GaN-based LEDs. Three types of FCLEDs were fabricated using the wafers from the same epitaxy run.

 

Fig. 9 (a) Cross-sectional TEM image of GaN-based LED epitaxial structure. (b) Schematic illustration of GaN-based LED epitaxial structure. (c) Magnified cross-sectional TEM image of GaN epitaxial structure including p-GaN, InGaN/GaN MQWs, and InGaN/GaN SL. (d) Magnified cross-sectional TEM image of the InGaN/GaN MQWs marked by the red square in (c). (e) Magnified cross-sectional TEM image of InGaN/GaN SL marked by the blue square in (c).

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A.2 Processing Scheme for FCLED-I

Schematic illustration of these steps appears in Fig. 10.

 

Fig. 10 Schematic illustration of the fabrication process flow for FCLED-I. The chip dimensions of FCLED-I are 45 × 45 mil².

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A. Defining the three-dimensional (3D) vias

• 1. Clean the LED wafer (acetone, absolute ethylalcohol (AEA), deionized (DI) water).
• 2. Clean the LED wafer with H₂SO₄: H₂O₂: DI water (5:1:1) under ultrasonic at 60°C for 10 min.
• 3. Pretreat with hexamethyldisilazane (HMDS) for 10 min.
• 4. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 5. Pattern photoresist by exposing to ultraviolet (UV) light in a mask aligner, developing (EPG516, developer) for 60 sec and curing for 25 min at 125°C.
• 6. Expose n-GaN layer to define 3D vias using inductively coupled plasma (ICP) etching with BCl₃/Cl₂ mixture gas (350W ICP power/375 RF power, 60 sccm BCl₃/40 sccm Cl₂, and 5mTorr).
• 7. Remove photoresist by washing in acetone.

B. Defining the current blocking layer (CBL)

• 1. Clean the LED wafer (acetone, AEA, DI water).
• 2. Clean the LED wafer with H₂SO₄: H₂O₂: DI water (5:1:1) under ultrasonic at 60°C for 10 min.
• 3. Deposit 200-nm-thick SiO₂ CBL on p-GaN by plasma enhanced chemical vapor deposition (PECVD).
• 4. Pretreat with HMDS for 5 min.
• 5. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 6. Pattern photoresist by exposing to UV, developing, and curing.
• 7. Etch SiO₂ with buffered oxide etchant (BOE; 130 sec).
• 8. Remove photoresist by washing in acetone.

C. Defining the ITO

• 1. Clean the LED wafer with H₂SO₄: H₂O₂: DI water (5:1:1) under ultrasonic at 60°C for 10 min.
• 2. Clean the LED wafer with HCl: DI water (1:2) for 30 sec.
• 3. Deposit 90-nm-thick ITO onto p-GaN by electron beam evaporation.
• 4. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 5. Pattern photoresist by exposing to UV, developing, and curing.
• 6. Etch ITO by using aqua regia etchant (38°C for 3 min).
• 7. Remove photoresist by washing in acetone.
• 8. Thermal annealing in N₂ ambient at 540°C for 20 min.

D. Defining finger-like n- and p-electrodes

• 1. Spin coat with photoresist (DNR-L300-D1). Soft bake at 100°C for120 sec.
• 2. Pattern photoresist by exposing to UV, developing, and curing.
• 3. Deposit Cr/Al/Ti/Pt/Au (20 nm/100 nm/50 nm/70 nm/1.2 μm) metallization layer onto 3D vias and ITO by electron beam evaporation.
• 4. Lift-off photoresist in acetone to define finger-like n- and p-electrodes on the 3D vias and ITO.

E. Defining DBR

• 1. Sputter two single TiO₂/SiO₂ DBR stacks onto ITO and n- and p-electrodes by ion beam deposition, the first DBR stack contains 7 pairs of TiO₂/SiO₂ (46.4 nm/78.8 nm) and the second DBR stack includes another 7 pairs of TiO₂/SiO₂ (60.4 nm/102.7 nm).
• 2. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 3. Pattern photoresist by exposing to UV, developing, and curing.
• 4. Etch p-electrode holes through DBR by using ICP etching based on CHF₃/Ar/O₂ mixture gas.
• 5. Remove photoresist by washing in acetone.

F. Defining p- and n-Pads

• 1. Spin coat with photoresist (DNR-L300-D1). Soft bake at 100°C for120 sec.
• 2. Pattern photoresist by exposing to UV, developing, and curing.
• 3. Deposit Cr/Al/Ti/Pt/Ti/Pt/Au (20 nm/100 nm/50 nm/50 nm/50 nm/50 nm/1 μm) onto p-electrode holes, 3D vias and DBR.
• 4. Lift-off photoresist in acetone to define p- and n-pads.

A.3. Processing Scheme for FCLED-II

Schematic illustration of these steps appears in Fig. 11.

 

Fig. 11 Schematic illustration of the fabrication process flow for FCLED-II. The chip dimensions of FCLED-II are 45 × 45 mil².

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A. Defining the 3D vias

• 1. Clean the LED wafer (acetone, AEA, DI water).
• 2. Clean the LED wafer with H₂SO₄: H₂O₂: DI water (5:1:1) under ultrasonic at 60°C for 10 min.
• 3. Pretreat with HMDS for 5 min.
• 4. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 5. Pattern photoresist by exposing to UV, developing, and curing.
• 6. Expose n-GaN layer to define 3D vias by ICP etching with BCl₃/Cl₂ mixture gas.
• 7. Remove photoresist by washing in acetone.

B. Defining the highly reflective silver (Ag)-based p-electrodes

• 1. Clean the LED wafer (acetone, AEA, DI water).
• 2. Clean the LED wafer with H₂SO₄: H₂O₂: DI water (5:1:1) under ultrasonic at 60°C for 10 min.
• 3. Pretreat with HMDS for 5 min.
• 4. Spin coat with photoresist (DNR-L300-D1). Soft bake at 100°C for120 sec.
• 5. Pattern photoresist by exposing to UV, developing, and curing.
• 6. Sputter 100-nm-thick Ag onto p-GaN, and then deposit a TiW (120 nm)/Pt (10 nm)/TiW (90 nm)/Pt (10 nm)/TiW (90 nm)/Pt (100 nm) stacks onto Ag.
• 7. Lift-off photoresist in acetone to define highly reflective Ag-based p-electrodes.
• 8. Thermal annealing in N₂ ambient at 600°C for 20 min.

C. Defining finger-like n-electrodes

• 1. Spin coat with photoresist (DNR-L300-D1). Soft bake at 100°C for120 sec.
• 2. Pattern photoresist by exposing to UV, developing, and curing.
• 3. Deposit Cr/Al/Ti/Pt/Au (20 nm/100 nm/50 nm/70 nm/1.2 μm) metallization layer onto 3D vias and Ag/TiW/Pt/TiW/Pt/TiW/Pt stacks.
• 4. Lift-off photoresist in acetone to define finger-like n-electrodes on the 3D vias.

D. Defining DBR insulating layer

• 1. Sputter two single TiO₂/SiO₂ DBR stacks onto Ag/TiW/Pt/TiW/Pt/TiW/Pt stacks and finger-like n-electrodes by ion beam deposition. The first DBR stack contains 7 pairs of TiO₂/SiO₂ (46.4 nm/78.8 nm) and the second DBR stack includes another 7 pairs of TiO₂/SiO₂ (60.4 nm/102.7 nm).
• 2. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 3. Pattern photoresist by exposing to UV, developing, and curing.
• 4. Etch p-electrode holes and 3D vias through DBR by using ICP etching based on CHF₃/Ar/O₂ mixture gas.
• 5. Remove photoresist by washing in acetone.

E. Defining p- and n-pads

• 1. Spin coat with photoresist (DNR-L300-D1). Soft bake at 100°C for120 sec.
• 2. Pattern photoresist by exposing to UV, developing, and curing.
• 3. Deposit Cr/Al/Ti/Pt/Ti/Pt/Au (20 nm/100 nm/50 nm/50 nm/50 nm/50 nm/1 μm) onto p-electrode holes and 3D vias and DBR.
• 4. Lift-off photoresist in acetone to define p- and n-pads.

A.4. Processing Scheme for FCLED-III

Schematic illustration of these steps appears in Fig. 12.

 

Fig. 12 Schematic illustration of the fabrication process flow for FCLED-III. The chip dimensions of FCLED-III are 45 × 45 mil².

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A. Defining the 3D vias

• 1. Clean the LED wafer (acetone, AEA, DI water).
• 2. Clean the LED wafer with H₂SO₄: H₂O₂: DI water (5:1:1) under ultrasonic at 60°C for 10 min.
• 3. Pretreat with HMDS for 5 min.
• 4. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 5. Pattern photoresist by exposing to UV, developing, and curing.
• 6. Expose n-GaN layer to define 3D vias by ICP etching with BCl₃/Cl₂ mixture gas.
• 7. Remove photoresist by washing in acetone.

B. Defining the highly reflective Ag-based p-electrodes

• 1. Clean the LED wafer (acetone, AEA, DI water).
• 2. Clean the LED wafer with H₂SO₄: H₂O₂: DI water (5:1:1) under ultrasonic at 60°C for 10 min.
• 3. Pretreat with HMDS for 5 min.
• 4. Spin coat with photoresist (DNR-L300-D1). Soft bake at 100°C for120 sec.
• 5. Pattern photoresist by exposing to UV, developing, and curing.
• 6. Sputter 100-nm-thick Ag onto p-GaN, and then deposit TiW (120 nm)/Pt (10 nm)/TiW (90 nm)/Pt (10 nm)/TiW (90 nm)/Pt (100 nm) stacks onto Ag.
• 7. Lift-off photoresist in acetone to define highly reflective Ag-based p-electrodes.
• 8. Thermal annealing in N₂ ambient at 600°C for 20 min.

C. Defining DBR insulating layer

• 1. Sputter two single TiO₂/SiO₂ DBR stacks onto Ag/TiW/Pt/TiW/Pt/TiW/Pt stacks by ion beam deposition. The first DBR stack contains 7 pairs of TiO₂/SiO₂ (46.4 nm/78.8 nm) and the second DBR stack includes another 7 pairs of TiO₂/SiO₂ (60.4 nm/102.7 nm).
• 2. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 3. Pattern photoresist by exposing to UV, developing, and curing.
• 4. Etch p-electrode holes and 3D vias through DBR by using ICP etching based on CHF₃/Ar/O₂ mixture gas.
• 5. Remove photoresist by washing in acetone.

D. Defining p- and n-electrodes

• 1. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 2. Pattern photoresist by exposing to UV, developing, and curing.
• 3. Deposit Cr/Al/Ti/Pt/Au (20 nm/100 nm/50 nm/70 nm/1.2 μm) metallization layer onto p-electrode holes and 3D vias and DBR.
• 4. Lift-off photoresist in acetone to define p- and n-electrodes on DBR and p-electrode holes and 3D vias, and an isolation trench was formed to separate n- and p-electrodes.

E. Defining SiO₂ insulating layer

• 1. Deposit 1-μm-thick SiO₂ insulating layer onto Cr/Al/Ti/Pt/Au metallization layer by PECVD.
• 2. Spin coat with photoresist (EPG516, Everlight Chemical). Soft bake at 95°C for 10 min.
• 3. Pattern photoresist by exposing to UV, developing, and curing.
• 4. Etch n-interconnect holes and p-electrode holes through SiO₂ by using ICP etching based on CHF₃/Ar/O₂ mixture gas.
• 5. Remove PR by washing in acetone.

F. Defining p- and n-pads

• 1. Spin coat with photoresist (DNR-L300-D1). Soft bake at 100°C for120 sec.
• 2. Pattern photoresist by exposing to UV, developing, and curing.
• 3. Deposit Cr/Al/Ti/Pt/Ti/Pt/Au (20 nm/100 nm/50 nm/50 nm/50 nm/50 nm/1 μm) onto n-interconnect holes, p-electrode holes and SiO₂ insulating layer.
• 4. Lift-off photoresist in acetone to define p- and n-pads.

A.5. Nanoindentation tests

S. Suresh et al. reported that nanoindentation with a sharp indenter could be utilized for the evaluation of residual stress [42]. This method has also been employed for measuring the residual stress within various materials [43–48]. The effect of residual stress within the specimen on the nanoindentation tests is illustrated in Fig. 13. For a specimen under compressive stress, the depth (H1) will be lower than that from a stress-free specimen (H) at the same load, because the compression stress within the sample can act as an additive load to resist the penetration of the indenter. Contrarily, the depth (H₂) from specimens under tension stress is higher than the depth in reference specimen (F) at the same load, due to the lower resistance to the deformation. Consequently, for load-controlled nanoindentation tests on specimens under different stress states, the maximum depth should follow the relationship H2>H>H1, as illustrated in Fig. 13(d) [42,47–49].

 

Fig. 13 Schematics of the effect of residual stress on nanoindentation tests: (a) The indentation on stress-free specimens; (b) and (c) The effect of compression and tension stress on the nanoindenation tests; (d) The comparison of load-depth curves from nanoindentation tests on specimens under different stress states.

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Therefore, for samples before and after annealing, increase in maximum depth (hmax) indicates rising tension stress. Higher increase is a result of more significant tension stress.

A.6. First-principles calculations

The first principles calculations were carried out using projector-augmented wave (PAW) method based on density functional theory (DFT). The generalized gradient approximation (GGA) in the Perdew-Burke-Ernzerh (PBE) form was taken into account as exchange-correlation energy functional. The plane-wave expansion of the electronic wave function was set to 300 eV energy cutoff. For k-point sampling in calculations of the interfacial structure, 8×8×1 Monkhorst-Pack grid were used. Ag/GaN interface were modelled using the periodic heterostructures formed by a slab of four atomic planes of the Ag(111) metal and a slab of four bilayers of GaN(0001). The overall thickness of the supercell was 25 angstroms. Different interfacial composition was studied by exchanging various Ag atoms to the Ga atoms. Five interfacial composition configurations were considered and corresponding atomic structures of Ag/GaN interface are shown in Fig. 14.

 

Fig. 14 Side view of geometries of Ag(111)/GaN(0001) interface. (a) Non-diffusion condition. (b) One Ag atom diffuses from layer5 to layer4; (c) Two Ag atoms diffuse from layer5 to layer4. (d) One Ag atom diffuses from layer6 to layer4 and from layer5 to layer3. (e) Two Ag atoms diffuse from layer6 to layer4 and from layer5 to layer3. (f) Top view of geometries of Ag(111)/GaN(0001) interface.

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A.7. TFCalc simulation for dielectric DBR

We used the commercial software, TFCalc, to model the design of a conventional single DBR stack consisting of 14 pairs of TiO₂/SiO₂ (46.4 nm/78.8 nm) dielectric layers optimized for central wavelength at 460 nm. In the numerical modeling, the conventional DBR stack is composed of 14 pairs of TiO₂/SiO₂ (46.4 nm/78.8 nm) dielectric layers optimized for a central wavelength at 460 nm. The refractive index of SiO₂ and TiO₂ were set as 1.45 and 2.46, and the polarization of incident wave was set as average polarization (50% s-polarized and 50% p-polarized). Figure 15(a) shows the reflectance of the single DBR stack at different incident angles. We found that the reflectance from a DBR exhibits an angular dependency. As the incident light deviates from normal incidence, the width of the high reflection band is narrowed and blue shifted, as shown in Fig. 15(a). Therefore, some loss of high-angle green and yellow photons will be incurred for the single DBR stack optimized for central wavelength at 460 nm, thereby leading to low reflectance in the green and yellow light wavelength regions. Figure 15(b) shows the reflectance of the single DBR stack optimized for different central wavelength from 460 to 600 nm by altering the thickness of TiO₂/SiO₂ dielectric layers. We noted that that the reflective bandwidth of the single DBR stack redshifts as the thickness of the TiO₂ and SiO₂ increases.

 

Fig. 15 (a) Reflectance of the single DBR stack at different incident angles. (b) Reflectance of the single DBR stack with increasing thickness of TiO₂ and SiO₂ dielectric layers.

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Funding

National Natural Science Foundation of China (U1501241, 51675386, 51775387); National Key R&D Program of China (2017YFB1104900); Hubei Province Science Fund for Distinguished Young Scholars (2018CFA091).

Acknowledgments

We acknowledge the nanofabrication assistance from Center for Nanoscience and Nanotechnology at Wuhan University.

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