1. Introduction

Superconducting nanowire single-photon detectors (SNSPDs) are among the highest-performing photon counters in terms of efficiency, speed, dark counts, and range of wavelength sensitivity. Traditionally, SNSPDs have had the greatest impact in applications that rely on their high timing resolution, including optical communication [1–3], quantum optics [4–8], and lidar [9]. Recently, new applications seek to take advantage of SNSPDs’ ultra-low dark count rates, which can be below $10^{-4}$ counts/s [10], or their sensitivity to mid-infrared wavelengths, where large arrays of time-resolved single-photon detectors are currently lacking [11]. In fields such as dark matter detection [10] and space-based astronomy [12], SNSPDs offer high-efficiency detection of low-flux signals, low intrinsic dark-count rates, and the possibility of gating out false events due to their timing resolution. However, these applications generally require larger arrays than are currently available, both in terms of number of elements and active area. Large SNSPD arrays could additionally be useful for quantum imaging, time-resolved imaging, or lidar applications.

The most mature and straightforward architecture for multi-pixel SNSPD arrays is direct readout, where each pixel has its own readout channel. To date, arrays of 64 pixels have been demonstrated using direct readout [2,13]. As pixel counts increase, direct readout becomes unfeasible due to the increasing heat load of high-speed cables and the limited cooling power of typical cryostats. Several architectures for cryogenic multiplexing of SNSPD arrays have been successfully demonstrated for array sizes up to 64 pixels [14], including row-column multiplexing [15], SFQ readout [16], pulse amplitude multiplexing [17,18], frequency multiplexing [19,20], and time-domain multiplexing [21]. Additionally, a single nanowire element has been used to resolve 590 effective pixels using time-of-flight information [22]. Here, we report on the first kilopixel-scale SNSPD array, achieved using a 32$\times$32 row-column multiplexing architecture.

2. Row-column multiplexing

The row-column multiplexing scheme has previously been described for a $2\times 2$ array [23] and an $8\times 8$ array [15]. In this scheme, $N\times N$ pixels can be read out using $2N$ lines. As shown in Fig. 1(a), each pixel consists of a series resistor with resistance $R_p$ and an SNSPD with inductance $L_p$ and variable hot-spot resistance $R_{hs}$. The hot-spot resistance is 0 $\Omega$ when the nanowire is in its superconducting state. One end of each pixel is connected in parallel to other pixels in the same row, and the other end of each pixel is connected in parallel to other pixels in the same column. Current is sourced to each row, distributed equally among the row’s pixels by the series resistors, and sunk to ground through inductors on each column ($L_C$). Amplifiers on each column and row are used to read out photon detection events. In the specific set-up used here, DC-coupled amplifiers are used; therefore, some of the bias current also flows to ground through the $R_L = 50~\Omega$ resistors on each readout line. When a nanowire detects a photon, it develops a resistance, $R_{hs}$, on the order of 1 k$\Omega$. Current is rapidly diverted from the pixel, leading to voltage pulses of opposite polarities at its row and column readout amplifiers. Coincidences between row and column events are used to determine which of the $N^{2}$ pixels fired.

 

Fig. 1. a) Schematic of the row-column array. b) Optical micrograph of the fabricated array showing the pixel pitch and size. c) Chip-scale layout of the array showing the Nb leads (teal), Au bond pads (yellow), and WSi column inductors (red). d) Fabrication flow, as described in the text. The SNSPD meander and layer thicknesses are not shown to scale.

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One downside of row-column multiplexing is the inability to image multi-photon events. For example, if two photons are detected at the same time by the pixel in row 1, column 3 (r1c3) and the pixel r2c2 (see Fig. 1(a)), simultaneous time tags will be recorded for rows 1 and 2 and for columns 2 and 3. It is clear that two events occurred, but the readout cannot distinguish between the pair of events being produced by r1c3 and r2c2 or by r1c2 and r2c3. In a real system with timing jitter, ambiguity can occur when two events arrive within the timing resolution of the readout, which ultimately limits the maximum count rate of the array. It is worth noting that time-of-flight multiplexing also suffers from the inability to image multi-photon events, but with the relevant multi-photon timescale being the nanowire’s reset time rather than the much shorter jitter timescale.

One particular drawback of row-column multiplexing is current redistribution. When one pixel fires, some current is also redistributed into other pixels in the firing pixel’s row and column, leading to smaller signals at the outputs and variation in a pixel’s current over time. This effect can be reduced by increasing the pixel inductance ($L_p$) or series resistance ($R_p$). Previous analysis has concluded that it is possible to scale this architecture to arrays of at $225 \times 225$ pixels before current redistribution destroys the signal-to-noise of the array [15].

3. Fabrication

An optical micrograph of the fabricated array is shown in Fig. 1(b), and the layout of the array chip is shown in Fig. 1(c). The array covers a $1.6 \times 1.6$ mm square with a 50 µm pixel pitch. The nanowire region in each pixel is $30 \times 30$ µm, resulting in a $36\%$ fill factor and a cumulative $0.96 \times 0.96$ mm photosensitive area. For the same pixel size, it should be possible to increase the fill factor to $60\%$ by reducing width of the Nb wires and by overlapping the series resistors and the row wires on different layers. The fill factor can also be increased by increasing the pixel size or by using a microlens array, which can have fill-factors over $90\%$.

The array was fabricated at the NIST Boulder Microfabrication Facility. Figure 1(d) gives an overview of seven key stages in the fabrication process described below. Fabrication begins with a 3 inch silicon wafer capped with a 150 nm-thick layer of thermally-grown SiO$_2$. Resistors are defined at each pixel by photolithography and sputtering of a Ti / PdAu / Ti trilayer with thicknesses of 2 nm / 35 nm / 2 nm, followed by liftoff in acetone (1). The thickness of the PdAu layer was chosen to provide a resistance of $\sim 8 ~\Omega /\square$ at a temperature of 1 K (the approximate operating temperature of the array), yielding a total resistance at each pixel of $\sim 50~\Omega$. Although the designed resistance at each pixel was $50~\Omega$, the measured average per-pixel resistance in the fabricated array was estimated to be $\sim 200~\Omega$. This resistance was determined based on the slope of the superconducting branch of the I-V curve for a single row scaled by 32 for the number of pixels in the row. The same PdAu layer also defines the contact pads for the rows. Each row contact pad connects in parallel to a single row of 32 resistors through a superconducting Nb wiring layer which is 50 nm thick. This layer is defined by photolithography, sputtering of the Nb layer, and liftoff (2). A 250 nm-thick SiO$_2$ dielectric layer is then deposited by plasma enhanced chemical vapor deposition (PECVD). Vias through the SiO$_2$ dielectric are defined by photolithography and reactive ion etching in a CHF$_3$/O$_2$ plasma (3). These vias connect the SNSPD to the underlying resistor. Vias are also etched over the row contact pads in the same step. The vias are filled with 5 nm Ti / 350 nm Au by photolithography, electron beam evaporation, and liftoff (4). A 50 nm-thick layer of Au is then patterned and deposited using electron beam evaporation and liftoff which serves to connect the SNSPD to the via (5).

The 3 nm-thick WSi layer which is used to fabricate the SNSPD is deposited by cosputtering from separate tungsten and silicon targets at room temperature, followed by a 2 nm-thick amorphous Si cap which serves to protect the WSi from oxidation and subsequent processing steps. A square of WSi having a width and length of 34 µm is then defined across the 50 nm-thick gold contacts at the location of each pixel by photolithography and RIE etching in an SF$_6$ plasma. The same WSi layer is also used to fabricate the column inductors. The wire composing the inductor is 1 µm wide, and has a total length of 74 mm. Electron beam lithography is then performed to define the nanowires using PMMA resist. The nanowires have a width of 180 nm, and the pitch of the meandering wire pattern is 260 nm. The PMMA pattern is transferred into the underlying WSi layer using RIE etching in SF$_6$ (6). The column wires connecting columns of 32 SNSPDs are patterned by sputtering of 50 nm of Nb and liftoff (7). The Nb wiring layer connects directly to the gold contact pad at each SNSPD in a column. Each Nb wire terminates at the WSi column inductor where the two layers are again connected by a 50 nm-thick gold contact pad. The Nb layer also defines the ground plane on the opposite end of the inductor. After patterning, the wafers are diced into 1 cm dies for mounting into standard ceramic J-leaded chip carriers, enabling integration with the existing 64-channel readout electronics.

4. Readout and control electronics

The 64-channel time-tagging readout electronics were developed as part of the ground receiver for NASA’s Deep Space Optical Communications project [3]. The first stage of amplification is provided by DC-coupled amplifiers with a $50~\Omega$ input impedance located at 40 K, with further amplification at room temperature. A 64-channel time-to-digital converter (DotFast/UQDevices model TDM64-800 [24]) converts the SNSPD pulses to time tags with a timing resolution of 15.625 ps and full-width half-maximum (FWHM) timing jitter below 50 ps. The time-to-digital converter (TDC) has a built-in comparator front end capable of triggering on the rising or falling edge of positive or negative signals. Time tags are output over PCI Express (PCIe) at rates of up to 900 MTag/s. Currently, the tags are written to a file for post-processing, but the PCIe output is compatible with real-time analysis using an FPGA.

The rows of the array are biased using four NI-9264 analog voltage output modules, and the bias current is introduced through 10 k$\Omega$ resistors on the 40 K amplifier board. We found that the array became unstable when all rows were biased at the same voltage. The instability is most likely due to the bias current from all detectors in a column approaching or exceeding the switching current of the column’s inductor. The inductor’s switching current was measured to be approximately 90 µA, while the total current produced in each column for the measurements described here reached 140 µA. This instability disappeared when alternating positive and negative voltages were applied to alternating rows, nulling the current through the column inductors. The array was thus biased with a positive voltage applied to all even rows and a negative voltage applied to all odd rows. Because the comparator threshold can either be positive or negative, for each measurement, time tags were first acquired while triggering on negative pulses from the odd rows and positive pulses from all columns and then a second acquisition was taken while triggering on positive pulses from the even rows and negative pulses from all columns. Example positive and negative pulses from the same column are shown in Fig. 2. For future arrays, we plan on designing the column inductors to have a higher switching current or eliminating them entirely. The column inductors allow for readout using AC-coupled amplifiers but are not necessary with the DC-coupled readout scheme used here.

 

Fig. 2. Examples of positive (red) and negative (blue) pulses from one column of the array measured at the TDC input. The array was biased at 3 µA per pixel. Solid lines represent individual pulses and dashed lines are time-averaged pulses. The narrow pulse shape and overshoot are caused by high-pass filtering by the cryogenic amplifiers. The amplifier chain’s gain is greater for positive pulses.

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Once the time tag files are acquired, we can assign row-column time tag pairs to their corresponding pixels. To do this, time tags are read out of the file, and sequential pairs of time tags with a separation less than a specified coincidence window are recorded as events for the pixel from the corresponding row and column. The optimal coincidence window is long enough to capture all intra-event coincidences without also capturing inter-event time tag pairs. The inset of Fig. 3 shows the effects of choosing either a too-short (orange) or too-long (red) coincidence window. Due to varying delays between the channels on chip, in the amplifier boards, and in the TDC’s FPGA, each pixel has a different delay between the time when its row registers an event and the time when its column registers an event. The average row-column differential delays for all pixels of the array fall in a range of $\pm 6$ ns. By calibrating the row and column delays, it is also possible to adjust time stamps by their readout channel’s delay and null out the average row-column time difference. The DotFast TDC has the capability to compensate for time delays between its channels before outputting sorted time tags, but this capability was not used for these measurements; instead, time tags were adjusted during post-processing. As seen in Fig. 3, calibrating the time delays allows for the use of a smaller coincidence window and therefore minimizes over-counting. More sophisticated time tag processing could also be used to identify the most likely event coincidences and ensure that time tags are not double-counted for multiple events. After calibration, the distribution of interarrival times is largely governed by the timing jitter, and so smaller coincidence windows can be used at higher bias currents where the jitter is lower.

 

Fig. 3. Illustration of coincidence times in the row-column multiplexing scheme. The inset shows how the choice of coincidence window can lead to over- or under-counting of events. Vertical lines depict two pairs of time tags, with the first pair corresponding to detection event A and the second pair corresponding to detection event B. The orange and red horizontal bars correspond to two different choices of coincidence window. If the coincidence window is too short (orange), then intra-event coincidences can be missed, and events are under-counted. If the coincidence window is too long (red), then inter-event time tags are falsely registered as events. The two histograms show example distributions of time differences between sequential row-column time tags across the array with the array biased at 3 µA and flood-illuminated with CW light. Row-row and column-column interarrival times have been omitted. Without calibrating the time tags, the interarrival times have a broad distribution primarily due to differential time delays within the TDC, with most interarrivals < 6 ns (purple). After applying calibrated timing offsets to each row and column, the interarrival time distribution is largely limited by the jitter, with most interarrivals < 1.5 ns (blue). Both histograms have a non-zero background that corresponds to the Poisson-distributed inter-event arrival times.

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5. Measurements

The array is operated at a temperature of 730 mK on a He-3 sorption cooler and is illuminated with 1550 nm light using free-space optics. A set of three short-pass filters mounted at the 40 K and 4 K radiation shields blocks room-temperature blackbody radiation while maintaining high transmission at 1550 nm. Optical losses in the filters are estimated to be less than 4%.

5.1 Bias-dependent photoresponse and yield

Figure 4 shows the total count rate vs. bias current for each of the 32 rows under 1550 nm flood illumination. Count rates are calculated for each pixel using calibrated time delays and a 1.5 ns coincidence window, then summed across all pixels in each row. The bias current is calculated as the average current in each pixel assuming uniform current distribution. Four pixels out of the 1024 pixels in the array show no photoresponse at any bias, and two pixels show a much lower photoresponse than their neighbors, corresponding to a baseline yield of 99.4%. As the bias current increases, the array develops more “hot” pixels with elevated count rates, which also decrease the yield of functional pixels. For example, at a bias current of approximately 3  µA, we observe five dead pixels, two suppressed pixels, and two hot pixels, giving an overall yield of 99.1%. At a bias current of approximately 4 µA, we observe nine additional hot pixels, giving an overall yield of 98.2%. The hot pixel behavior is due to relaxation oscillations in the presence of the DC-coupled readout as the pixel’s bias current surpasses its switching current. The switching current could be suppressed for these pixels because of variations in the nanowire thickness or width across the array, variations in the pixel resistor values, or constrictions in the nanowire. Because these hot pixels tend to have similar count rates to their neighbors at lower bias points, constrictions are the most likely cause. As the bias current increases, some of these hot pixels eventually switch to their normal state. For this work, we measured a single array without pre-screening for yield. Higher yields may be achieved by pre-screening candidate arrays with a cryogenic probe station.

 

Fig. 4. Count rate vs. average pixel bias current summed across each of the 32 rows under 1550 nm flood illumination. a) 3-D view of the count rate showing the spatial distribution of efficiency and hot pixels across the array. In general, the hot pixels appear to be evenly distributed spatially, although the two edge rows do contain some of the most constricted pixels. b) 2-D view of the same data in (a). A clear inflection point is visible in the count rate vs. bias curve, indicating that the array approaches saturated internal efficiency. Above 4.3 µA, more than half of the array’s rows are affected by hot pixels, although the overall percentage of hot pixels is much lower.

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As the rows approach saturated internal efficiency, there remains about 10% variation in count rate across the rows. The pixel-to-pixel variation can arise from 1) variation in illumination, 2) variation in bias current due to differences in the on-chip pixel resistors, 3) variation in bias current due to the amplifier board, 4) variation in the comparator’s triggering efficiency due to differences in amplifier noise or gain across the channels or 5) variations in the nanowire fabrication.

5.2 Detection efficiency and imaging capabilities

To measure the system detection efficiency of the array, we imaged a focused laser beam with a known power. Figures 5(a) and (b) show the log-scale count rate of the array under illumination by the laser spot. The image in Fig. 5(a) was taken at a bias current of approximately 3 µA with a calibrated 1.2 ns coincidence window, and the image in Fig. 5(b) was taken at a bias current of approximately 4 µA with a calibrated 0.6 ns coincidence window. The coincidence windows were chosen to collect > 99.5% of counts, based on the measured jitter for each bias current (see Section 5.3). At 3 µA, the median pixel had a dark count rate of 110 cps, and at 4 µA, the median was 215 cps. A 2-D Gaussian fit to the background-subtracted count rate across the array yielded a pixel efficiency of $12\%$ at a bias current of 3 µA, and $23\%$ at a bias current of 4 µA. Combined with the $36\%$ fill factor of the array, the total system detection efficiency is calculated to be $4\%$ at 3 µA and $8\%$ at 4 µA, where we define the system detection efficiency as the percent of photons entering the room-temperature cryostat window that are registered by the array and readout system. The measured pixel efficiency is comparable to that of other WSi SNSPDs without a full optical stack, indicating that the efficiency of the array can be enhanced significantly by embedding the pixels in an optical cavity. The fill factor can also be optimized either through the pixel layout or by using a microlens array.

 

Fig. 5. Imaging capabilities of the array. a, b) Log-scale count rate across the array under illumination with a focused laser beam. a) Approximately 3 µA bias current, adjusted to equalize background counts across the rows. The laser spot photon flux is $8.5\times 10^{6}$ photons/s (ph/s), and the scale is clipped at count rates above $1.6\times 10^{5}$ counts/s (cps). The image represents $2.0\times 10^{6}$ counts gathered over 2.3 s. b) 4 µA bias current, with rows 1 and 32 biased at 0 µA. The laser spot photon flux is 14.9 Mph/s, and the scale is clipped at count rates above $3.3\times 10^{5}$ cps. The image represents $1.8\times 10^{6}$ counts gathered over approximately 0.25 s. At the lower bias, there are fewer hot or dead pixels, and no cross-talk is evident. At the higher bias current, misattributions due to hot pixels are evident in streaks and false hot pixels. The hot pixel with the highest count rate (r13c3) has a count rate of 4.6  Mcps. c) Persistence images as a laser spot is swept across the array to spell out text using a steering mirror and a voltage-controlled attenuator (see Visualization 1). The array bias current is 3  µA.

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At a bias current of 3 µA, five dead pixels and two hot pixels are evident in Fig. 5(a). At the 4  µA bias current, there are nine more hot pixels (count rate > 100 kcps). As seen in Fig. 5(b), the elevated count rates in these pixels’ rows and columns lead to misattribution of an event’s originating pixel, with false hot pixels and streaks appearing at the intersection of rows and columns containing elevated counts originating from either hot pixels or the laser spot. The false pixels are clearly visible in this log-scale image; however, misattributions consist of at most 0.6% of the corresponding hot pixels’ counts. At the low bias current, no misattribution is evident.

As a demonstration of time-dependent imaging using the array, we swept a laser spot across the array to spell out our institutional logos. Persistence images of counts across the array are shown in Fig. 5(c), and movies are available online (see Visualization 1). For these measurements, the array was biased at 3 µA. The NIST movie consists of $5.8 \times 10^{6}$ total counts recorded over 6  seconds, and the JPL movie consists of $4.2 \times 10^{6}$ counts recorded over 5.5 seconds.

5.3 Jitter

Jitter measurements were performed using a 20 MHz mode-locked laser to flood-illuminate the array. Pixel time tags were recorded as the average of the corresponding row and column time tags, and a conservative 10 ns coincidence window was used in the time tag analysis. The resulting timing histograms were fitted with a Gaussian distribution to determine the FWHM timing jitter. For some pixels, it was not possible to obtain a good fit, due either to lack of counts or interference from neighboring hot pixels. Figure 6(a) shows the resulting maps of the FWHM jitter measured for each pixel of the array at bias currents of 3 µA and 4 µA, and Fig. 6(b) shows the same data binned into histograms. The measurements were taken at count rates of approximately 5 kcps per pixel. At the lower bias current, the average jitter was 400 ps, and at the higher bias current, the average jitter was 250 ps. These values are much higher than the < 100 ps jitter of a typical SNSPD and the < 50 ps jitter of the TDC. The high jitter can be attributed both to the pixels’ relatively low bias currents and to current redistribution in the array, as described in Section 2. The current redistribution diverts signal away from the amplifier chain where it can be detected and into other pixels. One effect of this redistribution is to decrease the signal level of the voltage pulse and to make the jitter more susceptible to amplifier noise. For example, in Fig. 6(a), the jitter map for the low bias current shows higher jitter for certain rows and columns, indicating that these channels have a larger noise contribution from their amplifiers. Another effect of current redistribution is to produce fluctuations in the bias current through each pixel, which then add to jitter through variations in pulse height. Future row-column arrays can minimize these effects with further optimization of the readout to decrease the amplifier noise contributions or optimization of the pixel inductance and resistance to improve the signal. The use of a constant fraction discriminator instead of a fixed-threshold comparator can also reduce the jitter that originates from temporal walk associated with varying pulse heights [25].

 

Fig. 6. Jitter measurements. a) Maps of the FWHM jitter measured for each pixel of the array at bias currents of 3 µA (left) and 4 µA (right). b) Histograms of the data in (a) showing the distribution of jitter across the array measured with the array biased at 3 µA (green) and at 4 µA (blue). At the lower bias current, the average pixel jitter was 400 ps, but the jitter distribution is peaked near 365 ps with a long tail towards higher jitter values. At the higher bias current, the average pixel jitter was 250 ps.

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As described in Section 2, the array’s jitter is relevant for avoiding misattribution. If the differential timing delay for each readout channel is calibrated out, then the minimum coincidence window will be limited by jitter. The smaller the coincidence window, the less likely that two events will occur during the coincidence window.

To probe the array’s maximum count rate, we biased either half or a quarter of the rows of the array at 3 µA and applied an increasing optical flux. The whole array was not biased at once in order to avoid the TDC’s maximum count rate of 900 MTags/s. With the efficiency calculated from the totalized count rate across the 8 or 16 biased rows instead of from coincidences, the efficiency showed no degradation up to count rate of 10 Mcps per row and an approximately 10% reduction at 30 Mcps per row. This calculation neglects the effects of misattribution on the maximum count rate. For example, if we assume that the photon arrival times follow a Poissonian distribution, and we use a coincidence window of 1.2 ns, at an average count rate of 960 Mcps across the whole array, approximately 30% of detected photons will arrive within the coincidence window of another photon, leading to misattribution errors for $\sim 15\%$ of the detected events. For a coincidence window of 0.6 ns, misattribution errors decrease to below 6%. However, at higher count rates, there is likely to be more current redistribution through the array and thus higher jitter.

6. Conclusion

In summary, we have fabricated an SNSPD array with 1024 pixels and a $1.6 \times 1.6$ mm area with a row-column multiplexing architecture. Using a 64-channel time-tagging readout, we found that the array has a baseline yield of over 99%, a system detection efficiency of up to 8% at 1550 nm, dark count rates on the order of a few hundred counts/s/pixel, and jitter of 250 - 400 ps FWHM. Compared with state-of-the-art near-IR, free-running Geiger-mode avalanche photodiode arrays of the same format, the proof-of-principle SNSPD array has comparable jitter and lower dark count rates but worse efficiency and uniformity [26–28]. We expect that improvements in efficiency, jitter, dark count rates, and yield are possible with further optimization of this initial design. Our results show that it is feasible to extend the previously-demonstrated row-column multiplexing architecture to kilopixel arrays and to yield SNSPDs over millimeter-scale active areas.