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Abstract
In this paper, we design and fabricate a 32-GS/s 6-bit digital-to-analog convertor (DAC) based on SiGe technology. The DAC uses double sampling technique and segment current steering architecture to achieve high dynamic linearity. A corrector circuit is proposed to suppress the duty cycle error for linearity optimization. The spurious free dynamic range (SFDR) is above 31.5 dBc over the Nyquist bandwidth at the sampling rate of 32-GS/s. A full-rate input interface is integrated to realize data exchange with field-programmable gate array (FPGA). The experimental results show that the net data rate of 50-Gb/s orthogonal frequency division multiplexing (OFDM) signals with non-uniform quantization can be generated by the designed and fabricated DAC. The OFDM signal transmission over 10-km standard single mode fiber (SSMF) with 64-quadrature amplitude modulation (QAM) and 128-QAM formats have been successfully achieved.
© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
High-speed digital-to-analog converters (DACs) are key components in high-speed optical fiber transmission systems. Various high-speed DACs have been reported [1–10]. A digital signal processor (DSP) or field-programmable gate array (FPGA) is used to transmit data for DAC. In order to apply the high-speed DAC in more application areas, it is convenient to communicate the high-speed DAC with FPGA, which is programmable according to different applications [5,10]. It is well known that high-speed input interface is necessary to transmit the signal from FPGA. Series input interface with synchronization evaluation logic unit is implemented for digital input signals [5], but the synchronization process is complicate. Conventional low-voltage differential signaling (LVDS) interface is also proposed for high-speed data transmission [10]. However, the speed of LVDS interface is usually less than 3-Gb/s per channel, which limits speed of the maximum permissible external data feed to the DAC. Therefore, it is desirable to design a high-speed input interface, which can improve the speed of data transmission per channel and implement the fast synchronization.
In this paper, a 32-GS/s 6-bit DAC based on SiGe technology is designed and fabricated, which integrates full-rate data interface running up to 10-Gb/s for data synchronization and descrambling. With full-rate data interface, the DAC can be flexibly interconnected with FPGA. At 32-GS/s sampling rate, the fabricated DAC can achieve the spurious free dynamic range (SFDR) better than 31.5 dBc across the first Nyquist bandwidth. Then, we use the designed and fabricated DAC to generate orthogonal frequency division multiplexing (OFDM) signals with non-uniform quantization. Finally, we transmit the generated OFDM signals over an intensity-modulation direct-detection (IM-DD) link. The experimental results show that the intensity modulated OFDM signals with 64-quadrature amplitude modulation (QAM) and 128-QAM formats can be successfully transmitted over 10-km standard single mode fiber (SSMF) at net data rate of 50-Gb/s. Non-uniform quantization algorithms can bring ~2 dB improvement for the receiver sensitivities.
2. Proposed DAC design
Figure 1 illustrates the diagram of chip block. The chip consists of DAC core, four sets of six-lane data interface, clock distributor and register. The differential input signals are first connected with on-chip 50-ohm resistors, and then pass through the high-speed input interface. The input interface consists of four identical six-lane data interfaces for data synchronization in synchronization mode and data descrambling in operation mode. The clock distributor provides the clock signal for the data interface and the DAC core. An on-chip delay circuit in the clock path to the DAC core is used to compensate the delay mismatch. The main function of convertor is implemented in the DAC core. As shown in Fig. 1, all functions such as synchronization and data transmission are controlled via the register.
2.1. High-speed data interface
In order to obtain a high-speed DAC as a separate chip, the circuit must integrate high-speed interface which supports off-chip synchronization. A synchronization method has been proposed by XOR-combining two adjacent digital input signals which are fed by the same bit sequence in synchronization mode [5]. In this paper, the synchronization is implemented based on pseudo-random binary sequence (PRBS). Figure 2 shows the block diagram of six-lane data interface. The input data is first feed to pre-emphasis amplifier to compensate high frequency loss. A resampling block is then used to align the data with suitable clock which is adjusted by the phase selector block. Finally, the input data is sent to XOR block, where the data is de-scrambled by built-in PRBS with length of 27-1. It is noted that the PRBS with length of 27-1 is produced by a PRBS generator, which is fed to all channels. The state of synchronization can be detected and sent to the register by the XOR and D-type flip flop (DFF) block.
The data interface must be synchronized before data transmission. In case of synchronization, the input bit stream from FPGA is set as PRBS with length of 27-1, which is the same as the built-in PRBS. The incoming PRBS is sampled by 90-degree and XOR operations with the built-in PRBS. When both sequences are synchronized, the output of XOR block remains zero constantly. If the output is not zero, the series of the PRBS in the FPGA requires further adjustment to assure the generated PRBS is aligned with the built-in PRBS. The synchronization process is implemented in all channels until each lane is synchronized. When the synchronization is achieved, the chip can work under two modes: scramble transmission and non-scramble transmission. In case of PRBS scrambled transmission, the input lanes implement XOR operation for the input data and PRBS. In case of non-scramble transmission, the XOR block acts as a buffer.
2.2. DAC core
The architecture of the 6-bit segmented DAC core is depicted in Fig. 3(a). Every two bits of the 24 lanes of series data are decoded from binary to thermometer code in the encoder block. Then the 36 lanes of 8-Gb/s data is resembled by the two stages of 2-1 multiplexers (MUXs) to create 9 lanes of 32-Gb/s data. Figure 3(b) shows one lane of 2-1 MUXs. The data is retimed by the DFF and latch, and then sent to the MUX block. Several ECL buffers which lie between MUXs and current switch array are used to reduce the clock noise and re-synchronize the digital signals. The current switch arrays implement the digital to analog conversion. In order to obtain good linearity performance in such high-speed, the segmented 2-2-2 architecture is proposed based on three identical 2-3 binary to thermometer encoders. The two most significant bits (MSBs), the two middle significant bits and the two least significant bits (LSBs) are respectively decoded into three lines, which drive three equally weighted current switches.
The timing skew may have great effect on the dynamical nonlinearity [11,12]. For the segmented DAC, the input impedance of current switches between segmentations is different, which leads to timing skew. In this circuit, ECL buffer with adjustable delay is placed between MUX and switch, which is used to optimize the timing skew. In order to further optimize the timing skew, we can tune the bias of ECL of the MSBs, the middle two bits and the LSBs separately. The timing skew of digital signals can be less than 0.5 ps by adjusting the delay time in ECL buffers.
2.3. Clock distributor circuit
The clock distributor provides clock for input interface and DAC core. As shown in Fig. 4, a duty cycle correction circuit is applied to reduce the offset of the input clock. The clock stop circuit is used to reset the clock network. Then the clock is feed to frequency divider and sent to a 4-phase clock generator.
For double sampling DAC, duty cycle error may seriously affect the performance of DAC. The error would cause a frequency distortion at FS/2-FIN [13]. As shown in Fig. 4, the timing error can be reduced by a duty cycle corrector. For 32-GS/s DAC, the timing error can be controlled within 100 fs.
2.4. Performance evaluation of DAC
At the same technology node, the SiGe heterojunction bipolar transistor (HBT) demonstrates a much higher cut-off frequency than complementary metal oxide semiconductor (CMOS). SiGe technology combines fast HBT and low power CMOS logic gates into a single chip, which is a good choice for DAC with high-speed data interface. The high-speed data interface and other high-speed circuits can be designed based on HBT, whereas low-speed logic circuits such as register, are designed based on CMOS. In consideration of the cost and actual demand, the DAC is designed and fabricated based on 0.18 um SiGe technology with HBT of 200/200 GHz peak ft/fmax. Figure 5 shows the chip micrograph. The chip area is 2.8 × 3 mm2 including bonding pads. The full-rate data interface lies on both sides occupying nearly half of the area.
The chip test setup is shown in Fig. 6. Considering the power of DAC is high, a heat sink is used to mount the chip. The chip is bonded to the RF test board for test. The Xilinx FPGA board VC7215 is used to produce the data stream for test. The FPGA is connected with the RF test board, which is integrated with the DAC. The reference clock of FPGA transceiver is provided by DAC.
The measured DNL (differential nonlinearity) and INL (integral nonlinearity) of the DAC are shown in Fig. 7(a) and 7(b). The DNL lies between −0.12 and 0.04 LSB. The measured INL is well below 0.11 LSB. The chip demonstrates good static performance. This clearly shows the advantage of the segmented thermometer-coded architecture. Single tone SFDR at 32 GHz sampling frequency is given in Fig. 8, which is all above 31.5 dBc from 100 MHz to Nyquist output frequency. The results show that the DAC has good dynamic linearity performance across the entire Nyquist bandwidth.
Table 1 summarizes a comparison of the DAC performance with similar design of 6-bit resolution. The DAC total power is 5.1 W, and the full-speed data interface consumes approximately 80% of the power.
Table 1. Performance Comparison of 6-bit DAC
3. Non-uniform quantization
For low resolution bit DAC, quantization noise may introduce large quantization noise, which may seriously degrade the system performance. In order to reduce the quantization noise of the generated analog signal, non-uniform quantization is proposed to set the quantization levels based on the Gaussian distribution of the generated analog signals [14,15]. In this case, small-amplitude waveforms will appear much more frequently, which may suffer from less quantization noise, resulting in an effective reduction of overall distortions. Moreover, non-uniform quantization can also reduce the required bandwidth of the system [16].
3.1. A-law quantization
The normalized amplitudes of the A-law quantization are given by the A-law expansion function [15], which can be expressed as:
where is the codebook with uniform quantization. For example, if 3-bit quantization is considered, then y = [-1, −5/7, −3/7, −1/7, 1/7, 3/7, 5/7, 1]. A is the compression parameter in the A-law compression algorithm. When the function of is obtained, the threshold can be determined by averaging the adjacent normalized amplitudes. Finally, the analog signals can be quantized according to the codebook and threshold.3.2. Lloyd quantization
The Lloyd algorithm is another method to determine the codebook and threshold based on minimum mean-square error (MMSE) criterion [17,18]. It first initiates the threshold according to the probability density function (PDF) of the analog signal amplitudes. Then, the amplitudes fall between the thresholds [ti ti + 1] are labeled as level li. The Lloyd algorithm iteratively calculate the mean-square error (MSE) between the quantized and original signals. Both the quantization levels and thresholds are updated during the iteration. The iteration stops when the output level and thresholds converge to achieve the MMSE between original and quantized signals.
4. Experimental setup and results
In our experimental, 5-bit quantization is applied to 64-QAM format, and 6-bit quantization is applied to 64-QAM and 128-QAM formats, respectively. The baseband OFDM signal is generated in MATLAB with 128-point fast Fourier transform (FFT). 48 subcarriers are loaded with data for the three modulation formats, respectively. A length of 4 samples is used as cyclic prefix (CP) to combat with the inter-symbol interference (ISI) induced by bandwidth limitation of optoelectronic devices and channel dispersion.
The experimental setup of the short-haul IM-DD OFDM fiber optical link is shown in Fig. 9. The generated baseband OFDM signals are normalized in Xilinx FPGA board VC7215 and sent to the DAC operating at 30-GS/s for 64-QAM and 25-GS/s for 128-QAM. Therefore, the raw data rate is 65.5-Gb/s and 63.6-Gb/s for 64-QAM and 128-QAM formats, corresponding net data rate of ~50-Gb/s considering the 20% forward error correction (FEC) code.
Fig. 9 Experimental setup of the IM-DD optical OFDM fiber transmission link. Inset (a)-(c): analog signal and the quantized signal based on uniform, A-law and Lloyd quantization schematics. Inset (I)-(III): EVM based on uniform, A-law and Lloyd quantization schematics.
We choose A-law and Lloyd algorithms to quantize the generated OFDM signals. The analog signal and the quantized signal based on the three quantization schemes are shown in the insets (a)-(c) of Fig. 9. The 8 output levels are also described. It is shown that the non-uniform quantization enables waveforms more concentrated in small amplitude regions, which results in lower value of error vector magnitudes (EVM) than uniform quantization scheme, as shown in the insets (I)-(III) of Fig. 9. It is also noted that the threshold of Lloyd is not symmetrical since only a small number of OFDM symbols are used for PDF calculation.
A Mach-Zehnder modulator (MZM) with bandwidth of 30 GHz is driven by an electrical driver with bandwidth of 18 GHz and biased at the linear operating point. The MZM is employed to modulate the CW light emission from a distributed feedback laser at 1550 nm for transformation of electrical field to optical field. After transmission over 10-km standard single mode fiber (SSMF), the power of received signal is controlled by a variable optical attenuator (VOA). The received optical signal is finally launched into a photodiode (PD) with bandwidth of 40 GHz to achieve optical-to-electrical conversion. The converted electrical signals are collected by a real-time Tektronix oscilloscope of DPO73304D operating at 100-GS/s, and processed off-line.
The offline processing at the receiver side is the same as that for conventional OFDM recovery, including time synchronization, FFT demodulation, channel estimation and equalization, de-mapping and decision. For the channel estimation, 10 training symbols are used followed by 400 payload OFDM symbols. About two million bits for each case are collected for BER (bit error rate) calculation.
The BER results versus received power for the three cases with three quantization methods are shown in Fig. 10. It is noted that in the IM-DD OFDM transmission link without EDFA, quantization noise is the major system impairment. For 64-QAM format with 5-bit resolution, the receiver sensitivity is −13 dBm for uniform quantization case at the BER threshold of 2.0 × 10−2. However, the receiver sensitivities in the A-law and Lloyd quantization cases are smaller than −15 dBm, indicating more than 2.0 dB improvement, as shown in Fig. 10(a).
Fig. 10 Experiment results of the IM-DD optical OFDM fiber transmission link with three quantization schemes for (a) 5-bit 64-QAM, (b) 6-bit 64-QAM and (c) 6-bit 128-QAM formats and corresponding constellation formats.
The performance comparisons for 64-QAM and 128-QAM formats are also shown in Fig. 10(b) and 10(c). The A-law and Lloyd quantization can also provide around 2 dB performance improvement for both modulation formats. The constellation points of the recovered signal in the corresponding cases are also shown in the inset. It is noted that, the determined thresholds and codebooks are calculated before the signal transmission. Therefore, only simple look-up table operations are performed in the transmitter to improve the system performance without sacrificing the spectral efficiency.
5. Conclusion
We have designed and fabricated a 32-GS/s 6-bit DAC for optical fiber transmission. The DAC adopts double sampling technique and segment current steering architecture. A full-rate input interface is integrated to realize data exchange with FPGA. A set of ECL buffers and clock corrector circuit are proposed to optimize the dynamic performance. At sampling rate of 32-GS/s, 31.5 dBc SFDR over the Nyquist bandwidth is achieved. Then, we apply the DAC in an IM-DD optical OFDM fiber transmission system. A-law and Lloyd algorithms are chosen to quantize the generated OFDM signals. The experimental results show that the net data rate of 50-Gb/s optical OFDM signals with 64-QAM and 128-QAM formats have been successfully transmitted over 10-km SSMF based on the fabricated DAC and non-uniform quantization. Non-uniform quantization algorithms can bring ~2 dB improvement for the receiver sensitivities.
Funding
Ministry of Science and Technology of the People's Republic of China 863 Program of China (2013AA014101); National Natural Science Foundation of China (61505153), Key Project of R&D Program of Hubei Province (2017AAA046).
Acknowledgments
In the 863 Program of China, 32-GS/s 6-bit ADC is also designed by Dr. Wu Danyu and Dr. Zhou Lei from Institute of Microelectronics of Chinese Academy of Science. The entire work in this paper is implemented in Wuhan Research Institute of Post and Telecommunication. The intellectual property belongs to Wuhan Research Institute of Post and Telecommunication. We would like to thank them for their support.
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