1. Introduction

Optical path switches have been gaining much attentions as key components for fast and energy efficient telecom and datacenter optical networks [1–3]. Free-space-based switches such as MEMS switches [4] have both a larger port-count and lower insertion loss when compared to waveguide-based switches. However, their application may be limited by a switching time of more than 10 milliseconds. Waveguide-based MEMS silicon optical switches [5] have a fast switching time of sub-microseconds, and exhibit low loss and low crosstalk, although their packaging technology has not been well established when compared to CMOS-based silicon photonics switches. On the other hand, the CMOS-based silicon photonics switches have a fast switching time ranging from the order of nanosecond to tens of microseconds, a small footprint due to large difference in refractive index, consume low energy, and can be mass produced (low-cost) due to well established CMOS process lines [6–10]. Recent progress in silicon photonics technologies has enabled the realization of a low-loss 32 × 32 silicon photonics switch with an average fiber-to-fiber loss of 10.8 dB [11] and using the hybrid integration of semiconductor optical amplifiers [12,13] to compensate for the loss in a silicon photonics switch, which paved the way towards silicon photonics switches with low insertion loss and high port count.

To enable a wider application of silicon photonics switches, further miniaturization of the switch is essential because it enables a larger port count and reduces the fabrication cost of the chip due to the increased number of dies obtained from a wafer. Miniaturization also reduces the on-chip loss because the length of the light propagation can also be reduced.

In this paper, we realized the miniaturization by performing the following two steps. First, we studied the minimum width of the TO MZI element switch, which was determined by the distance between two TO heaters. Previously, it has been unclear how densely the TO phase shifters could be arranged without experiencing thermal crosstalk. Therefore, the minimum distance between two TO heaters was investigated in Section 2 by measuring the thermal crosstalk amount using a specially prepared sample. Next, in Section 3, we proposed schemes for optical and electrical wiring to minimize the total length of the switch. Finally, in Section 4, we fabricated and demonstrated an 8 × 8 silicon photonics switch by using the proposed architecture, resulting in 1/23 miniaturization of the PIC part when compared with the previous architecture. We note that the footprint of the electrical pads was not included in the calculation. However, if we used microbumps [14], the electrical pads could be placed within the area of the PIC part and the total chip size could also be very small. We also measured the all-path transmission of the switch and the crosstalk value of one of the worst crosstalk paths, and the conclusions derived can be seen in Section 5.

2. Examination of the minimal distance between TO heaters

2.1 Setup

In the case of TO switches, the minimal distance between TO heaters is determined by the amount of thermal crosstalk. Therefore, we first measured the thermal crosstalk amount with using a specially designed sample and a setup illustrated in Fig. 1(a). Here, we fabricated a silicon photonics chip containing an asymmetric MZI (AMZI) with two heaters, one of which is position-shifted with respect to the center of the waveguide. We prepared samples with various shift amounts ($d_h$) of 0, 10, 20, and 30 μm. Figure 1(b) shows a micrograph of the sample. The heaters were connected to probe pads for the current injection. Figure 1(c) shows the cross-sectional structure of the sample, with a channel-type silicon waveguide of 430-nm width and 220-nm height. The over-clad is TEOS SiO₂ with a thickness of 1.5-μm.

 

Fig. 1 (a) A schematic illustration of the setup used for the examination of the thermal crosstalk. An asymmetric Mach-Zehnder interferometer (AMZI) with a position-shifted heater was prepared. The transmitted spectrum was measured by using an amplified spontaneous emission (ASE) source and an optical spectrum analyzer (OSA). (b) Micrograph of a fabricated sample, with heaters connected to probe pads for current injection. (c) Cross-sectional structure of the sample.

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2.2 Results

Figure 2(a) shows the measured transmittance spectrum of the sample at $d_h$ = 0 μm, where the power injected to the upper heater was varied from 0 to 20 mW. As shown in this figure, the wavelength of the dip shifted toward the shorter wavelength because of the phase shift in the upper phase-shifter arm. The amount of shift is plotted as functions of the heater power in Fig. 2(b), for the cases of $d_h$ = 0, 10, 20, and 30 μm. Dotted lines in Fig. 2(b) indicate the fitted results of the measured points. As shown in this figure, the slope of the shift deceases if $d_h$ becomes large. Figure 2(c) shows the slope of the wavelength shift, which is normalized with respect to that of $d_h$ = 0 μm. The solid curve in Fig. 2(c) shows a Gaussian fit to the measured points. As shown in this fit, the normalized slope at a distance of 15 μm is approximately 3%, which means that the thermal distribution at that point is 3% with respect to the center of the heater.

 

Fig. 2 (a) Measured transmittance spectrum of the sample with $d_h$ = 0 μm where the upper heater is driven with the power of from 0 to 20 mW. (b) Measured amount of wavelength shift as functions of the heater power, where devices with $d_h$ = 0, 10, 20, and 30 μm were used. (c) Normalized slope of the wavelength shift as a function of the position shift of the heater. The solid curve shows the fit to the measured points. The dashed lines show the point of $d_h$ = 15 μm and the slope of 3%.

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Figure 3(a) shows a schematic illustration of the thermal crosstalk caused by the heat distribution of the adjacent heater. It was assumed that the MZI switch is normally in cross state, i.e., the diagonal ports are connected without injecting power to the heaters. By injecting the power to the lower heater of the upper MZI, the switch goes into bar state, i.e., the parallel ports are connected. The phase change in this arm is π. By assuming the distance between adjacent phase shifter arms as 15 μm, the measured thermal distribution showed that the neighboring phase shifter arms experience a phase shift of 0.03π (3%). This phase shift can be compensated by tuning the power if the source of the heat is within the same MZI. However, if this occurs between different MZIs it becomes a thermal crosstalk, as shown by the orange and green lines in Fig. 3(a). By using a transfer matrix method, the amount of the thermal crosstalk was calculated to be −26 dB in this case. We note that, in a path-independent loss (PILOSS) topology, this crosstalk is guided to a terminated idle port in most cases and does not become the overall switch crosstalk. Figure 3(b) depicts a case in which the thermal crosstalk affects overall performance of the switch. The figure shows a PILOSS switch [15] with the path setting for 1−4’, 2−1’, 3−2’, and 4−3′, which shows two paths intersecting at the element switch of row 3 and column 3 where the neighboring switch is bar (ON) state, leading to thermal crosstalk. The expected value of the number of such an element switch in a path was also calculated. Since there were $N$ ON-state element switches randomly distributed around $N^2$ element switches in the PILOSS topology, the probability that an element switch is in the ON-state would be $1/N$. In the worst case, a path contains a maximum of $N-2$ intersections with the other paths at MZIs, and each of the intersections may cause the thermal crosstalk if the neighboring element switch (neighboring heater) is in ON-state. Therefore, the expected number of the element switch in which two paths intersect and the neighboring element switch is in ON-state is $(N-2)/N$, which is less than one for any value of $N$. It was also considered that the thermal crosstalk value of the N × N switch would be expected to be less than −26 dB, which is comparable to the typical intrinsic crosstalk value due to imperfections of the fabrication [16]. Therefore, we conclude that a distance of 15 μm between two adjacent phase shifter arms would be sufficient to be implemented in typical switch configurations such as PILOSS, which greatly reduces the total width of the switch because the previous design had a distance of 100 μm between two heaters.

 

Fig. 3 (a) An illustration of the thermal crosstalk (XT) caused by the nearby heater. (b) A sample case of the thermal crosstalk with the PILOSS switch topology.

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3. Design of high-density TO switch

3.1 Topology

The PILOSS topology is advantageous because of its path-independent loss, and strictly non-blocking and compact characteristics. As an extension to this, we propose a modified topology that provides some potential advantages.

Figure 4(a) shows the PILOSS topology with a 4 × 4 port count, consisting of an N² set of 2 × 2 element switches (which are depicted as S_ij) and (N – 1)² set of waveguide intersections, where N is the port count. It can be assumed that these elements of the PILOSS topology exist on a sidewall of a cylinder in a 3-D space, as indicated in Fig. 4(a) by the red / blue elements on the front/back side of the cylinder [17]. Figure 4(b) shows a structure where the cylinder was projected on the 2-D surface from the long axis. It can be observed that there are no waveguide intersections in Fig. 4(b). This structure is interesting because the loss is strictly path-independent, which is in contrast to Fig. 4(a) where the number of intersections on the path vary (e.g., paths 2−1’, 2−4’, and 2−3′ have 1, 2, and 3 intersections). However, the structure shown in Fig. 4(b) is not suited for miniaturization because the element switches are not arranged in a matrix form. The element switches shown in Fig. 4(b) were rearranged in a matrix form, as shown in Fig. 4(c). As shown in this figure, if vertical coupling methods (such as grating couplers) were to be used to connect with the external fibers, the topology of this switch would have a compact form without any intersections. Figure 4(d) is a different version of Fig. 4(c), which is compatible with standard edge-coupling methods. The structures shown in Figs. 4(c)-4(d) still possess the strictly non-blocking characteristic. Moreover, if the propagation losses of the outer waveguides are negligible, they also possess the property of path-independent loss, i.e., the number of element switches on any paths is the same (which is N).

 

Fig. 4 (a) The PILOSS topology as a 2-D projection of the cylindrical structure. (b) Another way of projecting the cylindrical structure without waveguide intersections. (c) Re-arranged structure of Fig. 4(b). (d) Another structure for edge coupling.

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Even in the modified topology of Fig. 4(d), if the input/output waveguides were placed in the second layer (e.g., SiN waveguides) and if appropriate inter-layer transition structures were used, all of the intersections could be avoided. This enables further miniaturization because the space for the intersections [which is denoted by the x-shaped regions in Fig. 4(a)], and the space for the curved waveguides that connect to the intersections can be omitted, along with the loss of the intersections. We note that in the original topology of Fig. 4(a), adopting two-layer optical wirings to avoid the intersections was difficult because the intersections were placed between element switches and large number of inter-layer transition structures were needed, subsequently leading to a large loss. Recently, we and other research groups have reported on multi-layer optical waveguides using Si and SiN waveguides [18–20]. We also note that this modified topology could be applied in non-duplicate polarization diversity switches, which are described in the Appendix. The amount of the thermal-crosstalk in this modified topology was found to be the same as the original PILOSS topology. In Section 4, this modified topology was realized with only one silicon layer [Fig. 4(d)]. Although the intersections could not be avoided in this case, it was still valid as a proof of concept.

3.2 Electrical multi-layer wiring scheme

Silicon photonics switches typically have a single layer of electrical wiring. However, the single-layer wiring scheme is not suited for miniaturization because the length of the switch is sometimes extended in order to allocate spaces to wire out from the heaters, as schematically shown in Fig. 5(a). The thick and thin blue regions in this figure indicate the ground wirings and current-injection wirings to the heaters, respectively. Placing normal bonding pads for flip-chip bonding would also be difficult when the distance between two TO heaters is 15 μm, implying the necessity of electrical wires to wire out from the switch. More importantly, the space required to wire out from the heaters in the single-layer wiring scheme is almost proportional to the port count N. Therefore, the area required for the wiring will be dominant for the large port-count switches.

 

Fig. 5 (a) An illustration of single-layer wiring scheme for the 8 × 8 switch, where the long axis is extended to insert the wires between two phase shifter groups. (b) An illustration of the proposed multi-layer wiring scheme with three layers, where the length of the switch is limited only by the optical wirings.

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We propose a multi-layer wiring scheme to solve this issue, as shown in Fig. 5(b). In this figure, the red, green, and blue lines show individual layers of the electrical wiring. The red lines are ground. There are four wires on a column of the green or the blue layer, which requires less space than that required for the optical connection. For a general N, the number of layers can be increased to N/4 + 1 to maintain the size required to wire out from the heaters constant. Therefore, it can be considered that the multi-layer wiring scheme can effectively reduce the length of the switch.

4. Device demonstration

4.1 Fabrication

By combining the results obtained in Sections 2 and 3, the miniaturization of the switch both in width and length can be obtained. Therefore, we designed and fabricated an 8 × 8 switch by using the modified PILOSS topology and the three-layer wiring scheme with 15 μm distance between two TO heaters. The switch was designed for a transverse-electric (TE)-like mode. For the waveguide intersections, we used adiabatic-type intersections [21]. We fabricated the sample using laboratory equipment, which included an e-beam lithography system. Starting from a Silicon-On-Insulator (SOI) with a BOX thickness of 3 μm and top silicon thickness of 230 nm, the silicon waveguides were formed using the e-beam lithography system and a dry-etching process. After depositing the TEOS SiO₂ cladding, the heater layer (Pt), 1st, 2nd, and 3rd wiring layers (Au) were fabricated using photolithography processes, where the three Au layers and the two insulating layers (SiO₂) had a thickness of 300 nm and 200 nm, respectively. The heaters and the electrical wires had widths of 5 μm and 10 μm, respectively. A scanning transmission electron microscope (STEM) image of the cross section of the fabricated sample can be seen in Fig. 6(a). It must be noted that the 3rd Au layer had been accidentally peeled off before the STEM measurement. Thus, the sample with three-layer wiring was successfully fabricated.

 

Fig. 6 (a) A STEM image of the cross-section of the fabricated sample. The 3rd Au layer had been accidentally peeled off before the STEM measurement. (b) A micrograph of the fabricated 8 × 8 switch with the modified PILOSS topology and the three-layer wiring scheme. The miniaturization achieved was 1/23 for the PIC part as compared with the previous report.

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Figure 6(b) shows a micrograph of the fabricated 8 × 8 silicon photonics switch with the modified PILOSS topology and the three-layer wiring scheme where the size of the PIC part is 0.3 × 1.2 mm², which was less than 1/23 of the 8 × 8 switch previously reported [16]. The switch chip was bonded on a ceramic package and a high-Δ single mode fiber array was attached on the edge of the chip.

4.2 Switch characterization

We first measured the electrical resistance of the 128 heaters on the chip as shown in Fig. 7. Here, the number of the open circuit heaters (∞ Ω) was plotted on the “0” in the figure. It can be observed that 19 heaters were in open circuit, and 9 heaters (around 30 Ω) were in short circuit. The uneven under layers shown in Fig. 6(a) are believed to have caused these unsuccessful heaters. However, this issue could be resolved by using Cu damascene processes of a standard CMOS process lines. The remaining 100 heaters had an average resistance of 57 Ω. Although there are unsuccessful heaters, a MZI is fully operational if one of the two heaters is not broken. Specifically, 92.2% (59 out of 64 paths) of the paths can be connected by using the successful heaters if they are connected one by one.

 

Fig. 7 A histogram of the measured resistance of the 128 heaters on the chip. In this graph, the number of open circuit heaters (resistance ∞) has been plotted at the “0” position.

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We measured the insertion loss (IL) of all of the path settings and all of the ports (8 × 8 × 8 = 512 points) as shown in Fig. 8. The 8 separate panels correspond to 8 input ports. The horizontal and vertical axes show the target output port setting and the fiber-to-fiber transmittance, respectively. The colored points show the corresponding output ports of the right legend and the gray points indicate lack of connections due to unsuccessful heaters. The measured IL to the target output ports showed values of approximately 15 dB. On the other hand, non-target output ports showed IL values of more than 35 ~40 dB, which indicate that the leakages were suppressed by more than 20 dB.

 

Fig. 8 Measured fiber-to-fiber IL of all the path settings and all the ports of the switch (8 × 8 × 8 = 512 points). The gray points show the paths that could not be connected due to unsuccessful heaters.

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We also analyzed the crosstalk spectrum of one of the worst crosstalk paths. A path setting of 1−5′, 2−6’, 3−8’, 4−7’, 5−1’, 6−2’, 7−3′, and 8−4’ was prepared, in which the leaked light to the 4−7’ path from all of the other paths was measured. In this path setting, the 4−7’ path intersected with other six paths on MZIs, and the thermal crosstalk occurred at the MZI of row 7, column 7. The results are shown in Fig. 9, where the 20 dB crosstalk bandwidth was approximately 8 nm and the 15 dB crosstalk bandwidth was approximately 19 nm. It must be noted that these results are almost the same as our previous report on the PILOSS 8 × 8 switch [16]. Therefore, we consider that the device is successfully working, and the effect of the thermal crosstalk is sufficiently small as expected in Section 2.2.

 

Fig. 9 Measured crosstalk spectrum of one of the worst crosstalk paths with a path setting of 1−5′, 2−6’, 3−8’, 4−7’, 5−1’, 6−2’, 7−3′, and 8−4’.

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4.3 Loss breakdown

This section attempts to show the loss breakdown. We obtained the propagation loss of the silicon waveguide using a cutback method and the value was 2.9 dB/cm for the TE-like mode. We also measured a fiber-to-fiber IL of the “through-chip” waveguide to determine the fiber to chip coupling loss, which was 5.1 dB per a facet. This was calculated as the difference between the measured IL and the calculated propagation loss of the on-chip waveguide. There were also routing waveguides from the switch to the edge of the chip, which causes approximately 2 dB loss depending on the port. Then “switch-part loss” can be roughly calculated as (total IL) 15 dB – 2 × (coupling loss) 5.1 dB – (routing loss) 2 dB $\approx$ 3 dB. Previously, switch-part loss of 4.7 dB was reported on the PILOSS 8 × 8 switch [16]. Therefore, we also achieved low loss. The switch-part loss can be further broken down into three parts: wave guiding loss (without any effect of bends), bending loss, and other excess loss (including the loss at the 3 dB coupler). The estimation of the breakdown of the switch-part loss of the previous and new switches can be seen in Fig. 10. The value of the propagation loss (per centimeter) is almost the same between the previous and the new designs. However, the guiding loss was reduced because the new design has shorter waveguide length due to miniaturization. Moreover, the new design helped in reducing the number (degree) of bends because the elements are close to each other, which also reduced the bending loss. Therefore, the loss reduction here can be considered to be reasonable. Finally, we note that the recently demonstrated 32 × 32 switch had a MZI loss of 0.053 dB [11], which was much smaller than that of the laboratory process (0.31 dB) utilizing a CMOS fab (SCR of AIST) equipped with ArF immersion lithography system. By implementing the same method, the “Guiding loss” and “Other loss” in Fig. 10 can be expected to be further reduced, resulting in a switch-part loss of 0.7 dB.

 

Fig. 10 A detailed breakdown of the switch-part loss. The new design has a smaller number (degree) of bends and shorter waveguide length when compared with the previous design.

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5. Conclusion

In this paper, we proposed and demonstrated the concept of an ultra-compact silicon photonics switch with high-density thermo-optic heaters. We first examined the minimal possible distance between two thermo-optic heaters, and the results of the heat-distribution measurements showed that a distance of 15 μm would be sufficient because a corresponding thermal crosstalk value of −26 dB is acceptable. This finding resulted in the reduction of the width of the switch. We then proposed optical and electrical wiring schemes to keep the length of the switch optically minimized. By combining the above results, we designed an 8 × 8 silicon photonics switch with a footprint of 1.2 × 0.3 mm² for the PIC part, which is less than 1/23 of the previous 8 × 8 switch design. The characterization of all the paths showed that the fiber-to-fiber IL was approximately 15 dB. Due to uneven under layers, 22% of heaters were unsuccessful, which resulted in 7.8% of disabled paths. However, the use of Cu damascene process in a standard CMOS process line would potentially solve this issue. The amount of optical crosstalk in one of the worst crosstalk cases was almost the same as our previous report, showing that the amount of thermal crosstalk was as small as expected. Finally, we performed the loss breakdown and demonstrated that the switch-part loss was reduced when compared with our previous design due to miniaturization. Further loss reduction would be possible by using the ArF immersion lithography system.

Appendix

The modified PILOSS topology presented in Section 3.1 is especially advantageous when used with a non-duplicate polarization diversity switch [22]. Figure 11(a) shows a schematic illustration of a 4 × 4 non-duplicate polarization diversity switch presented in [22]. A polarization splitter rotator (PSR) is used to separate/combine the TE and TM components. In this scheme, there are maximally $7N-3$ intersections on a path. If the loss of an intersection is assumed to be 0.028 dB, the total loss at all the intersections in the case of $N=32$ would be 6.2 dB, which is considerably large. Here, we propose a further modified scheme as shown in Fig. 11(b). Based on the modified topology shown in Fig. 4(d), a second layer has been added denoted by red hyphenated lines in Fig. 11(b). Figures 11 (a)-11(b) have exactly the same connections between element switches. However, the design of Fig. 11(b) does not contain any in-plane intersections. Considering the inter-layer transition loss of less than 0.5 dB [18], a loss reduction of more than 5.2 dB can be expected for the worst-case path of Fig. 11(a) in the new scheme. We note that the elimination of the waveguide intersections can also reduce the crosstalk which has been caused by the backward crosstalk at the intersections in our previous results [23].

 

Fig. 11 (a) A schematic illustration of the 4 × 4 non-duplicate polarization diversity configuration. PSR denotes the polarization splitter rotator. (b) A schematic illustration of the new scheme with double-layer optical waveguides. The black solid lines show Si waveguides and the red hyphenated lines show SiN waveguides.

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Funding

Japan Science and Technology Agency, CREST (JPMJCR15N6).

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