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Abstract
The performance of a photonic functional device in bulk CMOS has been limited by the high propagation loss in polysilicon strip waveguide. Based on the zero-process-change methodology, we successfully reduce the propagation loss of polysilicon waveguide from 112 dB/cm to only 38 dB/cm by solely engineering the waveguide geometry for the first time. Low propagation loss is attributed to a significantly reduced optical overlap factor of 0.09 to bulk polysilicon using subwavelength grating (SWG) waveguide design. These findings prompt us to demonstrate a narrowband SWG-based cladding-modulated Bragg reflector in bulk CMOS, which provides a full-width at half maximum (FWHM) of 1.63 nm, an extinction ratio of 24.5 dB, and a reduced temperature sensitivity of 27.3 pm/°C. Further reducing the FWHM to 0.848 nm is also achieved by decreasing the grating coupling strength. We believe the achievements made in this work validate a promising design path towards practical photonic-electronic applications in bulk CMOS.
© 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
The advent of high index contrast photonics enabled the integration of silicon photonic devices and traditional silicon electronics to provide high bandwidth communication channels with lower energy requirements than electronic links [1]. To date, the majority of silicon photonics is built on custom silicon-on-insulator (SOI) starting wafers with a 3-µm thick buried oxide (BOX) for optical mode confinement and a 220-nm thick crystalline silicon layer for low-loss waveguides [2–4]. This platform is not compatible with the thin-BOX deeply-scaled transistors in foundry SOI-CMOS process. As a result, front-end process modification to enable localized thick BOX on SOI wafers was utilized for monolithic photonic-electronic integration [5]. Alternatively, back-end substrate removal process was conducted to realize photonic circuits with electronics based on zero-process-change SOI-CMOS process [6–8]. However, for leading CMOS technologies below 28-nm transistor nodes, the crystalline silicon layers become too thin (less than 20 nm) to support photonic structures with sufficient optical confinement [9]. SOI-CMOS processes are also cost-prohibitive for many applications and have a limited supply chain for high volume markets. On the other hand, the majority of current microelectronic applications (computer microprocessor, memory, flash storage and so on) with >90% market share is based on bulk CMOS process, which requires the use of bulk silicon wafers with a thin gate oxide and shallow trench isolation (STI) for cost and performance (thermal) reasons. Due to the lack of crystalline silicon layer, it is challenging to realize low-loss photonic devices into bulk CMOS platform. Among all existing layers in commercialized bulk CMOS architecture, polysilicon layer seems to be the only viable material for photonic function implementation. Polysilicon can be easily deposited on almost any material and simultaneously has moderate carrier mobility capable for active photonic devices. Since the polysilicon serves as the transistor gate layers in electronics, the highest resolution of pattern definition with the best photolithography process is applied for the fabrication of this layer. However, optical waveguide made of polysilicon suffers from very high propagation loss due to the optical scattering and absorption at the polycrystalline grain boundaries and surfaces [10–12], thus limiting its practical applications in photonic-electronics integration. Significant works had been conducted to reduce polysilicon waveguide losses from initial reports of >100 dB/cm to 5.3 dB/cm [13–19] but none of the results were based on the fabrication process representative of electronic integration. Significant loss increase was recently demonstrated between as-deposited (∼10 dB/cm) and end-of-line (55 dB/cm) polysilicon waveguides, indicating the high impact of the thermal processing and the local dielectric environment of the electronic process in bulk CMOS [20,21]. The loss of polysilicon waveguide remains high even with the advanced 28-nm CMOS node. To address this issue, intensive investigations were conducted in recent years based on front-end process modifications [9,22–24]. However, introducing additional processes in a matured CMOS fabrication line may require further re-calibration of the electronic devices and modifications to the design rule manual (DRM) for complicated electronic circuits, thus needs further investigations and investments from the foundry. The avoid of process modifications especially at the front-end steps is crucial to provide photonic integration with minimum impact to the overall system. The main roadblock that limits the application of polysilicon photonic devices is its high light propagation loss. Previous studies had reported that optical scattering from the sidewalls and top surfaces has a non-trivial impact on polysilicon waveguide loss, but the dominant loss mechanism is the bulk waveguide loss according to the defect absorption analysis [20]. Therefore, the scaling of optical overlap factor by reducing the waveguide dimension (width or thickness) enables lower waveguide loss from the polysilicon material. This finding prompts us to replace strip waveguide with SWG waveguide design in order to further reduce the optical field overlap to the polysilicon core. SWG waveguide comprises of a periodic arrangement of high and low refractive index materials with a pitch less than one wavelength [25,26]. Bloch modes supported by the periodic arrangement of silicon pillars and cladding material enable lossless lightwave propagation in SWG waveguides. By modifying the pitch, width and duty cycle of the subwavelength grating, the refractive index, dispersion and mode overlap volume can be engineered in SWG waveguides [27]. SWG waveguide on silicon-on-insulator allowed low-loss lightwave propagation (2.1 dB/cm, comparable to the loss of silicon strip waveguide on SOI) [25] and was employed to realize narrowband spectral filters [28–31].
In this study, we successfully reduce the propagation loss of end-of-line polysilicon waveguides to only 38 dB/cm by employing subwavelength grating (SWG) waveguide design without any front-end process modification to the existing bulk CMOS. A SWG-based narrowband Bragg reflector with a high extinction ratio of 24.5 dB is also demonstrated to verify its feasibility for practical applications in bulk CMOS. Though the waveguide loss achieved in this work is still high, it should be acceptable for on-chip optical interconnect applications due to the compact size of the CMOS chips. For example, the distance between the processor and memory bank is within only few millimeters on the system-on-chip dies reported in [8]. Signal transmission in SWG waveguide for this distance introduces a tolerable optical loss of few dBs, which is significantly improved as compared to the loss from polysilicon strip waveguides.
2. Polysilicon SWG waveguide: design and experiments
In this work we aim to integrate photonic waveguide and functional devices in commercialized Nexsys 90-nm general-purpose bulk CMOS architecture provided by Taiwan Semiconductor Manufacturing Company (TSMC). This process has been widely utilized for implementing logic or mixed signal/radio frequency integrated circuits (ICs) in volume production and can be easily accessed from the worldwide IC service providers such as Europractice and MOSIS through multiple project wafer (MPW) runs. The layout of photonic devices in bulk CMOS is conducted by using the standard electronic process design kits (PDKs) in a common VLSI electronics computer-aided design (CAD) environment. This bulk CMOS platform comprises a p-type silicon substrate, lightly-doped n-well, deep n-well, heavily-doped n+/p+ implants, triple gate oxides, thin field oxide, shallow trench isolation, single polysilicon gate layer, and nine metal layers. Figure 1(a) shows schematically that a photonic waveguide can be implemented in the same active polysilicon layer where the transistor gates and local electrical interconnects are defined. To avoid unintentional implantation on polysilicon, doping block layers should be included in the layout to block phosphor/boron implants and metal silicidation. All designs strictly follow the foundry regulations without requiring the modification of front-end process. Since the field oxide below the polysilicon layer is only ∼350 nm in thickness, downward optical leakage happens from the waveguides to the silicon substrate. One possible solution is to create a localized thick BOX by an additional front-end fabrication step as proposed by IBM for silicon photonics integration [32], but the modification of front-end process requires the acceptance by the foundries. Another possible solution is to create a localized air cavity beneath the polysilicon waveguide by a post-micromachining process [21,33] without requiring the front-end process modification. In this work the avoidance of downward optical leakage of the photonic devices is achieved by simply removing the entire silicon substrate using the in-house grinding and alkaline wet etching processes. For numerical investigation, we build a photonic waveguide model consisting of a 150-nm-thick polysilicon core waveguide surrounded by a thin SiO spacer, a thin SiN layer, a 2-µm thick upper oxide cladding, a 350-nm thick field oxide layer beneath the silicon core, and a bottom air cladding. A thin SiN layer typically deposited atop polysilicon gate is used to define the contact vias during transistor fabrication. The addition of this layer strongly affects the waveguide effective index and should be taken into account in the simulation model [34]. Since no shallow etch step is provided for polysilicon definition, a pair of fully-etched grating coupler is employed to guide and couple the light between a lensed single mode fiber and a submicron polysilicon waveguide. The grating coupler has a periodicity of 920 nm and a duty cycle of 0.5 with an incident angle of 15 degrees. A peak coupling efficiency of around −8.5 dB with a 1-dB bandwidth of over 80 nm is observed for TE polarization, as shown in Fig. 1(b). Such a broadband grating coupler is attributed to its smaller waveguide effective index due to the fully-etched geometry over a thin polysilicon layer.
Fig. 1. (a) The schematic diagram of a photonic waveguide implemented on the polysilicon gate of commercialized bulk CMOS platform. (b) Microscopic view of fully-etched grating coupler in bulk CMOS and its measured coupling efficiency over 1500∼1600 nm wavelengths for TE polarization.
Numerical investigations are conducted by a commercial software suite based on three-dimensional finite-difference time-domain (3D-FDTD) method. Figure 2(a) shows the field propagation along polysilicon strip and SWG waveguide, respectively. It clearly reveals that the highest field intensity locates in the core of polysilicon strip waveguide while field propagating in polysilicon SWG waveguide is significantly delocalized. The comparison of their modal profiles and optical overlap factors along the field propagation direction are shown in Fig. 2(b). Optical overlap factor is defined as the fraction of the electrical field intensity confined within the polysilicon material. The optical overlap to the core of polysilicon strip waveguide is fixed at 0.422 along field propagation. Due to the field delocalization in SWG waveguide, the optical overlap factor on the cross-section of polysilicon pillars is 0.18. Since no polysilicon exists between pillars, the optical overlap to polysilicon material is zero. Therefore, the overall optical overlap factor in SWG waveguide is only around 0.09, which is about 4.6 times lower than that in strip waveguide. Considering that bulk material loss dominates the overall propagation loss in polysilicon waveguide, the employment of SWG waveguide design allows us to reduce the field overlap to the lossy polysilicon material and eventually reduces the waveguide loss. To date, most of the SWG-based photonic devices reported in the literature were defined by electron-beam lithography, but deep ultraviolet (DUV) lithography is utilized for pattern definition in bulk CMOS. To our best knowledge this is the first time that SWG-based photonic devices are implemented by end-of-line bulk CMOS process.
Fig. 2. (a) Field propagating along silicon strip and SWG waveguide for TE-like polarization at 1550 nm of wavelength. (b) Comparison of mode profile and optical overlap factor in silicon strip and SWG waveguides.
3. Polysilicon SWG waveguide: loss characterization
For device characterization, a tunable laser with a wide wavelength tuning range (1470 nm to 1620 nm) is utilized to characterize the spectral responses of as-fabricated devices. Polysilicon strip waveguides having a width of 450 nm and a thickness of 150 nm are implemented. Polysilicon SWG waveguides have identical physical parameters as the strip waveguide except for their periodic nature with a pitch of 300 nm and a duty cycle of 0.5. The well-known cut-back method for waveguide loss characterization is based on a comparison of optical transmission through waveguides of different lengths and fitting the length dependence assuming identical coupling conditions [35]. Coupling uncertainty to different devices leads to deviation in extracted waveguide loss, so long waveguides are usually employed in cut-back method to eliminate the impact of the coupling variation. However, in this work the maximum waveguide length is limited by the available chip size (1 mm2) we can access in a MPW run provided from the foundry. We therefore implement polysilicon strip and SWG waveguides with a length of 300, 600, and 900 µm, respectively, to characterize the waveguide loss by cut-back method. After characterizing multiple samples, we noticed around ±0.5 dB variation in fiber-to-fiber optical transmission of the same straight waveguide across the entire wafer. This variation can be attributed to the manual measurement error, the performance variation of the grating coupler, and the loss variation of polysilicon straight waveguide. By assuming identical coupling conditions, such variation leads to non-negligible uncertainty to the extracted waveguide loss.
To avoid this issue, we further conduct cut-back method in a reference ring resonator (named ring cut-back method afterwards) to characterize the loss of SWG waveguide. Firstly, a reference polysilicon ring resonator is built and characterized. Figure 3 show the top Scanning Electron Microscopy (SEM) image of the reference polysilicon ring resonator (450-nm waveguide width, 215-nm gap, and 20-µm radius) and its measured optical transmission spectrum. In order to extract the resonant properties, the optical transmittance $\textrm{T}(\lambda )\; $ is simulated by the transfer function of the all-pass ring resonator. The model can be formulated as [36]:
Fig. 3. (a) Top SEM view of reference polysilicon ring resonator and (b) its measured optical transmission spectrum.
Figure 4(a) shows the schematic diagram of the reference ring resonator with SWG waveguide sections as well as its top microscopic view and zoom-in SEM views. Their measured (solid lines) and fitted (dash lines) optical transmission spectra are shown in Fig. 4(b). According to Fig. 1(a), polysilicon layer is covered by a spacer and a SiN liner and is beneath the multilevel metals and intermediate dielectrics (IMD). As-realized devices are rinsed in a buffer hydrofluoric acid solution in order to expose the polysilicon layer to the air for SEM characterization and surface roughness investigation. Atomic force microscopy characterization shows a root-mean-square roughness of about 2∼3 nm on the top surfaces of polysilicon waveguides. Periodic polysilicon pillars, which were defined with rectangular shape in the layout, become rounded in as-fabricated SWG waveguide due to the smoothing effect of DUV lithography. Optical transition between strip and SWG waveguide is designed with low loss and low interface reflection (around 0.3 dB and −21 dB by 3D-FDTD method) by gradually increasing the corrugation width of sidewall gratings on a strip waveguide until it reaches the resolution limit of 100 nm for the core width. However, due to the profile distortion we observe abrupt interface and rounded SWG geometry in as-fabricated SWG-strip converter, as displayed in Fig. 4(a).
Fig. 4. (a) The schematic diagram, top microscopic view, zoom-in SEM views and (b) measured (solid lines) and fitted (dash lines) optical transmission spectra of as-fabricated polysilicon ring resonators with SWG waveguide sections of different lengths and four SWG-strip converters.
Figure 5(a) shows the loss characterization of polysilicon strip and SWG waveguides by cut-back method at 1550 nm of wavelength. We obtain around 112 and 38 dB/cm propagation loss of polysilicon strip and SWG waveguides, respectively, by linear fitting the length dependence of the optical transmittance. Assuming identical coupling condition, this linear fitting technique allows us to estimate the loss of strip-SWG converter by the optical transmission difference between the strip and SWG waveguides with “equivalent-zero-length” extracted from the intersection point on the vertical axis. In this case the loss per converter is around 0.8 dB at 1550 nm of wavelength. However, measured optical transmission at each sampling point has aforementioned ±0.5 dB coupling variation and is displayed as the error bar in the figure. Taking into account that the longest device in the series is 0.9 mm in length, the upper limit of the error in the loss figure can be estimated to be smaller than ±5.5 dB/cm which can be further reduced by statistical averaging. On the other hand, such a coupling variation can be avoided by alternatively performing ring cut-back method for waveguide loss characterization, as shown in Fig. 5(b). Since the resonant modes from three ring resonators never exist at exactly the same wavelength, we then choose the resonant mode that is closest to the target wavelength (in this case is 1550 nm with less than 1 nm deviation) for the three ring resonators. The round-trip loss of ring resonators is respectively obtained by fitting its spectral response with Eq. (1), as shown in Fig. 4(b). The sums of squared error (SSE) in the fitted data is less than 0.1 with repeatability. We therefore obtain a propagation loss of 38 dB/cm by linear fitting the length dependence of the round-trip loss. The insertion loss of strip-SWG converter is then derived from the difference of round-trip loss between the reference ring resonator and the ring resonator with “equivalent-zero-length” SWG waveguide. The loss per converter is around 0.718 dB. Figure 5(c) compares the waveguide loss spectra of strip and SWG waveguides characterized by the cut-back and ring cut-back method, respectively, across 1500∼1600 nm of wavelength range. Polysilicon strip and SWG waveguides are characterized to have a wavelength-dependent propagation loss of 93∼142 dB/cm and 22∼50 dB/cm by cut-back method. However, we observe some fluctuations on the loss spectrum of both strip and SWG waveguides. Those fluctuations are partially attributed to the back-reflection from the grating couplers that forms an internal Fabry-Perot cavity and generates ripples on the transmission spectrum. For the case of SWG waveguide, there is additional Fabry-Perot cavity formed by the back-reflection of the strip-SWG converters, thus making the transmission spectrum even noisy. On the contrary, the ripples on the transmission spectrum has less impact on the extracted waveguide loss by ring cut-back method. The resultant SWG waveguide loss extracted by ring cut-back method ranges from 29 to 46 dB/cm with less fluctuations across the entire wavelength range of 1500∼1600 nm. Lower waveguide loss happens in longer wavelengths due to its smaller optical overlap factor to the polysilicon core. Similarly, Fig. 5(d) compares the insertion loss spectra of strip-SWG converter extracted by cut-back and ring cut-back method, respectively. We observe much consistent loss values for the data extracted by ring cut-back method. The loss ranges from 0.5 to 1 dB depending on the wavelength. Furthermore, the interface reflection of the strip-SWG converter was characterized to be around −24 dB based on an optical frequency domain reflectometry (OFDR) provided from a commercial optical vector analyzer (OVA5000 from Luna Inc.). This value is lower than the theoretical predicted one and may be attributed to the rounded geometry of as-fabricated SWG waveguides that reduces the interface reflection. Such a low residual reflection from a strip-SWG converter does not introduce asymmetric resonances and could be ignored during the data fitting process.
Fig. 5. (a) Measured optical transmission of straight polysilicon strip and SWG waveguides versus waveguide length at 1550 nm of wavelength (cut-back method). (b) Extracted round-trip loss of as-fabricated polysilicon ring resonators versus SWG waveguide length at 1550 nm of wavelength (ring cut-back method). (c) Extracted waveguide loss spectra of polysilicon strip and SWG waveguides. (d) Extracted optical loss spectra of a strip-SWG converter.
Table 1 compares the propagation loss of end-of-line polysilicon waveguides in bulk CMOS reported in the literatures. The pioneering work by J. S. Orcutt et al. in 2011 demonstrated 55 dB/cm end-of-line propagation loss in 80-nm thick polysilicon waveguides realized by zero-change bulk CMOS process [21]. Since then, several front-end process modifications such as localized crystallization [23], implant amorphization [22], and anneal/planarization [9] were utilized to reduce the end-of-line polysilicon waveguide loss to around 20 dB/cm for both 1550 and 1310 nm of wavelengths. This work demonstrates the loss reduction of 150-nm-thick end-of-line polysilicon waveguides from 112 to 38 dB/cm by simply employing SWG waveguide design without any process modification. To note that a higher propagation loss in 150-nm-thick polysilicon strip waveguide demonstrated in this work, as compared to the one in the prior work (80-nm-thick polysilicon waveguide) [21], is mainly attributed its two times higher optical overlap factor (0.42 versus 0.22 at 1550 nm of wavelength) that results in a higher bulk optical loss. The difference in manufacturing process recipes between two foundries may also play a role in the final polysilicon waveguide loss. Nevertheless, there is limited room for further loss reduction by simply shrinking the waveguide dimension. Reduced optical overlap factor can also be achieved by implementing slot waveguides in bulk CMOS. However, we anticipate to receive less than two-fold of loss reduction in slot waveguides due to its moderate optical overlap factor of 0.2. Experimental results on polysilicon slot waveguides will be reported elsewhere. As a result, we believe the use of SWG waveguide design is the most efficient mean to reduce the optical overlap factor and bulk loss for optical signal transmission in bulk CMOS. Furthermore, the combination of SWG waveguide design with process modifications made by the prior works could further reduce the waveguide loss, thus making the proposed photonic platform even promising for practical applications.
Table 1. Performance comparison of end-of-line polysilicon waveguides in bulk CMOS
4. SWG-based cladding-modulated waveguide Bragg reflector
Waveguide Bragg reflector has become an important building block for applications in optical signal processing, microwave/millimeter wave generation, high-speed optical modulators, sensors, etc. Due to the small waveguide dimensions for single-mode light propagation in a strip silicon waveguide, any small perturbation on the sidewall corrugations can greatly alter the grating coupling strength. This makes it difficult to obtain narrowband responses from strip silicon waveguide gratings. According to the coupled-mode theory, the full-width at half maximum (FWHM) of the spectral response from a grating structure is defined as
Fig. 6. The schematic diagrams, measured optical transmission spectra, and temperature-dependent Bragg wavelengths of (a,b) strip-based and (c,d) SWG-based cladding-modulated waveguide gratings in bulk CMOS.
Figure 7(a) shows the top SEM view of as-fabricated SWG-based CladMod Bragg reflector. Rounded sidewall corrugation profile is attributed to insufficient resolution of DUV lithography [38], which results in a narrower FWHM in the spectral response of as-fabricated Bragg reflector. In the experiments we implement nine Bragg reflectors with different distances between core and cladding waveguides (d = 200, 300, 450, 550, 650, 750, 850, 950, 1050 nm) in order to vary the grating coupling coefficient. To maintain κL product, three total grating lengths of 300, 900, and 1500 µm are employed. Figure 7(b) presents the measured FWHMs and extinction ratios of SWG-based CladMod Bragg reflectors. We achieve 6.6-nm FWHM and 25.2-dB extinction ratio for the device having the smallest core/cladding waveguide distance of d = 200 nm. When the distance is increased to 1050 nm, the resulting Bragg reflector provides the narrowest FWHM of 0.848 nm. A lower extinction ratio of only 11.9 dB in this case is due to the insufficient grating length. On the contrary, larger than 25-dB extinction ratio is achieved for the Bragg reflectors with the smallest waveguide distance in device sets A, B, and C. Such a superior device performance verifies the low-loss propagation in polysilicon SWG waveguide.
Fig. 7. (a) Top SEM view of SWG-based cladding-modulated waveguide gratings and (b) their FWHMs and extinction ratios versus the distance between core and cladding waveguides. There are three device sets A, B, C in this figure representing different lengths L of the waveguide gratings: (A) L = 300 µm, (B) L = 900 µm, and (C) L = 1500 µm.
5. Conclusions
It is still challenging to implement photonic functional devices in commercialized bulk CMOS process due to the high propagation loss of the polysilicon strip waveguide. Despite many attempts to reduce the optical waveguide loss by process modifications, its impact to the existing electronic devices needs further investigations and verifications. In this work we successfully reduce the waveguide loss from 112 dB/cm to only 38 dB/cm by simply employing SWG waveguide design without modifying any in-foundry front-end process. In addition to traditional cut-back method, we also utilize ring cut-back method to characterize the waveguide loss without suffering from the coupling variation during the measurements. Loss reduction in SWG waveguide is attributed to its significantly lower optical overlap factor of 0.09 which leads to lower optical bulk loss. This design concept can be alternatively applied by shrinking the strip waveguide dimension or by employing slot waveguide design. However, we demonstrate that SWG polysilicon waveguide design achieves the lowest optical loss in bulk CMOS due to its lowest achievable optical overlap factor. These findings also prompt us to realize SWG-based CladMod waveguide Bragg reflector having a FWHM of 1.63 nm, an extinction ratio of 24.5 dB, and a reduced temperature sensitivity of 27.3 pm/°C in bulk CMOS. By increasing core/cladding waveguide distance to 1050 nm, a FWHM of 0.848 nm is demonstrated in SWG-based waveguide Bragg reflector. For practical applications, we propose to use low-loss SWG waveguides for relatively long-distance signal transmission such as the optical routes between the memories and CPUs or for implementing photonic devices that require a longer waveguide such as Bragg reflectors. On the contrary, we still prefer to utilize strip waveguides for realizing compact photonic devices such as ring resonators in bulk CMOS to leverage from its compact size. Considering that the CMOS chip is usually with mm2 area, SWG-based photonic devices in bulk CMOS would enable practical applications in optical interconnect and sensors.
Funding
Ministry of Science and Technology, Taiwan (104-2221-E-110-061, 105-2221-E-110-075, 106-2221-E-110-060-MY3).
Acknowledgments
The authors would like to acknowledge chip fabrication support provided by Taiwan Semiconductor Research Institute (TSRI). The authors also acknowledge Mr. Yu-Jen Chen, Ms. Yin-Hsuan Li and Mr. Zhan-Wen Song of National Sun Yat-sen University for the help in device characterization.
Disclosures
The authors declare no conflicts of interest.
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