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Abstract
Optical power splitters are fundamental blocks for photonic integrated circuits. Conventional 3-dB power splitters are either constrained to single-mode regime or to the limited optical bandwidth. In this paper, an alternative design approach is proposed via combined method of topology optimizations on both analog and digital meta-structure. Based on this approach, a dual-mode power splitter is designed on silicon-on-insulator with an ultra-broad bandwidth from 1588 nm - 2033nm and an ultra-compact footprint of only 5.4 µm × 2.88 µm. The minimum feature size is 120 nm which can be compatible with silicon photonic foundry process. The simulated excess loss and crosstalk over this wavelength range for the two lowest TE modes are lower than 0.83 dB and -22 dB, respectively. To the best of our knowledge, this is a record large optical bandwidth for an integrated dual-mode 3-dB power splitter on silicon.
© 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
Wavelength-division multiplexing (WDM) and mode-division multiplexing (MDM) are enabling techniques for parallel data processing and transmission [1–4]. Simultaneously multiplexing on both wavelengths and guiding modes can significantly boost the data capacity for on-chip system. However, conventional devices are either constrained to single-mode regime or have limited optical bandwidth. It is highly desirable to develop functional elements which are transparent to guiding modes and wavelengths. Power splitter is one of the fundamental building blocks in photonic integrated circuits. Dual-mode and three-mode power splitters have been reported on silicon [5–11], which makes it possible for multi-mode photonic integrated circuits [12,13]. But the optical bandwidth of these devices is normally limited to tens of nanometers. Although the three-mode ultra-broadband power splitters have been implemented, they occupy too much on-chip area (exceed 100 micrometers) [14,15]. On the other hand, ultra-broadband power splitters have also been designed with a compact footprint, they are limited to single-mode operation [16–18]. According to our best knowledge, ultra-broadband dual-mode splitter has not been achieved yet and remains a challenge.
In recent years, ultra-compact and high-performance on-chip photonic devices based on pixelated meta-structures have been demonstrated. In general, their structures can be classified into digital and analog meta-structures. The former consists of a limited number of pixels with fabrication-friendly dimensions. But this type of structure is normally optimized by digital topology optimization (DTO) such as brute-force searching methods [19–21] or heuristic methods [22–25] which are not efficient. As the number of pixels or the functionality complexity increases, the optimization process becomes much more challenging for these methods. On the contrary, the analog meta-structure has numerous pixels with much smaller dimension and the corresponding analog topology optimization (ATO) methods have been proposed such as density topology optimization [26,27], objective first method [28,29], level-set method [30,31] and so on. The design freedom of this type of structure is much larger than the digital counterpart, but the irregular device geometry makes the fabrication difficult. There are several improved schemes trying to overcome the dilemma of both ATO and DTO. For example, the method proposed by Wang et al. [32] suffer from the binarization problem and the minimum feature size is limited to 70 nm. In Ref. [33], the adjoint method is used to facilitate the DTO process, but the design freedom of this work is quite limited.
In this paper, we propose an alternative design approach which is analog and digital topology optimization (ADTO) method. Based on this method, we demonstrate the design of a dual-mode 3 dB power splitter on silicon-on-insulator (SOI) with a compact footprint of only 5.4 µm × 2.88 µm. The device has a record large optical bandwidth from 1588 nm - 2033nm. The result demonstrates the possibility and reliability of the proposed ADTO method for efficient design of highly functional and high-performance on-chip photonic devices.
2. ADTO method
The schematic diagram of the proposed splitter is shown in Fig. 1. The device is designed on standard SOI substrate with 220 nm top silicon, 2 µm buried oxide, and 0.6 µm-thick oxide cladding. The splitter consists of an input, two outputs, and multimode waveguide region with a dimension of 5.4 µm × 2.88 µm. The width of the Input, Output-1 and Output-2 waveguides are all chosen to be 1.2 µm, which can support two lowest TE modes. The gap distance between the two output waveguides is set to be 0.48 µm to avoid mode coupling between adjacent waveguides. A device structure is initialized with a random structure which is symmetric with respect to the horizontal central axis. The expected functionality of the device is as follows: when the TE0/TE1 mode source is launched at the input waveguide, the beam will be coupled to two output waveguides with 50:50 split ratio without mode conversions.
Fig. 1. (a) The initial structure diagram of the dual-mode 3 dB power splitter. (b)-(c) The cross-sections of input and output waveguides, respectively.
The transmission efficiency of the splitter can be obtained by the overlapping integral of the actual and standard electric fields of TEm mode (m = 0, 1). TTEm is the transmission efficiency of TEm mode which can be expressed as follows:
In the ATO stage as shown in Fig. 2(a), the optimized region is divided into a 270 × 144 pixel matrix with each pixel dimension of 20 nm × 20 nm. Due to the symmetry of the 3-dB splitter, a 270 × 72 pixel matrix is used to record the dielectric constant of each pixel. The value of each matrix element is between the permittivity silicon ɛSi and the permittivity silicon dioxide ɛSiO2. Based on the adjoint method, the gradients of all pixels can be obtained by only two 3D FDTD simulations for the TE0/TE1 mode which is important to determine the optimization direction [34]. The permittivity will be updated in each iteration according to the L-BFGS-B method [35] and the pixel gradient. By this process, the permittivity of each pixel is optimized which results in an intermediate structure with continuous permittivity distribution. Then, the Heaviside filter is used to binarize the permittivity of each pixel [36] and the analog-topology (AT) structure is obtained. Different from typical ATO method [26–31], no constraint on the minimum feature size and smooth the edges is required at this point. Instead, we applied a DTO method to solve the fabrication constraints.
During the DTO stage as shown in Fig. 2(b), the pixel sizes in the optimized region will be enlarged to meet the fabrication requirements. Here, the size of each pixel is chosen to be 120 nm × 120 nm, which is fabrication-friendly in the silicon photonic foundry process. As shown by the zoom-up detail of the partial region in Fig. 2(a), the large pixel will be fully filled with either silicon or oxide. By examing the corresponding FOM defined as FOM-Si or FOM-SiO2, the structure of max(FOM-Si, FOM-SiO2) will be preserved. When the material properties of all pixels are determined, the structure of the optimized region will be transformed into the digital-topology (DT) structure with large pixel dimension. Although the DT structure can be easily fabricated due to the expansion of pixel size, this conversion process results in a slight degradation in device performance. For this case, the DBS method [19–21] is applied to the DT structure which helps to further improve the performance of the device and the digital-optimized (DO) structure is obtained. Based on an 8-core desktop computer (Intel Core i7-9700 K), the optimization time of ADTO method is close to 72 hours.
3. Results and discussions
The optical fields of the AT structure, the DT structure and the DO structure are calculated at 2000nm wavelength in Fig. 3. As shown in Fig. 3(a)-(f), the TE0/TE1 mode launched from the input waveguide is divided into several beams by pixel nanoholes in the optimized region. However, at each output waveguide, these beams are refocused and converted to TE0/TE1 mode with negligible mode conversion. Since the device is a symmetric structure, 50:50 split ratio can be achieved for both TE0 and TE1 modes. For the AT structure, the DT structure and the DO structure, their transmission spectra at Output-1 waveguide are plotted in Fig. 4(a)-(c). Overall, the transmission curves of the devices are very flat over the optimized wavelength range. According to the simulation results of Fig. 4(a), the excess loss (EL) and crosstalk (CT) of the AT structure are < 0.36 dB and −19.6 dB for both TE0 and TE1 modes from 1550 nm - 2100 nm wavelength. Though low ELs and low CTs are achieved, this structure is difficult to fabricate. As shown in Fig. 4(b), the EL and the CT of the DT structure are increased to 1.0 dB and −14.9 dB from 1665 nm - 2050nm wavelength. At this point, the minimum feature size of each pixel is 120 nm, which can be easily achieved by standard silicon photonic process. However, the enlarged pixels significantly deteriorate the device performances. To cope with this case, the DBS method [19–21] is applied to the DT structure and the DO structure is obtained which is final optimized structure. For this structure, the ELs of TE0 and TE1 modes are both < 0.83 dB from 1588 nm −2033nm wavelength in Fig. 4(c). Their CTs are < −22 dB and −23 dB, respectively.
Fig. 3. (a)-(c) The simulated optical fields of Hz for TE0, (d)-(f) for TE1 at 2 µm wavelength for the AT structure, the DT structure and the DO structure, respectively.
Fig. 4. (a)-(c) The transmission spectra of the AT structure, the DT structure, the DO structure, respectively. (d) The corresponding transmission spectra of the optimization results of DBS method.
It should be noted that the CT level is not constrained in the FOM optimization since very low CTs have been obtained for the digital-optimized structure. By constraining the CT level in the optimization process, the device performance can be further improved. Of course, with smaller pixels, the performance of the device will be better. Our simulation results show that when the minimum feature size is reduced to 100 nm, ELs of both TE0 and TE1 modes will decrease by around 0.15 dB in the same wavelength range. It is worth mentioning that the minimum feature size of the ADTO method can be flexibly adjusted according to the needs of the designer. Due to the strong birefringence of the widely used silicon waveguide geometry, there is a huge difference in the effective refractive index between the TE mode and the TM mode. Therefore, the device of this paper cannot work well under the TM mode. Of course, a TM-mode splitter can be designed and optimized by redefining the expression of FOM.
The DBS method is a brute force search method and modifies only a limited number of parameters in each iteration. To demonstrate the reliability of our method, the conventional DBS method are applied to the same initial structure and FOM expression for optimization. When the optimization time reaches 110 hours, DBS method gets stuck in a local optimum and the corresponding transmission spectrum of the device is shown in Fig. 4(d). For both TE0 and TE1 modes, ELs and CTs of the device are less than 1.5 dB and −16.1 dB in the wavelength range of 1628 nm – 1881nm, respectively. Of course, by modifying the expression of the FOM and the initial structure many times, the DBS method may be able to optimize the device with better performance. However, obviously this way greatly increases the time cost. Compared with the former, the ADTO method search the parameter space more efficiently. In the ATO stage, the ADTO method only needs 4 simulations in the to determine the optimization direction of all pixels in this paper. Overall, the ADTO method obtains better results in only 2/3 time of the DBS method in this paper. Compared with typical ATO methods [26–31], ADTO method sacrifices the freedom of the optimized area. However, there is no irregular topological shape in the structure optimized by the ADTO method. Based on a standard silicon photonic platform, each pixel of the optimized region can be easily fabricated.
Due to the fabrication imperfection, there may be deviation between the actual pixel size and the target dimension. Here, the fabrication tolerance is studied by numerically calculating the transmission under different pixel sizes. Figure 5(a) and (b) show the transmission spectra corresponding to the pixel size with ±10 nm for TE0 and TE1 modes. The transmission efficiency of both modes drops slightly due to fabrication errors. However, the device can still maintain low ELs (< 1.3 dB) at a bandwidth of 425 nm (1608 nm – 2033nm) for both modes. Compared with the ELs, the CTs of the device is more sensitive to the variation of pixel size. But they are still < −15.4 dB in the same wavelength range. In practice, the oxide of the upper cladding may not completely fill the nanohole gap, as shown by the inset of Fig. 5(c). This effect is simulated considering different air gaps thickness (30 nm and 60 nm), as shown in Fig. 5(c) and 5(d). It can be seen that this effect has negligible impact on the device performance within the wavelength range from 1550 nm–2050 nm. It is interesting to find a spectral dip on the curves in Fig. 5, which is possibly due to some resonant features in the device.
Fig. 5. (a)-(b) The Output-1 transmission spectra of TE0 and TE1 modes with ±10 nm variations of the pixel dimension. (c)-(d) Transmission spectra corresponding to air gaps with different thicknesses (30 nm and 60 nm).
To better compare the device performance of this work with previous research, Table 1 is a brief summary for several typical dual-mode 3-dB power splitters. It can be seen that the optical bandwidth of most devices is limited to tens of nanometers. While several broadband devices have been demonstrated, their footprints are not compact enough. By introducing the ADTO method in this work, ultra-compact dual-mode splitter with a record bandwidth exceeding 445 nm is achieved. The footprint of the device is very compact, and the ELs and CTs are also maintained at a low level. Additionally, by choosing a suitable initial structure, increasing the optimization time and the number of pixels, the performance of the device can be further improved.
Table 1. The comparison of the dual-mode 3-dB power splitter.
4. Conclusions
In summary, this paper proposes an ADTO method which benefits from the advantages of both ATO and DTO. This method has been applied to the design a dual-mode 3-dB power splitter with an ultra-broad bandwidth of 445 nm and an ultra-compact footprint of only 2.88 µm × 5.4 µm. To the best of our knowledge, this is a record large optical bandwidth for an integrated dual-mode 3-dB power splitter on silicon. This work shows the high efficiency and reliability of the proposed ADTO method which overcome the pixel dimension constraints for conventional ATO. With variations of the pixel size, the device shows a good fabrication tolerance. More importantly, this method can be extended to design of many other on-chip optical devices.
Funding
National Natural Science Foundation of China (61875049, U21A20454); Science, Technology and Innovation Commission of Shenzhen Municipality (JCYJ20180507183418012, RCYX20210609103707009); Natural Science Foundation of Guangdong Province for Distinguished Young Scholars (2022B1515020057).
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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