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Abstract
In this paper, we demonstrate a novel hybrid 3C-silicon carbide-lithium niobate (3C-SiC-LN) platform for passive and active integrated nanophotonic devices enabled through wafer bonding. These devices are fabricated by etching the SiC layer, with the hybrid optical mode power distributed between SiC and LN layers through a taper design. We present a racetrack resonator-based electro-optic (EO) phase shifter where the resonator is fabricated in SiC while using LN for EO-effect (r33≈ 27 pm/V). The proposed phase shifter demonstrates efficient resonance wavelength tuning with low voltage-length product (Vπ.Lπ ≈ 2.18 V cm) using the EO effect of LN. This hybrid SiC-LN platform would enable high-speed, low-power, and miniaturized photonic devices (e.g., modulators, switches, filters) operable over a broad range of wavelengths (visible to infrared) with applications in both classical and quantum nanophotonics.
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1. Introduction
Integrated photonic material portfolio has been recently extended to the likes of silicon carbide (SiC) and lithium niobate (LN) owing to their unique material properties for both classical and quantum photonics. SiC has a broad transparency range (wavelength: 0.37-5.6 µm) and exhibits a wide range of nonlinear optical effects [1–4]. SiC exists predominantly in three polytypes: 3C (cubic), 4 H and 6 H (hexagonal). 4H-SiC is available in thick bulk crystalline form and is converted into 4H-SiC-on-insulator (4H-SiCOI) using ion-implantation, bonding, and etching to form a thin (thickness ∼ 600 nm) SiC layer to enable photonic device fabrication [5]. Alternately, 4H-SiCOI prepared from oxide-fusion bonding and rigorous polishing (to thin down the thick SiC layer to the desired thickness for device operation) has been widely used for microelectromechanical systems (MEMS) [6,7]. A similar approach [8] adopted for photonics, avoids the crystal-damage arising from ion-implantation thereby enabling high-quality resonators [9] and photonic crystal cavities [10] for nonlinear applications. Amongst the other SiC polytypes, the 3C form can be epitaxially deposited on silicon (Si) wafers using a combination of carbonization and epitaxy [11], thereby enabling thin film growth, batch processing, and considerably less-expensive and high-yield production unlike its crystalline counterparts (4 H, 6 H). Initial fabrications on 3C-SiC are based on Si-undercut architectures with the demonstrations of disk resonators [12]. However, the major challenges with this approach are the lack of mechanical stability and the presence of defects at the 3C-SiC/Si interface layer contributing to optical loss. Further development of thin-film 3C-SiCOI using bonding techniques solved this problem through polishing-off the defect layer, and henceforth enabling high-quality-factor (high-Q) resonators [13], electro-optic phase shifters and modulators (r41≈ 2.6 pm/V) [14,15], single-photon detectors [16] and defect-based quantum emitters [17]. On the other hand, LN has been the standard material for bulk electro-optic (EO) modulators due to its strong EO effect (r33≈ 27 pm/V), where waveguides are patterned using diffusion techniques [18]. In addition, LN is an excellent candidate in nonlinear photonics for applications like wavelength conversion, optical frequency combs etc. due it its high third order nonlinearity (n2= 2 × 10−19 m2/W) [19]. With the development of thin-film LN-on-insulator (LNOI), wafer-scale fabrication of LN has been demonstrated [20] with physical etching techniques. This is because the standard CMOS precursors used for etching Si or silicon nitride (SiN), like the fluorinated gases, lead to lithium fluoride residues, which contribute to optical loss [21]. However, the re-deposition of LN during the physical etching needs to be carefully controlled to avoid optical loss. Such redeposition is undesirable in standard large-scale CMOS foundries due to contaminations where traditional dry and wet etch procedures are implemented. Alternatively, hybrid material platforms have been proposed to circumvent the LN etching by bonding or depositing a conventional CMOS-compatible photonic material like Si or SiN. For example, a hybrid Si-LN platform [22,23] makes use of the EO effect in LN and waveguiding in Si. A similar approach has been demonstrated in a hybrid SiN-LN, with the inclusion of SiN, through chemical vapor deposition (CVD) [24]. More recently, polymer waveguides with low-refractive index (∼ 1.54) are integrated on LN for the demonstration of bound states in the continuum [25]. These hybrid material platforms provide compact devices due to high aspect ratio-etching on Si/SiN, which is otherwise difficult to achieve in the physical etching process of LN. More recently, diamond-like-carbon material is proposed for etching LN that can achieve fully etched devices with higher aspect ratios [26]. However, this process also entails an additional deposition of SiN as an intermediate mask, not making it any more efficient compared to a SiN-LN heterogeneously integrated hybrid platform. While SiN provides a wider transparency range (wavelengths: 0.47-6.7 µm) compared to Si, the material stress makes the heterogenous integration difficult. Furthermore, its lower-refractive index (∼2.00 at 1550 nm wavelength) leads to less flexibility in device engineering, large device footprints, and inefficient grating couplers on a hybrid SiN-LN platform due to low-index contrast between SiN and LN. On the other hand, the high absorption loss of Si at lower wavelengths (e.g., 400-1000 nm) prevents it use in this hybrid platform for wideband operation, despite the high index of Si. This makes SiC an excellent candidate for realization of the hybrid platform with LN. In addition to having a wide transparency range, SiC also exhibits higher refractive index (∼ 2.57 at 1550 nm wavelength) enabling efficient grating couplers while adhering to CMOS compatible device fabrication. The integration of SiC with LN will be advantageous for various reasons. For example, one can envision photonic devices fabricated in SiC layer making use of its higher refractive index for compactness and the broad wavelength of operation, while using LN for high-speed modulation (EO-effect), and wavelength conversion (four-wave mixing). In addition, quantum photonic devices such as emitters and detectors can be patterned on SiC layer with visible to infra-red wavelength conversion enabled through LN layer. Recently, amorphous-SiC (a-SiC) enabled by CVD on oxide substrates [27] has been investigated, and when deposited at low temperatures [28], it could potentially enable the CMOS compatible co-integration of SiC with other unique photonic materials like SiN. However, CVD-based integration of SiC requires further investigation into the stress control caused due to the large coefficient-of-thermal expansion (CTE) mismatch between SiC and LN.
Here, we demonstrate, for the first time, a hybrid 3C-SiC-LN platform where devices are etched in the SiC layer. The first known demonstration of bonding between SiC and LN was reported in Ref. [29] for acoustic filters, although without a device demonstration. Here, we demonstrate, for the first time, the hybrid SiC-LN photonic platform through wafer bonding with the demonstration of fundamental passive (waveguides and resonators) and active (an EO phase shifter) photonic devices.
2. Hybrid SiC-LN integrated photonic platform
2.1 Bonding and thin-film SiC processing
We begin the process with a 4” 3C-SiC and an X-cut LNOI wafer. The 3C-SiC (from NovaSiCTM) is formed by epitaxial deposition of a 2 µm-thick layer of SiC over a 510 µm-thick Si substrate followed by a chemical-mechanical-polish (CMP) step. The thin-film LN wafer (from NANOLNTM) consists of a ∼ 270 nm-thick X-cut LN layer on a 4.7 µm buried-silicon oxide (SiO2) layer over a Si substrate (thickness ∼ 525 µm). First, these wafers are thoroughly cleaned using the standard SC-1 (5:1:1 volume ratio of H2O, NH4OH, and H2O2), and SC-2 (5:1:1 volume ratio of H2O, HCl, and H2O2) solutions, followed by the deposition of a 45 nm-thick SiO2 layer through atomic layer deposition (ALD).
The process flow for the wafer bonding is illustrated in Fig. 1. We perform a direct fusion bonding of the SiC and LNOI wafers, with the thin interface oxide where the hydrophilic bonds are created. Typically, these bonds are strengthened during the high-temperature annealing process. However, the CTE values for SiC (2.7 × 10−6 K-1) and LN (13.4 × 10−6 K-1 along the X and Y axes) are widely different even at room temperature. This difference aggravates at higher temperatures and leads to wafer cracking due to thermal stress. Stronger surface activation could enable low-temperature bonding without compromising the bond strength. In our approach, we treat the wafers with de-ionized water before placing them in a chamber with high vacuum under nitrogen plasma to increase the hydrophilicity of the wafer surfaces [30]. The AFM measurements for the SiC and LNOI wafers before bonding are shown in Figs. 2(a) and (b), respectively. We can see that the wafer surfaces prior to bonding are smooth with root-mean-squared (RMS) roughness (σ) < 1 nm. After activation, the wafers are pre-bonded at room temperature under a force of 2 kN followed by annealing at a temperature of 100 oC over 20 hours to increase the bond strength. The bonded wafer pair is cleaved into four quarters (Fig. 2(c)), and the post-processed quarter is depicted in Fig. 2(d) showing the bonded 3C-SiC film over LN. This die is further processed by removing the Si handle layer and CMP to thin down the SiC film to 280 nm, and the final cleaved die is shown in Fig. 2(e).
Fig. 2. The three-dimensional (3D) AFM images of the (a) SiC wafer (σ = 0.349 nm), (b) LNOI wafer (σ = 0.279 nm) before bonding, (c) the bonded quarters cleaved from the bonded pair, (d) the bonded SiC film on LN after the Si-handle removal, and (e) the final polished SiC-LN bonded die.
The Si handle removal during post-processing consists of dry etching in SF6 (sulfur hexafluoride) plasma, followed by wet etching in a 45% KOH (potassium hydroxide) solution for several hours. The surface of the SiC film after the Si-removal contains residues that lead to a rough surface as seen from the AFM measurement shown in Fig. 3(a). This final surface is polished-off in a chemical-mechanical-polishing (CMP) step. As shown in Fig. 3(b), the surface roughness is considerably improved after CMP, which removes the surface residues and the defects at the SiC/Si layer. The cross-sections of the bonded samples after Si-handle removal and after further CMP are depicted in the scanning-electron-microscopy (SEM) images of Figs. 3(c) and 3(d), respectively.
Fig. 3. The AFM measurements of the (a) SiC-bonded layer on LN after the Si-handle removal (σ = 0.884 nm), and (b) after CMP (σ = 0.356 nm). (c, d) The cross-section SEM images of the bonded sample (c) after Si-handle removal (showing a 1.84 µm-thick SiC on the LN layer, and (d) after CMP (showing a final 280 nm-thick SiC film bonded on the LN layer). BOX: Buried-oxide layer.
2.2 Fabrication and characterization of the photonic devices in the 3C-SiC layer
All devices in our platform are fabricated in the SiC layer with the optical mode distributed between the SiC and LN layers. The SiC film thickness is chosen to enable the key performance features like the optical mode power distribution between the SiC and LN layers. The initial thickness of the SiC layer is ≈ 2.0 µm, which is further thinned down using CMP and blanket SiC etching to get rid of defects and enable further device fabrication. The final SiC thickness after CMP is measured to be 280 nm with a variation of ± 20 nm. More details of the thinning approach and challenges are discussed in Supplement 1. This is not necessarily the optimal thickness for all device engineering, but we found it to be practically feasible, given the controllability of our overall thinning method. The fabrication process flow for the fabrication of devices in 3C-SiC using electron-beam lithography and dry etching was developed and optimized by our group as described in Ref. [13]. The same processes are used in this work, and they are not repeated here for brevity. No etching of the LN layer is performed, and a variety of waveguides, grating couplers (GCs), and resonators are fabricated as fundamental devices by etching SiC.
First, we performed Lumerical simulations to arrive at the optimal waveguide dimensions to support a single mode operation while considering the film thickness variations (as waveguide height). We selected the width of the waveguide to be ∼ 900 nm to provide single-mode operation and to maintain relative power distribution between SiC and LN layers. For the resonator, the bend radius is chosen to accommodate low bend loss (see Supplement 1 for details). Note that this number might change through a rigorous multi-scale optimization of the overall device in future, but it is a good choice for an initial demonstration. The waveguide width also influences the mode distribution in the SiC and LN layers. Figure 4(a) shows the confinement (% of electric field intensity in LN) distribution map of the fundamental transverse-electric (TE) mode with electric field in the plane of the waveguide, for different waveguide dimensions. To couple the light into and out of the integrated photonic chip, multiple efficient apodized grating GCs (Fig. 4(b)) are designed considering the process and SiC thickness variations [31]. The simulated transmission spectra for different GCs are shown in Fig. 4(c), which indicate high transmission efficiency up to 50% or above thereby ensuring significant fiber-grating optical coupling after device fabrication. Figure 4(d) shows the apodization of tooth width and pitch for one of the GCs.
Fig. 4. (a) Variation of the electric field intensity distribution % in LN layer (confinement factor) for the fundamental TE mode for different waveguide heights and widths (highlighted points show the dimensions of the waveguides used in the racetrack resonators), (b) SEM image of a fabricated GC, (c) simulated transmission/coupling efficiency curves of different apodized GCs with a fiber-coupling angle of 3o), and (d) apodization tooth widths and pitches for the grating coupler highlighted in the box in (c).
Figure 5(a) shows a racetrack resonator with input/output GCs which is further integrated with electrodes. On these devices, we observed a side wall angle of 65o (Fig. 5(b)) with smooth sidewalls (Fig. 5(c)). The metal electrodes are fabricated for the application of the DC electric field to the LN layer for active (EO) tuning of the device response. For the electrode-fabrication, we spin-coat a 770 nm-thick layer of PMMA (A6) as the electron-beam (e-beam) resist, patterned by electron-beam lithography. This is followed by the development, metal deposition (300 nm gold (Au) /20 nm of titanium (Ti)) using e-beam evaporation and a final lift-off in acetone to form the electrodes. characterized using the experimental set up shown in Fig. 5(d) with input-output cleaved fibers for light coupling into the gratings. The DC probes are arranged to supply the DC voltage to the fabricated Au electrodes.
Fig. 5. (a) The microscopic image of the fabricated racetrack resonator with input-output GCs, the SEM images of (b) the waveguide cross-section showing a side wall angle at 65o, (c) bend portion of the racetrack, and (d) the characterization setup with input-output fibers and DC probes with wire connections.
3. Electro-optic phase shifter design and discussion
A key factor in selecting the width of the waveguide is the distribution of the mode energy between the SiC and LN layers. To maximize the EO-effect, the optical mode should interact with the electric field in LN layer where the EO-effect occurs, while maintaining the waveguiding provided by the SiC layer. Figures 6(a) and 6(b) show the electric-field profiles of the fundamental TE guided modes within the hybrid waveguides of 900 nm and 450 nm widths, respectively. We estimate about 30% of the power of the fundamental TE mode is present in the LN layer (ГLN: confinement in LN = optical mode power in LN / optical mode power in SiC) for the waveguide width of 900 nm as shown in Fig. 5(a). For the waveguide width of 450 nm, we observe that the fundamental TE mode extends further into the LN layer increasing the confinement to 77% as illustrated by the mode profile in Fig. 5(b). This is an important observation as it explains how we can use the design parameters to control the power between the two layers, e.g., for the desired level of EO tuning.
Fig. 6. The TE-mode profiles of the hybrid waveguides with width of (a) 900 nm and (b) 450 nm in SiC, representing the two ends of the waveguide taper used in one arm of the racetrack resonator for better EO tuning. (c) The microscopic image of the racetrack (coupled to a 900 nm wide bus waveguide with a coupling gap of 120 nm, a bend radius of 70.45 µm, and the total circumference of 1.042 mm) with Au electrodes (interaction region highlighted by the dashed box). (d) The geometry of the highlighted interaction region in (c) showing the taper and electrodes (Au pads). (e) The spectral response of the racetrack in (c) with no applied voltage showing a free spectral range (FSR) of 0.97 nm and loaded Q ≈ 14,000.
The active devices of interest (EO phase shifters) are demonstrated within racetrack resonators coupled to a bus waveguide all fabricated in the SiC layer. The index change is achieved through the application of electric field. For this purpose, the top-arm of the racetrack resonator is integrated with electrodes as shown in Fig. 6(c) to apply a DC electric field creating along a waveguide-electrode interaction region. Furthermore, to increase the strength of EO tuning, the interaction region is linearly tapered down from the original width of 900 nm to a smaller width of 450 nm (see Fig. 6(d)), which increases the confinement in LN resulting in stronger interaction between the optical mode and the DC electric field. The selection of the 450 nm width at the end of the taper is based on ease of fabrication and limiting the overall device size while achieving a good portion of the mode energy (77%) in the LN layer for effective tuning. The spectral response of the racetrack in Fig. 6(c) without any DC voltage is shown in Fig. 6(e). The electrodes for applying the DC field are placed on the LN layer ∼ 1 µm apart from the waveguide edges, and the refractive index change is estimated from the CHARGE and FEEM simulations implemented using Lumerical (see Supplement 1 for more details on the simulation approach and the governing equations). By using a detailed optimization of the trade-off between the added loss and the necessary operation voltage for a desired tuning, one can achieve the desired performance.
Figure 7(a) shows the fundamental TE mode in the SiC-LN waveguide (SiC width = 450 nm in the EO tuning region of the tapered arm) with electrodes placed on LN. The DC electric field distribution caused by an applied voltage of 15 V is depicted in Fig. 7(b), as obtained from the CHARGE simulations. The induced refractive index change calculated from the simulations follows a linear trend with the applied voltage as shown in Fig. 7(c), which is a characteristic of the linear EO effect. The optical loss for the TE mode due to metal absorption is approximately 0.39 dB/cm as shown in Fig. 7(d), obtained from the FEEM simulations.
Fig. 7. (a) The fundamental TE mode in the hybrid waveguide (width = 450 nm) from FEEM simulations, (b) the DC electric field distribution under applied voltage of 15 V (from CHARGE simulations), and (c) the variation of the effective index of the fundamental TE mode with the applied DC voltage due to the linear EO effect.
To demonstrate the EO tuning, we apply a DC voltage to the fabricated electrode pads in the interaction region of the racetrack resonator. The index change induces phase shift of the optical signal in the racetrack, as it travels through the interaction region, which shifts the resonance wavelengths. The details of the theoretical wavelength shift estimation are provided in Supplement 1. Figure 8 shows the experimental results of the EO resonance wavelength tuning for two racetrack resonators with different interaction regions. The basic waveguide width for both structures is 900 nm as explained before. One of these racetracks is designed to include the tapering in the interaction region to a width of 450 nm (illustrated in Fig. 6(d)), while the other consists of a waveguide with a constant width (900 nm) all along the racetrack (i.e., no tapering). The resonance wavelength shifts for the racetracks without and with taper are shown in Figs. 8(a) and 8(b), respectively. For the racetrack without taper, we estimate the wavelength-shift sensitivity of ∼ 0.0043 nm/V (Fig. 8(c)), indicating a Vπ.Lπ of ∼ 3.15 V cm. For the racetrack with the tapering of the waveguide in the interaction region, we observe a higher sensitivity of ∼ 0.0062 nm/V or Vπ.Lπ ≈ 2.18 V cm (Fig. 8(d)). The results in Fig. 7 clearly show the possibility of using the geometrical design parameters of the resonator in the tuning region to change the sensitivity of the phase shifter to the applied voltage.
Fig. 8. Resonance shift observed due to the EO effect in the racetrack resonator as a function of the applied voltage (a) without the taper, (b) with the taper described for the structure in Fig. 6(d). The sensitivity of the resonance shift as a function of the applied voltage for (c) the non-tapered waveguide (width = 900 nm), and (d) the tapered waveguide (width = 450 nm) in the waveguide-electrode interaction region. The solid lines in (c) and (d) connect the experimental data points and serve as guides for eye showing an approximately linear trend.
Our results show the first demonstration of the feasibility of using the hybrid 3C-SiC-LN platform for integrated nanophotonics. The distribution of the guided mode between the SiC and LN layers allows for using the trade-offs among the tuning sensitivity, device footprint, and optical loss to obtain the desired device performance without any need to etch LN. Note that like any other first demonstration, we did not perform a rigorous optimization of the fabrication processes or the device designs. Thus, there are still several areas where performance improvement can be achieved. Using a thicker initial 3C-SiC material for having a higher quality SiCOI platform before bonding to LN, improving the quality of the hybrid platform by adding stress-releasing patterns to the LN layer, switching to 4H-SiC to achieve a higher material quality at a higher cost and lower yield, and further optimization of the geometry of the device (including the thicknesses of SiC and LN) are a few examples.
In summary, we demonstrated here a novel hybrid 3C-SiC-LN platform where CMOS-compatible fabrication is conducted on the SiC layer, and the bonded LN layer provides the EO effect for tuning. On this platform, we demonstrated an EO phase shifter integrated into a racetrack resonator providing a low Vπ.Lπ ≈ 2.18 V cm. The combination of the high-speed and energy-efficient EO effect in LN with the broad wavelength transparency and CMOS compatibility features of SiC will enable broadband high-speed devices (e.g., modulators and switches) with low-energy consumption fabricated in a CMOS compatible process flow. While this paper demonstrates the feasibility of this unique platform, future research for improving the performance measures and material quality will be needed to convert it into a universal CMOS-compatible platform for ultrafast, low-power, and miniaturized nanophotonic systems for passive, active, nonlinear, and quantum photonic applications.
Funding
Army Research Office; National Science Foundation.
Acknowledgments
This work was performed in part at the Georgia Tech Institute for Electronics and Nanotechnology (IEN), a member of the National Nanotechnology Coordinated Infrastructure (NNCI), which is supported by the National Science Foundation (NSF) (Grant ECCS-1542174).
The authors would like to thank especially the IEN staff at Georgia Tech (Tran-Vinh Nguyen, Yolande Berta), engineers at EVGroup (Sean Napier, Garret Oakes, Vineeth Reddy), and Entrepix (Scott Drews) for their valuable discussions and process support.
Disclosures
The authors declare no conflict of interest.
Data availability
Data underlying the results are not publicly available at this point but may be obtained from the authors upon request.
Supplemental document
See Supplement 1 for supporting content.
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