1. Introduction

Digital halftoning, sometimes referred to as spatial dithering, is the process by which a continuous-tone, gray-scale image is printed or displayed using only binary-valued pixels. The underlying concept is to provide the viewer of the image the illusion of viewing a continuous-tone image when, in fact, only black and white pixels values are used in the rendering. This process is particularly important to applications such as laser printing, bilevel displays, xerography, and more recently, facsimile.

One of the most popular halftoning processes, introduced by Floyd and Steinberg [1], uses the error diffusion algorithm. In this algorithm, each pixel value is quantized and the resulting quantization error is diffused, in a predetermined weighted pattern to neighboring pixels, in an effort to influence the quantization decision of the neighboring pixels so to improve the overall quality of the halftoned image. Classical error diffusion algorithms, however, suffer from implementation constraints. In conventional unidirectional error diffusion, the algorithm raster scans the image (typically from upper left to lower right) and the quantization error from each pixel is diffused forward and down in a fixed weighted pattern. For each pixel, a binary quantization decision is made based on the intensity of the individual pixel and the weighted error diffused from the previously quantized pixels. As a result of this unidirectional processing, the diffusion filter is necessarily casual resulting in undesirable visual artifacts in the halftoned image.

Recently, we have investigated the application of a neural network implementation of a two-dimensional error diffusion algorithm for the purpose of improving overall halftone image quality [2,3]. In this implementation, all quantization decisions are made in parallel and the error is diffused symmetrically in two spatial dimensions. Visual artifacts previously attributable to the unidirectional halftoning algorithm are eliminated and the overall halftoned image quality is significantly improved. Computer simulations of the two-dimensional error diffusion neural network have produced some of the best halftoned images to date. However, implementation of the algorithm in software is not practical due to the computational effort and interconnect requirements of the neural algorithm. Consequently, several smart pixel technologies have recently been investigated as possible hardware implementation options to achieve real-time function of the neural halftoning algorithm.

Smart pixels integrate optical devices with solid state circuitry to take advantage of the speed and processing capabilities of solid state electronics and the parallelism of optics for input and output. Proof-of-concept smart pixel arrays (SPAs), using three different smart pixel technologies, have been manufactured and tested to evaluate their capability to implement a full-scale error diffusion neural network for digital halftoning: flip-chip bonding of gallium arsenide (GaAs) self electrooptic effect device (SEED) modulators on silicon complimentary metal-oxide-semiconductor (CMOS) circuitry [4,5]; liquid crystal spatial light modulators integrated with silicon CMOS circuitry, referred to as liquid crystal on silicon (LCOS) [6]; and monolithic integration of LEDs with GaAs circuitry using Epitaxy-on-Electronics (EoE) [7]. All have demonstrated promise as viable technologies to produce SPAs capable of high quality halftoned images at video frame rates.

This paper presents experimental results from testing one of the proof-of-concept neural SPAs, called OPTOCHIP, manufactured using EoE technology. Due to the audience of this publication, only results from testing the optical devices on the SPA will be presented here. The results of testing the purely electronic circuitry will be presented in a later publication. The following section describes the device architecture, Section 3 presents the experimental results and analysis from testing each of the SPA components, and finally, a summary of the results and discussion of the applicability of this smart pixel integration approach is included in Section 4.

2. Device Architecture

This SPA was one of nine individual designs in the composite OPTOCHIP Project funded by the Defense Advanced Research Projects Agency (DARPA). The purpose of the OPTOCHIP Project was to provide complex optoelectronic integrated circuits to application-level researchers to advance the development of the optical interconnect field while simultaneously providing feedback on the EoE process to refine and improve the specific optoelectronic devices. LEDs were chosen as the first optoelectronic sources to be manufactured using EoE with the ultimate goal to produce lasers for SPAs.

The architecture for this SPA design was a 3×3 neural array, shown in Fig. 1, which was designed to enable characterization of three of the functional components necessary for the implementation of an optoelectronic neuron which ultimately will be employed in the smart pixel realization of the error diffusion neural network. The three components in this architecture are: 1) detection of the optical gray-scale input signal, 2) implementation of a specific non-linear sigmoidal function for thresholding (quantization), and 3) optical transmission of the resulting bilevel output signal. Figure 2 shows a photomicrograph of a single OPTOCHIP neuron and Fig. 3 shows the corresponding schematic of the neural circuitry, including both enhancement- and depletion-mode metal-semiconductor field-effect transistors (MESFETs), called DFETs and EFETs respectively. The circuitry includes optically sensitive EFET (OPFET) detectors, a direct-coupled FET logic (DCFL) inverter and buffer to produce the sigmoidal function, and a driver circuit for each LED. Three voltages (V_DD, V_bias, and V_LED) are common to all nine neurons on the SPA (numbered by the convention shown in Fig. 1) while all other inputs and outputs are pinned-out separately to allow testing of each individual component on the chip. This methodology provided the ability to not only analyze optical device and circuit uniformity across an individual chip, but also to analyze chip-to-chip uniformity and potentially comment on manufacturability issues.

 

Fig. 1. Photomicrograph of OPTOCHIP, a proof-of-concept smart pixel implementation of a 3×3 neural array.

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Fig. 2. Photomicrograph of a single neuron on OPTOCHIP displaying the three neural components: 1) the detector circuit, 2) the quantizer circuit, and 3) the LED with its driver circuit.

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Fig. 3. Circuit schematic of a neuron on OPTOCHIP. Darkened transistors are depletion-mode MESFETS. All others are enhancement-mode MESFETS.

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The first step in manufacturing the neural SPA was producing the circuitry through a commercially available fabrication process. The manufacturer for the electronic circuitry in this SPA was Vitesse Semiconductor Corporation using their HGaAs III process. In the design of the circuitry, the placement of the optoelectronic devices was generally unrestricted, limited only by the physical dimensions of the optoelectronic devices and system integration issues such as optical crosstalk, localized thermal heating, and circuit sensitivity. The completed wafers were then sent to the Massachusetts Institute of Technology (MIT) where the LEDs were then integrated using the EoE process [8,9]. Dielectric growth windows (DGWs) were etched in the circuitry and then indium gallium phosphide (InGaP) LEDs were regrown in the DGWs using molecular beam epitaxy (MBE) at temperatures below 475°C. This lower temperature approach to MBE has previously demonstrated high quality optoelectronic devices without the performance degradation typically associated with MBE regrowth on GaAs circuitry. [10].

Four SPA chips received from MIT were characterized. Two were pre-EoE devices without LEDs, labeled #E1 and #E2 throughout the remainder of this paper, and two were post-EoE devices with LEDs, labeled #815 and #816. It would have been preferable to characterize each chip before and after the EoE process but the scope of this project did not allow this. The following sections present the experimental results from testing the SPA’s optical components, the detectors and LEDs.

3. Experimental Results and Analysis

3.1 OPFET Detectors

The detector circuit for the neural SPA receives an analog optical input signal and produces an analog voltage which will subsequently be used as the input to the quantizer circuit. The circuit consists of a 40-μm × 40-μm OPFET detector in series with a 18-μm × 6-μm DFET. The detector is surrounded by an n⁺ source/drain implant ring that is electrically connected to reduce any crosstalk with surrounding circuitry. The OPFET is simply described as an EFET without a gate. The transistor is instead turned on by incident light which creates charge carriers in the channel that are subsequently swept out by the drain-to-source bias voltage.

To characterize the detector circuit, an optical input from a Ti:sapphire laser with known power, tuned to a wavelength of 850 nm, was focused onto the detector with the entire beam incident inside the detector boundaries. Here, V_DD was set to 2.0 V. The output voltage, V_det, was then measured as the incident optical power was varied over a 100 nW dynamic range. Measurements were made on each of nine detectors on two different SPA chips, a pre-EoE chip (#E1), and a post-EoE chip (#816). By the time the detector testing was conducted, Chip #E2 and #815 had become non-functional. Performance curves for the nine detectors on the pre-EoE chip are shown in Fig. 4, while the performance curves for the nine detectors on the post-EoE chip are shown in Fig. 5.

The detectors proved to be very sensitive but demonstrated poor uniformity across a single chip in the 0–30 nW range. In this range, the output voltage varied (compared to the maximum value) between the extremes of 4% and 51% for the pre-EoE chip and between 1% and 53% (excluding #4 and #7 as outliers) for the post-EoE chip. The behavior of detectors #4 and #7 on Chip #816 is believed to be the result of damage to the OPFETs, which could have occurred during the fabrication, regrowth process, packaging, or bonding steps.

These detectors were designed for digital applications and from Figs. 4 and 5 it can be seen they would work very well. But for this analog application, the signal variation in the 0–30 nW range for an array of detectors on the same chip is unacceptable. The variation is most likely due to differences in individual OPFET doping levels, for which the tolerances for uniformity are not as stringent for a digital fabrication process as for an analog process. This variation in doping will cause each detector to turn-on at different incident power levels. A detector more suitable to analog applications would be selected for full-scale implementation of the neural SPA.

Some of the variation of the detector performance may also be attributed to the manufacturing process. In order to control the doping level and get good uniformity, the Vitesse HGaAs III process includes a light p-type implant over the entire wafer. This produces a parasitic p ^--n junction below all devices on the chip with the p-side of these devices electrically connected to the p ^--layer. A floating photovoltaic self-bias, or backgate, voltage is therefore produced when light is incident on this junction. This backgate voltage can significantly effect the performance of the detectors and produce crosstalk with adjacent devices. For the HGaAs III process, the n ⁺ implants around the detectors were found to be of insufficient depth to isolate the detectors and prevent this crosstalk. Vitesse’s latest revision of their process, HGaAs IV, has since corrected this backgating problem by providing reliable isolation rings with deep n ⁺ implants and ohmic contacts to the p ^-layer allowing the backgate voltage to be implicitly set [9].

 

Fig. 4. Pre-EoE detector performance curves (Chip #E1).

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Fig. 5. Post-EoE detector performance curves (Chip #816).

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3.2 Light Emitting Diodes (LEDs)

The output of the halftoning neural array is a digital optical signal, in this case an LED turned either on or off for each pixel. The layered structure of the InGaP LEDs grown by MIT in 50μm × 50-μm DGWs using the EoE integration process is shown in Fig. 6a. A scanning electron micrograph of a completed LED is shown in Fig. 6b and a photomicrograph of an operating LED is shown in Fig. 6c. The LEDs were designed to emit at 873 nm, the room temperature badgap of GaAs. Each LED is surrounded by a contiguous metal shield, constructed from metal layers 1 through 3, to prevent injection of stray charge carriers into the electronic circuitry neighboring the radiating LED.

 

Fig. 6. (a) Illustration of the layers of the InGaP LED structure grown by EoE, (b) Scanning electron micrograph of a completed LED, and (c) Photomicrograph of an operating LED.

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Four voltages are required to operate the LEDs, three of which are common to all LEDs in the 3×3 array. The bias on the LED is set with V_LED = 5.0 V and the magnitude of the current through the LED is varied by varying V_bias between 0.0 V and 2.7 V. V_DD is again set to 2.0 V. Each LED has a separate pin for V_ctrl. The LEDs are turned on or off individually by setting V_ctrl to 0.7 V or 0.0 V, respectively. The LEDs were tested for uniformity in power and spectral characteristics. Each of the nine LEDs on Chips #815 and #816 were tested for a total of eighteen characterized LEDs.

The output power of each LED was varied by adjusting V_bias and the radiated power measured with a 1-cm² circular detector placed as close to the LED as possible. Since the LEDs radiation pattern is Lambertian, a correction factor was calculated, using the geometry of the experimental setup to account for the radiation not incident on the detector, and applied to the power measurements. Light versus current (L-I) curves for the eighteen LEDs are shown in Fig. 7.

This was MIT’s first attempt at manufacturing monolithically integrated sources using EoE and the uniformity and yield for the LEDs was generally poor. Though all eighteen LEDs emitted light, only about one third emitted sufficient power to be useful for this application. Subsequent to this fabrication, larger 85-μm and 100-μm LEDs, manufactured by MIT with the same processing approach, demonstrated better uniformity and yield. The difference has been attributed to foreign material that remained in the 50-μm DGWs after the etching and cleaning process which did not allow uniform material growth in the 50-μm LED structure. Subsequent changes in the DGW etching and cleaning process have resulted in higher quality LED structures for all size LEDs.

 

Fig. 7. L-I curves for eighteen LEDs from Chips #815 and #816.

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From Fig. 7 it is clear that substantial current is required to drive the LEDs at sufficient output power, in excess of 6 mA per LED. For a full-scale digital image halftoning application, the total power required to drive a large array of pixels (256 × 256 or larger) would likely produce undesirable thermal effects on the chip. Part of the cause of the large drive current is the inherent inefficiency of LEDs, which in this case, is exasperated by the impurities described in the previous paragraph.

Spectral testing was conducted by coupling light from the LED directly into a multimode optical fiber which was coupled to an optical spectrum analyzer. Spectral testing could be not be conducted on five of the LEDs each on Chips #815 and #816 due to insufficient emitted power. Figure 8 shows the spectral emission curves at three different power settings for the LED at Neuron #6 on Chip #815. The mean center wavelength of the ten LEDs which were tested was 872.5 nm with a standard deviation of 1.4 nm and the mean full-width half-maximum (FWHM) was 31.0 nm with a standard deviation of 2.5 nm.

The LEDs demonstrated good spectral consistency, with the measured wavelength matching the designed wavelength within the experimental error of the measurement equipment. The slight red-shift in wavelength and increased FWHM with increased power (see Fig. 8) were consistent trends across all ten LEDs. Both trends are consistent with typical LED performance and neither is significant enough to effect the performance of the neural halftoning application.

Although these LED sources have limitations, the results from the OPTOCHIP project have provided valuable information for improving the EoE process and for pursuing MIT’s ultimate goal, using EoE to produce higher efficiency laser sources.

 

Fig. 8. Spectral curves for the LED on Chip #815, Neuron #6, at three different power settings.

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4. Summary

In this paper we have presented the architecture and experimental characterization of a novel SPA employing InGaP LEDs monolithically integrated on GaAs circuitry using EoE technology. The results show the ability to produce high density optoelectronic circuits for the error diffusion neural network application. Though characterization of the detectors and LEDs on this device demonstrated limitations in their use, future developments in this technology are promising. The measured non-uniformity in detector performance will likely be improved by the next generation circuit manufacturing process, Vitesses’s HGaAs IV process. It was known prior to the manufacture of these SPAs that the high power requirements and poor directionality of LEDs are characteristics that make them an impractical choice for use in large arrays required for full implementation of the error diffusion neural network, and the experimental data confirm this. Lasers provide better efficiency and directionality than LEDs and provide monochromaticity that LEDs do not. Better efficiency and directionality are characteristics required for successfully implementing a full-scale neural SPA for near real-time digital image halftoning and monochromaticity allows the use of diffractive optics for array generation and fan-out. The goals of using LEDs for these SPAs were to gain experience in using EoE to manufacture optoelectronic sources, to improve the EoE process, and ultimately to manufacture lasers, all goals which have been successfully achieved subsequent to this specific work.