FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

Noriaki Kaneda; Ziyi Zhu; Chun-Yen Chuang; Amitkumar Mahadevan; Bob Farah; Keren Bergman; Doutje Van Veen; Vincent Houtsma

doi:10.1364/OFC.2020.T4D.2

Optical Fiber Communication Conference (OFC) 2020
OSA Technical Digest (Optica Publishing Group, 2020),
paper T4D.2
•https://doi.org/10.1364/OFC.2020.T4D.2

FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

Noriaki Kaneda, Ziyi Zhu, Chun-Yen Chuang, Amitkumar Mahadevan, Bob Farah, Keren Bergman, Doutje Van Veen, and Vincent Houtsma

Optical Fiber Communication Conference 2020

San Diego, California United States
8–12 March 2020
ISBN: 978-1-943580-71-2

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AI Assisted Access Networks (T4D)

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N. Kaneda, Z. Zhu, C. Chuang, A. Mahadevan, B. Farah, K. Bergman, D. Van Veen, and V. Houtsma, "FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON," in Optical Fiber Communication Conference (OFC) 2020, OSA Technical Digest (Optica Publishing Group, 2020), paper T4D.2.

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Abstract

A fixed-point deep neural network-based equalizer is implemented in FPGA and is shown to outperform MLSE in receiver sensitivity for 50 Gb/s PON downstream link. Embedded parallelization is proposed and verified to reduce hardware resources.

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