Abstract
VCSELs are near ideal light sources for free space, parallel optical interconnects since they are highly efficient, can be fabricated into 2D arrays and emit a low divergence column of light normal to the surface. However, integrating the VCSELs into smart pixels introduces fabrication problems since they can not be grown on foundry fabricated Si CMOS or GaAs MESFET circuits. Thus, the fabrication of complex pixels is difficult. Three methods of electrically connecting VCSELs to electronic chips have been discussed by Bryan et al. [1]; wire bonding, bridge bonding, and flip chip bonding to the whole VCSEL chip to a separate area of the electronic chip. Unfortunately none of these techniques are suitable for large-high speed arrays since they involve excessive numbers of long electrical lead wires or thin film traces which occupy a large area and add significantly to the capacitance and inductance of the circuit. Recently Goosen et al. [2] have developed a co-planar flip-chip bonding process for the attachment of SEED devices to CMOS chips. Their process has been shown to be both scalable and reliable [3]. This technique significantly increases the combined array size and decreases the interconnect capacitance and inductance allowing for much faster operation. The present paper reports the development of a co-planar bonding technique for VCSELs onto prefabricated pixel chips. This paper presents the details of this flip-chip bump-bonding integration.
© 1997 Optical Society of America
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