1. Introduction

Crystalline Si solar cells comprise more that 80% of the photovoltaic (PV) market today, and between the two types of technologies using single crystalline and multi-crystalline Si substrates, multi-crystalline (MC) cells currently dominate due to relatively lower costs [1]. Si solar cells typically require a texturing of the surface in order to enhance light trapping. Such texturing is straightforward and effective for single crystalline Si solar cells, and carried out using a KOH based etching procedure [2]. However, due to the anisotropic nature of the KOH etch, this process cannot be used for MC Si cells. While an acid based etching technique is often used [3], this has been unsatisfactory. To date, there exists no satisfactory process for texturing MC Si.

In this paper, we demonstrate that texturing the MC Si surface in the form of micron wire arrays is a possible solution, and demonstrate functional wire array textured MC Si solar cells fabricated using a self-assembled microsphere based patterning technique. The patterning is done using chemically functionalized polystyrene microspheres to create cheap, easily dispensed, one monolayer high, patternable masks on a functionalized MC Si surface. Dry etch techniques, increasingly used in the PV industry, are then employed to form textured wire arrays on the MC Si substrates, using the microsphere mask. We show that the wire patterned MC Si devices show an enhanced short circuit current as well as an improved device “pseudo-efficiency” (i.e. the efficiency with the effects of the series resistance extracted) compared to planar MC Si devices. While the improvements are a result of the significantly lowered surface reflectivity due to the presence of the wires, these results also highlight the series resistance as a significant issue for wire textured MC Si solar cells. Previous reports [4,5] have shown that the Si wire array structure can enhance the absorption and carrier collection. The self-assembled microsphere patterning technique has been studied earlier [6], in the context of single crystal Si substrates, and previous published reports have demonstrated benefits in the reflectivity of the substrates [7]. High performance wire-array Si solar cells have been demonstrated and effects of varying the wire size have been discussed [8]. In this work we adapt this process to the needs of MC Si solar cells where the surfaces are considerably more irregular than single crystal Si, and where the needs for a texturing process is more urgent. In addition to the expected benefits in light absorption, we have fabricated functional solar cells and demonstrate enhancements in the short circuit current and the pseudo efficiencies, compared to non-textured, planar controls.

2. Experiments

Lightly doped (~5 × 10¹⁶ cm⁻³) p-type MC Si wafers were first etched with NHA (HF:HNO₃:CH₃COOH = 2:10:5) solution to remove the surface saw damage of approximately 10 - 15 µm Si, since MC Si wafers are typically received in as-sawn condition. Following an O₂ plasma clean at 150W for 30 minutes to remove polymer residues and form a thin oxide layer, the substrates were rinsed with deionized (D.I.) water and dried. The MC Si surfaces were then chemically functionalized by modifications with aminopropyltriethoxysilane (amino-silane) following a similar process reported earlier [9]. After this, the MC Si substrates were immersed in a solution of 0.2% amino-silane in D.I. water for 1 hour at room temperature, rinsed with D.I. water and then baked at 85 °C for 15 minutes. This process results in the formation of –NH₂ bonds on the native oxide surface of the MC Si as shown in Fig. 1(b) , in order to create a surface for selective adhesion of 1 monolayer of the microspheres.

 

Fig. 1 (a)-(d) Microsphere patterning on MC Si substrates. (e) SEM image of patterned monolayer microsphere on MC Si.

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Carboxyl functionalized polystyrene microspheres with diameter of 1 µm were diluted in D.I. water to a concentration of ~6 mg/ml and dispensed on MC Si substrates to an amount of ~100 µL per 1 cm² of Si surface. After a drying time of 1-3 hours in a laboratory ambient, the microspheres remain stacked as multiple layers on the MC Si as illustrated in Fig. 1(c). The samples were then rinsed with D.I. water and blown-dry with compressed nitrogen gas. This process washed away the excess microspheres adhering to one another, leaving behind a single monolayer of the spheres on the Si surface shown in Fig. 1(d). The microsphere patterning process and a top-view scanning electron microscope (SEM) image of the monolayer of microspheres are shown Fig. 1(e). The typical surface coverage was about 90-95%. It was found that too diluted solution would cause much less coverage, which was not desirable. The process is straightforward and requires no spinning or roller/squeegee based dispensing.

The microsphere monolayer was then used as a mask for subsequent dry etching to create the wires. Following a trimming process in oxygen plasma (100 Watt, 15 sccm) to open the spacing between each microsphere, the samples were then reactive-ion etched (RIE) with a gas mix of HBr (160 sccm), Cl₂ (100 sccm), and CF₄ (32 sccm) at an RF power of 85 Watts. This created an array of slightly tapered wires, and an example is provided in Fig. 2(a) ; where the wire height is ~1.8 µm with wire diameters of 400 ~500 nm at the top and around 700~800 nm at the base. Following the etching, the samples were cleaned in a piranha solution (H₂SO₄:H₂O₂ = 3:1) solution for 5 minutes and then in buffered HF (BHF) (HF: H₂O = 1:10) for 2 minutes for 3 cycles, to remove the RIE residues.

 

Fig. 2 (a) SEM images of top-down wires after RIE. (2) Measured reflectivity of MC Si (Device A), MC Si with wire textured structure (Device B), and standard KOH textured single crystal Si. Dash lines indicate WAR of each sample.

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Radial p-n junctions in the wires were then created using a gas phased diffusion process using POCl₃ at a temperature of 840 °C for 60 minutes to form the n-type emitter layer with a doping concentration of ~10¹⁹ cm³ at surface and a junction depth of ~400 nm.

After the POCl₃ process, samples were cleaned using standard RCA-1 and RCA-2 processes, followed by removing ~10 nm of the surface Si with NH₄OH:H₂O (25:1) to reduce RIE damage. This was followed by an oxidation step to grow 10 nm of SiO₂ in a furnace at 900 °C (20 minutes at 1:1 O₂:N₂ flow rate). Devices were completed with the deposition of metal finger contacts (see Fig. 3(a) insert) for the top electrode (50 nm Ti, 50 nm Pd and 150 nm Ag) metal contacts, a Ti/Au (10 nm/100 nm) for the back contact, followed by dicing to form 1 cm x 1 cm devices. Forming gas anneal at 400 °C for 30 minutes was performed to improve Si-metal contacts. Cu plating technique was used to deposit Cu on the top electrode to reduce the metal contact resistance and fill any discontinuity in the front contact lines.

 

Fig. 3 (a) Measured light I-V characteristics of control sample, and devices with wire texture. Insert: device illustration. (b) SEM image of MC Si devices with wire texture.

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Three types of devices were fabricated using above processes as listed in Table 1 . Type A refers to the planar controls fabricated on a bare MC Si wafer with same processing steps but without any wire patterns. Types B and C were MC Si solar cells with wire texturing. The type B device had the SiO₂ passivation layer prior to top contact metallization, while type A did not have any oxide passivation. More than 10 devices were fabricated for each structure and typical single device performance was discussed below.

Table 1. Measured solar cell device parameters

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3. Results and discussion

The reflectivity measurement was performed on a ProtoFlex's quantum efficiency QE1400 measurement system. The incident light was at ~10 degree to the normal of the sample surface, and the reflected light was collected by a 2-inch diameter integration sphere. The measured reflectivity spectra of the wire-textured sample (Device B) are plotted in Fig. 2(b) and compared to the planar substrate and a KOH etched single crystal Si (100) substrate with a pyramidal texture, as a reference. The standard textured single crystal Si was fabricated in the lab using a (100) single crystal Silicon etched in a 90 °C 1.6 Mol KOH solution for 15 minutes. As the data indicates, there is a significant drop in the reflectivity for the wire textured MC Si devices, which is comparable to the reflectivity of a standard KOH etched single crystal Si (100) substrate. It is also instructive to compare the solar weighted average reflectivity (WAR) relative to the AM1.5G solar spectrum, calculated in the range of 300 – 1100 nm. The WAR reflectivity drops from 22.6% for the planar MC Si sample to 13.5% for the wire textured MC Si sample, and is comparable to the 11.9% WAR for a KOH textured single crystal Si (100) sample with pyramidal surface morphology.

The photovoltaic characteristics of the devices were measured using a simulated AM1.5G solar illumination with a reference standard. The measured light I-V characteristics are plotted in Fig. 3(a) and the solar cell device performance parameters are listed in Table 1. The table summarizes the efficiency, fill factor, open circuit voltage (V_OC), and short circuit current density (J_SC) extracted from I-V measurements with 1 sun illumination, and series resistance (R_S) which was extracted from intensity dependent light I-V and J_SC-V_OC measurements [10,11]. The table also includes the pseudo-efficiency, which displays the intrinsic performance of the solar cell by excluding the effect of series resistance. The standard technique for this measurement is described in Sinton’s work [10,12].

From the light-IV measurement, all the wire textured MC Si devices display, on average, 20% higher short circuit current densities (J_SC) compared to the planar control sample. These results indicate higher photocurrents, and are directly related to the enhanced light absorption in these samples. While the J_SC is higher for the wire textured MC Si samples, as listed in Table 1, they have lower fill factors and higher series resistances compared to the planar device, resulting in efficiencies that are fortuitously close to one another. These differences shed light on the underlying effects of the wire microstructure. The open circuit voltage (Voc) of the wire textured MC Si devices is lower by about 30-40 meV compared to the control sample. This is expected, since the Voc can be expressed as following [13]:

The observed high series resistance is the principal detriment, and stem from a combination of several factors: (i), the presence of the wire textured structures that perforate the metal (busbar and finger); and (ii), an increase in the metal-semiconductor contact resistance due to RIE damage on the surface. Extracting out the series resistance, the benefits of the wire textured cells, thanks to enhanced light trapping and hence improved J_SC, are clearly observable with the pseudo-efficiencies of the planar control (sample A) increasing relatively by 7% and 16% for the wire textured samples (B and C). Device C showed light series resistance and lower fill factor than Device B, which could be caused by additional SiO₂ passivation.

The external quantum efficiency (EQE) and internal quantum efficiency (IQE) of the fabricated solar cells are plotted in Fig. 4 . As expected, solar cell devices with the wire-textured structure show a higher EQE because of improved light absorption. For the IQE measurement, with the relative light absorption normalized out, the control sample shows a higher efficiency because of the lower series resistance and higher fill factor. These results further clarify and contrast the beneficial effect of the wire texture, i.e. enhanced light absorption, and the drawbacks, i.e. increased series resistance and carrier recombination.

 

Fig. 4 (a) EQE, and (b) IQE of MC Si solar cells with/without wire textured structure.

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4. Conclusion

In summary, we demonstrated a simple, economical and scalable way of creating wire textured MC Si solar cells to yield reflectivities that are comparable to KOH etched single crystals Si solar cells. The process requires a chemically sensitized self-assembled mask layer without requiring optical lithography, and a dry etch step, which is increasingly used in the Si photovoltaic industry. The result solar cell devices show improved short circuit current and, once the series resistance effects are separated out, the power conversion efficiency. The work also points to series resistance being a significant challenge that needs to be overcome for any wire array based solar cells.