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This paper presents a high performance DC-coupled 10 Gbit/s APD-based optical burst-mode receiver (BM-RX) for symmetric 10G-GPONs. The BM-RX can handle upstream bursts with a loud/soft range wider than 24.0 dB, and the measured sensitivity is −30.0 dBm at BER = 10−3 after a start of burst settling time no longer than 51 ns. This paper also investigates, for the first time, the inter-burst guard time required for a 10 Gbit/s BM-RX with auto-reset generation, while the PON operates upstream at a high raw BER and is using FEC.
©2011 Optical Society of America
1. Introduction
As the demand for broadband services keeps rising, interests in time division multiplexing (TDM) passive optical networks (PONs) continue to grow. Anticipating an explosive growth of the worldwide data traffic, IEEE 10GE-PON and ITU-T XG-PON1 systems have been standardized and start being deployed. The 10GE-PON and the XG-PON1 can provide respectively 10/10 Gbit/s and 10/2.5 Gbit/s downstream/upstream transmission capacities. For the near future a symmetric 10/10G-GPON with shorter overhead may provide higher network transmission capacity and efficiency, especially when short bursts are emitted upstream.
The optical line termination (OLT) of the 10G-GPON relies on a high-performance burst-mode receiver (BM-RX). To cover the high optical power budget required for co-existence with already deployed PONs, avalanche photodiode (APD) burst-mode receivers (BM-RX) are used with strong forward error correction (FEC). Several 10 Gbit/s BM-RXs have been published [1–4] for IEEE 10GE-PONs, where the BM-RX settling time requirement is quite relaxed. The development of a 10 Gbit/s BM-RX for advanced 10G-GPONs however remains challenging due to the combined requirements: high BM-RX sensitivity (< −28 dBm), wide dynamic range (DR > 22 dB) and short settling time (< 100 ns) are the BM-RX’s key figures of merit.
Most 10 Gbit/s BM-RX designs to date use AC-coupled interfaces [1–4]. However, a fundamental limit on performance of AC-coupled BM-RXs results from the AC-coupling time constant tradeoff. As shown in Fig. 1 ., the coupling capacitance between the burst-mode transimpedance amplifier (BM-TIA) and the burst-mode limiting amplifier (BM-LA) should be chosen carefully to speed-up the settling time while tolerating a long sequence of consecutive identical digits (CID). Therefore, AC-coupling requires line coding, such as 8B/10B and 64B/66B used in 1G-EPON and 10G-EPON respectively, to limit the maximum CID length. The AC-coupling time constant tradeoff makes it difficult to achieve a response time below 400 ns. One method to reduce the response time below 400 ns, while maintaining operational conditions with long CIDs, is to use two-stage feedback inside the BM-LA [3]. In [4], an AC-coupled BM-RX applies baseline wander common mode rejection combined with inverted distortion techniques, resulting in a settling time of 150 ns at the cost of an additional BM-Rx sensitivity penalty of 1dB.
The alternative is a DC-coupled interface between a BM-TIA and a BM-LA. Ref [5] presents a DC-coupled receiver which meets the 10G-EPON specifications with a settling time of 800 ns. As there is no coupling time constant tradeoff, a DC-coupled BM-RX can achieve a much shorter settling time [6]. Our previous work shows a 10 Gbit/s DC-coupled PIN-Based BM-RX for a 10 Gbit/s long reach PON [7]. The upstream channels were OSNR limited by using optical amplification, and the BM-RX did not require high sensitivity or wide dynamic range. Therefore threshold extraction by peak detection was chosen to obtain a short overhead of 58 ns, and a measured BM-RX sensitivity of −10.9 dBm at a BER of 10−10, with a loud/soft ratio of 10.6 dB. However, a peak-detection based feed-forward circuit is inherently not very accurate, and results in relatively high power consumption. In this paper we present a new DC-coupled feedback BM-RX which combines the advantages of DC- and AC-coupled approaches to provide an overall optimized performance.
Efficient PON uplink transmission requires a DC-coupled BM-RX with a short overhead for any incoming burst, irrespective of the received signal strength. The burst overhead time is a combination of inter-burst guard time and BM-RX settling time. A fast settling DC-coupled BM-RX needs a reset signal at the end of each burst, in order to erase all the information of the previous burst and to prepare the BM-RX for the next burst to come. This reset signal may originate from the medium access control (MAC) layer of the PON, as there the respective timeslots for upstream transmission are allocated, but good system practice avoids time-critical signals crossing the boundary between the PON physical layer and the MAC layer. At 10 Gbit/s, the guard time is substantially longer than the maximum CID sequence that can occur in the burst payload, so one can distinguish the long logic 0 of the guard time from the CIDs in the burst payload of the incoming bit stream. As a result, the BM-RX is able to detect the end-of-burst (EoB) itself, and to automatically generate a reset signal without the need for time-critical signals from the MAC layer. Our research group published a 10 Gbit/s DC-coupled BM-RX with an auto-reset function in [8]. As EoB detection might fail with noisy incoming signals, this paper investigates the robustness of the auto-reset generation at high bit error rate (BER), a situation that occurs when feedforward error correction (FEC) is deployed.
This paper is an expanded version of our presentation on ECOC 2011 [9]. The different building blocks of the BM-RX, namely the APD, BM-TIA and BM-LA, are discussed in more detail in Section 2. In Section 3, the influence of a high pre-FEC BER on the BM-RX auto-reset function is studied for the first time. Section 4 presents the measurement setup and experimental results, similar to [9].
2. 10 Gbit/s DC-coupled BM-RX
Figure 2 depicts the 10 Gbit/s DC-coupled BM-RX configuration. It contains an APD, a BM-TIA and a BM-LA, which are described in detail below. The DC-coupled BM-TIA and BM-LA chips were fabricated in a STMicroelectronics 0.13 µm SiGe BiCMOS process.
2.1 The 10 Gbit/s BM APD-TIA
The 10 Gbit/s BM APD-TIA converts the input current from a 10G APD photodiode into a differential output voltage. Low noise amplification and high overload handling are the main figures of merit. The APD used for this work is an AlInAs/InGaAs APD structure with an excess noise factor F(M) of 3.3 at M=10, as shown in Fig. 3a . Figure 3b illustrates that a 3-dB bandwidth of about 10 GHz is achieved for avalanche gains between 4 and 15, and that the extrapolated gain-bandwidth product is about 150-160 GHz [10].
Fig. 3 (a) Excess noise factor versus multiplication gain of APDs with two doping levels. (b) 3-dB Bandwidth versus multiplication gain of AlInAs/InGaAs APD with 9x1017cm−3 charge doping level.
The 10 Gbit/s BM-TIA incorporates a fast gain control (FGC) and gain-locking function. It achieves a wide dynamic range by three transimpedance gain settings. When a burst has ended, the BM-TIA is reset to a high transimpedance gain ZT,High (65 dBΩ) for maximum RX sensitivity. The single-ended O/E response at high gain ZT,High is measured at TIA’s output P using HF probes (Fig. 4 ) and it shows ~6 GHz 3dB bandwidth. The power of the new incoming burst is measured at the output of the TIA core. As soon as this power exceeds a certain power level, the transimpedance is switched from ZT,High to a middle gain setting of ZT,Mid (48 dBΩ) by switching the feedback resistance of the TIA core. A second gain switching from ZT,Mid to the low gain ZT,Low (44 dBΩ) is set by changing the gain of the single-to-differential convertor, and happens when the received signal power exceeds a second power threshold. This three-step gain switching is accomplished within several nanoseconds. After the gain switching process, and within the burst preamble, the TIA transimpedance gain is locked in order to avoid bit error rate (BER) degradation due to ZT switching inside the burst payload interval. The BM-TIA also performs a coarse threshold compensation (CTC) process, which sets the balance signal of the single-ended to differential converter according to the transimpedance gain settings. This minimizes the DC offset in the TIA output signal at the RX sensitivity level, and helps reduce the settling time of the BM-LA. Figure 2 indicates that the BM-TIA has no reset pin. The reset signal is conveyed from the BM-LA via a common-mode signaling method. The input buffer of the BM-LA alters the common-mode voltage of the BM-TIA output. The BM-TIA senses these common mode changes, so that no dedicated reset signal line is required.
2.2 The 10 Gbit/s BM-LA
The subsequent 10 Gbit/s feedback type BM-LA [11] has two operation modes: a fast decision threshold level detection mode and a slow threshold level tracking mode. When a new burst arrives, the threshold detection circuit first performs fast offset compensation and amplitude recovery. At the end of the preamble, the BM-LA switches to the slow tracking mode, which is crucial to provide a higher tolerance to CIDs. The time constant of the offset compensation loop is set by the bias current of the offset integrator, which is implemented as a low-frequency amplifier with large capacitive loads. The bias current switches between respectively 1 mA and 15 µA for the fast and slow threshold extraction. At the end of the burst, the BM-LA resets the decision threshold to the default state, by discharging the capacitive loads of the offset integrator, and waits for the arrival of a next burst. Therefore, a reset signal is needed for the BM-LA.
The advantage of using two operation modes in the BM-LA is verified by means of simulations. We have simulated the RX settling time and output jitter in the presence of long CIDs for both a BM-LA with one fixed operation mode and for the new BM-LA with two operation modes. A fixed 211-1 PRBS data pattern with inserted 64-, 128-, 256- and 512-bit CIDs was applied in the transient simulation. By using a smaller time constant at the start of each burst, the new design shows ~75% reduction of the settling time, from 200 ns to 41 ns. This significant settling time reduction does not deteriorate the CID tolerance. As shown in Fig. 5 , the proposed 10 Gbit/s BM-LA can handle up to 512-bit of CID by switching the time constant to a larger value. In this way, the proposed BM-RX can achieve simultaneously a fast response and a large CID tolerance. The interested reader can find more details about the implementation of the BM-LA in our previous published paper [11].
Fig. 5 (a) Duty cycle distortion during preamble for 300 mVpp with 150 mV offset, (b) Data dependent output jitter for 20 mVpp input with 10mV offset
3. Auto-reset generation at high BER
In order to guarantee high sensitivity and short overhead time, the transimpedance gain setting of the BM-TIA and the threshold of the BM-LA are reset at the end of the burst. Therefore, an external reset signal is needed. However, when the guard time can be distinguished logically from the maximum CID of the payload, the BM-RX preferably generates the reset signal itself after detecting the EoB. In this way, no time-critical signals must cross the boundary between the MAC layer and the physical layer [6]. The reset generator, published by our research group in [8], detects the EoB when the BM-LA receives a long sequence of logic 0’s without any logic 1. This duration is chosen sufficiently longer than the maximum CID in order to avoid an untimely reset signal during the payload. However, the auto-reset generation will suffer from noise, especially at the high pre-FEC BER. Figure 6 illustrates the influence of high BER in case of [8], where a reset signal is generated after counting n consecutive 0-bits. Every 1-bit that is erroneously received during the guard time causes the counter to restart, resulting in a delayed reset generation. When the time needed to detect the EoB is longer than the guard time, no reset signal is generated. Consequently, the BM-RX might miss the next burst. Hence, the minimum guard time should be chosen carefully.
Therefore the probability of detecting the EoB is calculated versus the guard time. Two probabilities, namely Pn and Prestart, are defined as illustrated in Fig. 6. Pn is the probability of detecting the EoB, or in other words receiving n consecutive 0-bits during the guard time, and is given by Pn = (1-BER)n. Prestart(k) on the other hand is the probability that the counter is restarted after exactly k bits. This happens when the kth bit is erroneously detected as a logic 1 and EoB was not detected before. Thus Prestart(k) can be calculated as:
With PEoB(k) the probability of detecting EoB within k bits. Consequently, the probability of detecting EoB after exactly k bits is given by Prestart(k-n).Pn and thus the probability of detecting EoB within k bits after the end of the preceding burst is equal to:
Figure 7 shows the probability of missing the EoB, thus missing a reset, versus the guard time at 10 Gbit/s for different BERs in case n is chosen equal to 100. Allowing a missed reset in only 1 out of 1010 cases requires a minimum guard time of 20 ns, 43 ns and 69 ns at a BER of respectively 10−10, 10−4 and 10−3. The sudden drops of the curve are due to the small chance of restarting the counters, which is equal to the BER. Note that these simple calculations don’t take into account the time needed to restart the counters.
To make the auto-reset generation more robust at high BER, we can further extend the technique used in [8]. Instead of restarting the counter after a 1-bit fault, we could tolerate a number f faults before the counter restarts again. The idea is to generate a reset signal after receiving n consecutive bits, including a maximum of f 1-bits. In other words, the EoB detection only restarts the counter after receiving f+1 1-bits.
Formula (2) is still valid for evaluating this technique analytically. Pn is now given by . Taking into account the time needed to restart the counter, expressed as r bit periods, Prestart is equal to:
Where NoR is the number of times the counter restarts during the EoB-detection. Each restart of the counter is preceded by a sequence of maximally n-1 bits, containing f 1-bits (as can be seen in the third part of Fig. 6). Div(k,pl) is thus the number of possible divisions of k bits over pl places with f ones and maximally n-1 bits in each place and is given by:
Figure 8 shows the probability of missing the EoB versus the guard time at 10 Gbit/s and BER = 10−4, assuming that the counters are restarted within 2 ns. In order to avoid a wrongly generated reset during the payload, n is set to respectively 100, 155 and 215 for f equal to 0, 1 and 2. As Pn decreases with increasing f, the three curves overlap each other. As n is taken larger to avoid a false reset generation, the actual EoB detection takes more time. Furthermore, the chance of restarting the counter reduces with increasing f, as it is now equal to BERf+1, resulting in a stepped curve as shown in Fig. 8. The required guard time, allowing a missed reset in only one out of 1010 cases, is respectively 51 ns, 50 ns and 45 ns. When allowing 0 bit errors, an extra 7 ns is needed, due to the restart time of the counter. This restart time has less influence when more bit errors are allowed during the detection. Furthermore, the probability of a false reset generation during payload decreases for higher f, e.g. a 215-bit long sequence with only 2 1-bits is unlikely to occur during payload. Consequently, the new proposed reset generation is more robust.
This newly proposed auto-reset generator was successfully implemented in the 2nd version of the BM-LA IC, using a clock counter and a 1-bit counter. Reset is generated after the clock counter exceeds the clock threshold (n). Every time that the 1-bit counter exceeds its threshold (f), the EoB detection is restarted. Both n and f are fully programmable, which makes the auto-reset generation flexible to use. The interested reader can find more details about the implementation of the auto-reset generation in our paper [12].
4. Experimental setup and results
The 10 Gbit/s BM-RX performance was evaluated using the experimental set-up shown in Fig. 9(a) . Two 1.3 µm burst-mode transmitters (BM-TXs) named TX #1 and TX #2, are alternately sending 10 Gbit/s burst packets. TX #1 contains a 1.3 µm electro-absorption modulator (EAM) integrated with a DFB-laser diode. It has an output power of +4.4 dBm and an extinction ratio (ER) of 10 dB. The output optical power of the two BM-TXs can be adjusted by two variable optical attenuators (VOAs), namely VOA #1 and VOA #2 for respectively TX #1 and TX #2. For interference measurements on weak bursts preceded by strong bursts, the power level provided by TX #2 is set at −6 dBm after a two-to-one 3 dB optical combiner, a level close to the APD overload, while only the BER of the bursts emitted by TX #1 is recorded using an Agilent 81250 ParBERT. The 10 Gbit/s burst packets shown in Fig. 9(b) consist of a 51.2 ns preamble and a 1280 ns payload. The guard time between bursts is set to 25.6 ns. The payload is composed of 3 sections of non-return-to-zero (NRZ) 231-1 pseudo random bit sequence (PRBS) data patterns, separated by 2 sequences of 72 CIDs (respectively 72 logic 1’s and logic 0’s), in order to validate the BM-RX’s tolerance to long CIDs. In this measurement setup the ParBERT also generates the reset signal. On-chip auto-reset generation is successfully tested in a 2nd version of the BM-LA IC, as will be presented in [12].
The measured BER curves are displayed in Fig. 10 . The input sensitivity of the BM-TIA with a continuous-mode (CW) LA is −31.9 dBm at a pre-FEC BER of 10−3 and −27.1 dBm at a BER of 10−10 for CW input signals. In the BM-RX back-to-back (B2B) configuration, the measured sensitivity at a pre-FEC BER of 10−3 is −30.8 dBm and the sensitivity at a BER of 10−10 is −26.0 dBm, mainly due to the input sensitivity penalty of the BM-LA. A new version BM-LA with improved sensitivity has been developed and manufactured at the time of writing. With the improved BM-LA sensitivity, we would expect the 10 Gbit/s BM-RX to show a better B2B sensitivity at a BER of 10−10. This will allow the advanced BM-RX to be used without FEC in networks that do not require maximum optical power budget. Thanks to the three transimpedance gain settings within the BM-TIA, the error free input overload level was found to be higher than −5 dBm. This yields a dynamic range of more than 25.8 dB.
Fig. 10 (a) The measured BER curves for TIA+CW-LA, BM-RX B2B, and (b) 2 TX branches; BER vs. different preamble times (right).
In the experiments with 2 branches of BM-TXs, the BM-RX sensitivity measured on the weak burst emitted by TX #1 is −30.0 dBm for the worst case when the output power of TX #2 equals −6 dBm. Thus the BM-RX penalty is 0.8 dB at a loud/soft ratio of 24.0 dB. The BM-RX penalty at a BER of 10−10 was found to be even smaller, and about 0.35 dB. From Fig. 10 (a) one can see that the 51 ns, 76 ns and 102 ns preamble performance is almost identical. A very smooth degradation is observed for the 25 ns preamble. Table 1 summarizes the performance evaluation of the 10 Gbit/s DC-coupled BM-RX. A pre-FEC BER threshold of 10−3 is employed as recommended for the upstream by IEEE 802.3av 10G-EPON.
Table 1. Performance Summary of the DC-coupled BM-RX at 10 Gbit/s
5. Conclusions
A high performance DC-coupled 10 Gbit/s APD-based BM-RX, suitable for symmetric 10G-GPONs, has been demonstrated with a RX sensitivity of −30 dBm at a BER of 10−3 while handling a loud/soft ratio of 24 dB. The 10 Gbit/s BM-TIA applies a three-step fast gain setting, resulting in a high dynamic range of over 25 dB. The DC offset in the LA’s input signal is minimized at the RX sensitivity level by the CTC of the TIA. The residual offset is compensated within the BM-LA, using a feedback offset compensator with switched time constants. As a results, both a very short settling time of only 51 ns and a high tolerance to long sequences of CIDs is achieved.
This paper also presents a new method for the auto-reset generation, allowing one or more bit errors while detecting the EoB at high BERs. A thorough analytical study shows that the required guard time, allowing a missed reset in only one out of 1010 cases, is around 50 ns.
Acknowledgments
This work was supported by the EU-funded FP7 ICT projects MARISE and EURO-FOS. The authors would like to thank STMicroelectronics for providing chipset fabrication, and Sumitomo Electric Device Innovations, Inc for providing 1.3 µm 10G EML devices.
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