1. Introduction

Owing to the environmental concern, reducing network energy consumption has attracted intensive research attentions, and will become more critical as the telecom industry increases its network capacity exponentially [1,2]. Currently, adapting the network capacity to the real-time network traffic has been proposed to reduce energy consumption of telecom networks. This approach can significantly reduce the network energy consumption for two major reasons. First, high-rate network devices consume higher energy as compared to low-rate devices. However, the current network always operates at high rate with large power consumption in order to accommodate the peak-hour traffic. Second, telecom network traffic shows dramatic variations over time as illustrated in the typical daily traffic profile at Amsterdam Internet exchange [3]. Usually, the network capacity is adapted by selectively powering off network elements including network nodes and links when the network traffic drops below certain value [4, 5]. To maximize the number of sleeping network nodes or links for minimum network energy consumption, there have proposed proper high layer or cross-layer processing schemes such as packet forwarding, routing, and traffic grooming (including electric/optical bypass) [6–10].

This paper proposes a novel energy-efficient optical transceiver design which adapts its operating rate to the real-time incoming traffic and its energy consumption. As compared to existing solutions, the proposed approach does not need the upper layer functions, thus simplifying the network control. The main idea is to adaptively enable/disable individual block in parallel processing modules according to the dynamic network traffic load. The target system uses digital transceiver with OFDM (Orthogonal Frequency Domain Multiplexing) as the modulation scheme. As recent studies show that OFDM has become a good candidate for optical communications from access to transport networks [11,12], the proposed approach in this paper provides a promising solution to achieve energy efficiency in future telecom networks.

2. Principles of the solution

Our approach is based on two facts in the system. First, with OFDM, the bandwidth in use can be instantly adjusted, and the sampling rate can be changed accordingly. Second, in high-speed implementation, a system usually contains multiple identical modules to work in parallel. Thus, varying the sampling rate can facilitate putting some modules into the power-saving mode.

2.1. OFDM bandwidth vs. FFT size and the sampling rate

Fast Fourier Transform (FFT) [13] has become a common and efficient way to generate and demodulate OFDM signals in the digital domain. At the transmitter side, inverse FFT (IFFT) is used to convert signals from the frequency domain to the time domain before transmission. Denote X(k) as the frequency-domain signal to be modulated by the kth subcarrier. Then, the corresponding time domain signal is $x(n)=(1/N)\cdot {\sum }_{k=0}^{N-1}X(k)\cdot \mathit{exp}(2\pi \cdot i\cdot k\cdot n/N)$, where n = 0, ... , N – 1. If the lower half bandwidth is used while the upper half frequency subcarriers are all set to zero, we can obtain the time domain signal, i.e., $x^{\prime }(m)=(1/2M)\cdot {\sum }_{k=0}^{M-1}\cdot X(k)\cdot \mathit{exp}(2\pi \cdot i\cdot k\cdot m/M)$, where x′(m) is generated at point x′(m) = x(2m) (m = 0, 1, ... , M – 1), and M = N/2. This is the IFFT equation with only half samples without the consideration of the amplitude difference. This equation shows that if the duration of an OFDM frame is constant, the time-domain signal can be generated using half size FFT with half sampling rate when the bandwidth is reduced to a half. The same principle can be applied to the receiver side which uses FFT to convert the signal back to the frequency domain for processing. Thus, it is feasible to reduce the sampling rate and the processing complexity when a lower bandwidth is enough to accommodate the incoming traffic.

2.2. Hardware implementation architecture

In systems with digital signal processing, signals for high data rate applications such as those above 10Gbit/s usually cannot be generated by simply using the traditional serial processing with one sample per clock cycle. There are two typical designs for high speed OFDM transceivers. First, a single module is used to generate multiple samples in one clock cycle. This is referred to as sample-wise parallelization. Second, multiple and identical instances are used to process in parallel; this is referred to as module-wise parallelization. The former solution requires special design for each link speed and clock frequency such that the resource utilization can be optimized, while the latter one may use existing design with some additional distribution and control modules. As compared to the solution of using dedicated design for key signal processing modules, revising and recycling of previous design with additional distribution and control logic requires much less effort although it is at the cost of slightly increased logic consumption. Therefore, the module-wise parallelization is a more popular solution, and has been extensively used in high-speed systems nowadays.

Usually, the digitizing module, i.e., the analog-to-digital converter (ADC) at the receiver side, works at the rate below 10G samples per second. To meet the requirement of higher throughput such as 100Gbit/s link, multiple sub-ADCs are arranged to work in parallel, with a track (or sample)-and-hold (T&H) module being placed in front of each sub-ADC. The phases of the tracking clocks of these T&H modules are interleaved with each other so as to provide evenly distributed sampling points at a higher sampling rate. Fig. 1 illustrates an example of the high-speed ADC structure containing 4 sub-ADC channels, each of which is connected to one T&H module. The clock generator distributes the clock signal with phase shifts of 0°, 90°, 180°, and 270° to the four T& H modules, respectively. By doing so, the input signal can be evenly sampled.

 

Fig. 1 An example of the high-speed ADC structure

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Attributed to the parallelization of signal processing logic as well as the interleaving of low-speed sub-ADCs, it is possible to power-off or hibernate part of these modules when the required sampling rate is low.

3. Energy efficient transceiver design

Based on the feasibility of individually powering off or hibernating each instance of the parallel modules by using techniques such as power gating [14], we propose an energy-efficient digital transceiver with OFDM as the modulation scheme. Fig. 2 describes the system block diagram of the proposed transceiver.

 

Fig. 2 The system block diagram of the proposed transceiver

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Transmitter: At the transmitter side, a traffic status monitoring module keeps collecting link traffic information by monitoring the corresponding queue length. Note that instant access to queue status has been implemented in most commercially available traffic managers. The traffic information is passed to the bandwidth decision module which adjusts the bandwidth allocation accordingly. The bandwidth can be adjusted every w frames. w is pre-configured based on factors such as the control frame structure and the hardware reaction time. Note that w frames need be greater than the time that takes the module to transit between the asleep status and the active status. In the OFDM modulator which includes the symbol mapping and IFFT conversion modules, the bandwidth allocation information is mapped onto the dedicated control sub-carrier(s) during the symbol-to-subcarrier mapping, and further passed to the receiver. These control subcarriers are located within the lowest frequency range such that they can always be received. The newly-made bandwidth allocation decision is sent to each functional module to enable/power-on or disable/power-off part of its internal parallel blocks in the next w frame. The sample distribution logic inside each functional block segments the samples stream and distributes to the parallel processing modules. When bandwidth decision changes, this logic responds accordingly to re-distribute the segments to those active blocks. For OFDM modulator, the symbol mapping logic will map the input signals onto only those allocated sub-carriers; the IFFT conversion module also adjusts its processing size (number of IFFT points) to provide consistent bandwidth and sampling rate.

Receiver: At the receiver side, during the initialization stage, the input signal is assumed to be with full-bandwidth, and both the ADC and the digital processing logic operate at the full speed. The processing decision module receives the information carried by control subcarriers, and further extracts the control message including the allocated bandwidth information. Then, the receiver is able to track the bandwidth allocated by the transmitter and adjust its functional modules including the sampling rate of ADC according to the specified w value. Consider ADC as an example. When the bandwidth is reduced to a half and there are 2 · k sub-ADCs work actively in interleaved mode, k sub-ADCs can be put in the power-saving mode, and the other k sub-ADCs remain staying in the active mode such that 1/2 of the original sampling rate can be guaranteed. The reduced sampling rate further allows half of the current active signal processing instances stay in the power saving mode.

One advantage of the proposed solution is that the receiver can be blindly started without knowledge of the bandwidth in use. It further implies that no feedback control is necessary from the receiver to the transmitter. The robustness of the system can therefore be enhanced, and the reaction time can be reduced.

Bandwidth allocation: The decision making module at the transmitter side makes its decision according to its internal queue length. Denote q as the queue length, th^l as the lower bound of the queue length to reduce the bandwidth to a half, and th^u is the upper bound of the queue length to double the bandwidth. A simple bandwidth allocation scheme can be as follows. If q < th^l, and the bandwidth being used is not the lowest, the bandwidth is reduced to a half; if q > th^u, and the bandwidth is not fully utilized, the allocated bandwidth is doubled. Figure 3 illustrates the process of adapting bandwidth. At the end of frame i, the transmitter finds that its queue length exceeds the upper bound th^u. Then, it notifies the receiver to double the band-width in frame i + 1. It takes some time for the receiver to switch data rates. In this example, the rate is doubled at frame j, and the switching time equals to j – i – 1 frames. The sampling rate should be doubled at frame j + 1 as well.

 

Fig. 3 An illustration of the bandwidth adaptation process

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4. Performance analysis

Overhead analysis: In the proposed system, additional logic is required for sample distribution/reassembly and power control modules. The control logic takes less than 5% of overall resource, which is negligible as compared to the resource-consuming signal processing logic (e.g., FFT/IFFT). Besides the logic overhead, some bandwidth is required to convey allocated bandwidth information between transmitters and receivers. Consider OFDM signal with 200 subcarriers achieved from 256-point IFFT conversion. If the control information is carried by a single subcarrier in multiple OFDM frames, the bandwidth overhead used for control signals is only 0.5% of the total network bandwidth. Therefore, both the logic overhead and the bandwidth overhead can be negligible in the proposed system.

Power efficiency and delay performances: We investigate the power efficiency and delay performances of our proposed system by simulations. Consider a pair of 100 Gigabit Ethernet transceiver, and a self-similar traffic profile with packet size being uniformly distributed between 64 bytes and 1518 bytes. Receiver can support three data rates: 25Gbit/s, 50Gbit/s, and 100Gbit/s.

In Fig. 4(a), we do not consider the time which takes a transceiver to switch from one rate to another. th^l and th^u are set as 2500 bytes and 15000 bytes, respectively. Traffic transmission in 10 seconds is simulated. Denote T(25), T(50), and T(100) as the time duration that the transceiver operates at 25Gbit/s, 50Gbit/s, and 100Gbit/s, respectively. Denote P(25), P(50), and P(100) as the power consumption of the transceiver when it stays in operates at 25Gbit/s, 50Gbit/s, and 100Gbit/s, respectively. Assume P(25) : P(50) : P(100) = 1 : 2 : 4. With conventional transceivers, the energy consumption in these 10 seconds equals to 10s·P(100). With the proposed energy-efficient transceivers, the energy consumption equals to T(25) · P(25) + T(50) · P(50) + T(100) · P(100). The normalized power saving is then defined as

 

Fig. 4 Simulation results. (a). Performances vs. load (Stabilizing time=0, upper bound=25k bytes, lower bound=2.5k bytes), (b). Performances vs. stabilizing time (load=18.3Gbit/s, upper bound=25k bytes, lower bound=2.5k bytes)

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In real implementations, the modules inside the receiver may take some time to transit between the sleep mode and the active mode. We refer this transition time to as “stabilizing time”. Power consumption of the modules during the stabilizing period is assumed to be the same with that in working mode. In Fig. 4(b), the traffic load is set as 66Gbit/s. Fig. 4(b) illustrates that with the increase of the stabilizing time, the time that the transceiver operates in 25Gbit/s and 50Gbit/s keeps decreasing, and the time that the transceiver operates at 100Gbit/s keeps increasing. When the stabilizing time is as large as 6μs, the transceiver operates at 100Gbit/s most of the time even if the load is only 66Gbit/s since the large stabilizing time prohibits the transceiver to switch down a lower rate once it increases to a higher rate. When the stabilizing time equals zero, the power saving is over 30%. With the increase of the stabilizing time, power saving decreases. When the stabilizing time is as large as 6μs, the power saving is reduced to less than 10%. Although the time that transceivers operate at high rate increases with the increase of the stabilizing time, delay performances generally increases with the increase of the stabilizing time as shown in the figure because the large amount of time that the transceiver spent in switching status cannot be used for data transmission.

5. Conclusion

We proposed an energy-efficient OFDM transceiver which dynamically adjust its power-on individual parallel modules according to the network traffic load for energy saving. The proposed receiver is able to blindly start and track the bandwidth decision made by transmitter without feedback control or higher-layer operation. Simulation results shows that signficant amount energy can be saved especialy when during the off-peak traffic hours with low network traffic load.