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Abstract
This paper presents a single-photon avalanche diode (SPAD) in 55 nm bipolar-CMOS-DMOS (BCD) technology. In order to realize a SPAD having sub-20 V breakdown voltage for mobile applications while preventing high tunneling noise, a high-voltage N-well available in BCD is utilized to implement the avalanche multiplication region. The resulting SPAD has a breakdown voltage of 18.4 V while achieving an excellent dark count rate of 4.4 cps/µm2 at the excess bias voltage of 7 V in spite of the advanced technology node. At the same time, the device achieves a high peak photon detection probability (PDP) of 70.1% at 450 nm thanks to the high and uniform E-field. Its PDP values at 850 and 940 nm, wavelengths of interest for 3D ranging applications reach 7.2 and 3.1%, respectively, with the use of deep N-well. The timing jitter of the SPAD, full width at half maximum (FWHM), is 91 ps at 850 nm. It is expected that the presented SPAD enables cost-effective time-of-flight and LiDAR sensors with the advanced standard technology for many mobile applications.
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1. Introduction
Single-photon avalanche diodes (SPADs) are promising sensor devices enabling single-photon and time-of-flight (ToF) detection, and therefore they have a wide range of applications such as light detection and ranging (LiDAR), space navigation, three-dimensional (3D) face recognition and tracking, fluorescence correlation spectroscopy (FCS), ToF positron emission tomography (PET), etc. [1,2]. In particular, SPADs fabricated in a complementary metal-oxide- semiconductor (CMOS) technology have received a great amount of attention for the applications mentioned above because of their low-cost fabrication and monolithic integration capability. Moreover, with the CMOS scaling, a SPAD-based sensor can provide more functionalities with many transistors, while the fill factor of the SPAD is maximized. Using an advanced CMOS technology also offers an additional benefit to a sensor, in terms of power consumption. This is because advance technology is designed to be more power-efficient than older one, by providing high doped layers with less defects. This can be especially important for sensors in mobile applications that need to operate on a limited power source.
To develop a SPAD in advanced CMOS technology, there have been some attempts using 40∼65 nm nodes [3–6], however, these SPADs show a high dark count rate (DCR), and a low photon detection probability (PDP), because of the reduced depletion width caused by the increased doping concentration with the node scaling. One solution to overcome the performance degradation with the CMOS scaling is utilizing bipolar-CMOS-DMOS (BCD) technology, as it provides lower-doped layers compared to other CMOS technology. In addition, one can improve the PDP performance further with higher excess bias voltage, since high-voltage transistors are available in BCD. Recently, a BCD-SPAD achieving low DCR and high PDP has been reported by using a deep P-well/buried N-well junction [7], but the high breakdown voltage (VBD) over 30 V is a high price to pay as many mobile applications prefer a SPAD having sub-20 V VBD.
In this paper, we present a SPAD based on a shallow junction fabricated in 55 nm BCD technology. We conducted a technology computer-aided design (TCAD) simulation to check the E-field profile of the device at above its VBD and characterized it in terms of I-V, light emission test (LET), DCR, afterpulsing probability (APP), PDP, and timing jitter. With these, we demonstrate that the proposed BCD-SPAD achieves low DCR and high PDP while confining its VBD under 20 V.
2. Device structure and simulation
Figure 1 shows the proposed SPAD structure in 55 nm BCD technology. The SPAD is based on a shallow junction consisting of P + and high-voltage N-well (HVNW) with a deep N-well (DNW) underneath. Thanks to the low-doped HVNW, the device can prevent tunneling noise and improve its PDP, and by utilizing the DNW, it can further enhance its long-wavelength efficiency. The SPAD is designed and fabricated in a circular shape to alleviate the high E-field at the edge of the junction, and P-epi guard ring is implemented at the outside of the junction to prevent the premature edge breakdown. The diameter of the active junction and guard-ring width are 10 µm and 2 µm, respectively.
To verify the effect of the guard ring, TCAD Sentaurus is used to simulate the E-field profile of the SPAD, and the results are shown in Fig. 2. It clearly shows that the premature edge breakdown is effectively prevented by the P-epi guard ring because its doping concentration is much less than the P + layer, and consequently, the E-field is uniformly formed in the intended planar junction between P + and HVNW.
3. Experimental results
The I-V characteristics of the SPAD with and without illumination were investigated with a device parameter analyzer and the results are depicted in Fig. 3. The VBD of the SPAD is about 18.4 V achieving sub 20 VBD.
LET was conducted in order to check the absence of the premature edge breakdown and the device active area as shown in Fig. 4 [8]. As the area emitting light is regarded as the avalanche region, Fig. 4(b), obtained at the excess bias voltage (VEX) of 3 V, clearly demonstrates that a higher E-field than the critical E-field is uniformly formed at the junction of the SPAD, which corresponds well to the result of TCAD simulation shown in Fig. 2.
DCR characteristics were measured with an external passive quenching resistor of 100 kΩ and an oscilloscope, and the results are plotted in Fig. 5. During the measurement, the recharge time of the SPAD was about 1.3 µs. The DCR increases with VEX because the increasing E-field with high VEX enhances the avalanche breakdown probability and the carrier generation rate [9]. Although the SPAD is based on a shallow junction fabricated in an advanced technology node, it achieves excellent DCR performance thanks to the low-doped HVNW available in the BCD technology. It enables a wider depletion region and consequently prevent tunneling noise more effectually. The DCR of the SPAD is just 0.03 cps/µm2 at VEX = 1 V, and it shows a low DCR of 4.4 cps/µm2 even at VEX = 7 V. The inset of Fig. 5 shows measured DCR values at VEX = 7 V with 9 different dies and it implies that the DCR uniformity is good.
Fig. 5. DCR of the BCD-SPAD vs. VEX at room temperature. The inset shows the SPAD DCR values at VEX = 7 V obtaiend from 9 dies.
The DCR characteristics of the BCD-SPAD at different temperatures from -25 to 75 °C were investigated using a temperature chamber as shown in Fig. 6(a). It reveals that the DCR has a higher temperature dependence as the temperature increases. In order to analyze the dominant mechanisms of the DCR at the temperature conditions, activation energies were extracted from the Arrhenius plot as can be seen in Fig. 6(b). The activation energies indicate that trap-assisted thermal generation becomes the primary contributor to the SPAD DCR at above room temperature while tunneling is the main contributor at below room temperature.
Fig. 6. (a) DCR vs. temperature characteristics of the BCD-SPAD at different VEX and (b) Arrhenius plot of the BCD-SPAD at VEX = 7 V.
The afterpulsing characteristics of the proposed device were checked using the inter-avalanche time histogram method as shown in Fig. 7 [8]. In the measurement, inter-avalanche time statistics were collected at VEX = 7 V, with the dead time of 300 ns using an external quenching circuit. The APP of SPAD was estimated as 0.77% when the dead time is 300 ns.
PDP characteristics of the SPAD were measured from 400 to 950 nm at VEX of 1, 3, 5, and 7 V as shown in Fig. 8. Since the afterpulsing phenomenon can result in the overestimation of the PDP values, its afterpulsing probability was already checked as shown in Fig. 7, which confirms that the PDP values were not affected by the afterpulsing. The PDP curves show ripples due to the interference when the light passes through the dielectric layers that have different refractive indices on the top of the SPAD [10]. The peak PDP of the SPAD is 70.1% at 450 nm. Although the PDP decreases as wavelength increases, as many photons are absorbed in the deeper region than in the shallow junction of the SPAD, the PDP in NIR still shows a considerable value, e.g., PDP of 7.2 and 3.1% at 850 and 940 nm, respectively, where many 3D ranging technologies are interested in.
Timing jitter indicates the uncertainty of the time response of the SPAD, i.e., the uncertainty between actual and measured photon arrival time [11]. It was measured using the time-correlated single-photon counting (TCSPC) technique with an 850 nm picosecond pulsed laser when the repetition rate is 20 MHz and the VEX is 7 V. To accurately measure the inter-arrival time between the laser pulse and SPAD pulse, an oscilloscope having high bandwidth and high sample rate was utilized. The measurement results are shown in Fig. 9. It achieves excellent timing jitter performance, 91 ps full width at half maximum (FWHM) and 224 ps full width at tenth maximum (FWTM), including the jitter of the laser and laser driver.
Table 1 shows the performance summary of the proposed BCD-SPAD and comparison with previously reported SPADs fabricated in advanced CMOS technology. Thanks to the BCD technology, the proposed SPAD achieves much better performance in terms of DCR, timing jitter, peak PDP, and PDP at 940 nm when compared to the SPADs fabricated in 40 nm and 65 nm CMOS technology [3–6]. Especially, it is notable that the proposed SPAD shows much lower DCR and much higher PDP compared to the CMOS-SPADs. When it comes to the comparison with the other BCD-SPAD based on a deep junction [7], the proposed SPAD achieves higher peak PDP, while showing comparable DCR. Although the previous BCD-SPAD shows higher PDP at 940 nm, the difference is not significant. Most of all, the proposed device has a great advantage in terms of the low VBD, which is the crucial difference that makes the proposed SPAD more favorable in mobile applications. In other words, the proposed SPAD is the most optimized device for low-power applications among recently reported SPADs fabricated in advanced CMOS technology.
Table 1. Performance summary and comparison with CMOS-SPADs
4. Conclusion
This work presents a high-performance SPAD fabricated in 55 nm BCD technology. The proposed SPAD achieves a low DCR of 4.4 cps/µm2 at VEX = 7 V. It attains a peak PDP of 70.1% and PDP of 7.2 and 3.1% at 850 and 940 nm, respectively, at the same VEX. In addition, the SPAD achieves a good timing jitter, 91 ps FWHM at 850 nm. All the performance is obtained while confining its breakdown voltage under 20 V, which can open the way for SPAD sensors to be utilized in many mobile applications.
Funding
Korea Institute of Science and Technology (2E32242).
Acknowledgments
This work was supported by the Korea Institute of Science and Technology (KIST) Institution Program (Grant No. 2E32242).
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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