1. Introduction

Graphene based optoelectronics is of great interest for the relevant electro-optical properties of graphene, for the technological compatibility of graphene with other materials and because graphene is substantially wavelength independent [1,2]. Single and double layer graphene on Silicon On Insulator (SOI) electro-absorption modulators [3–5], graphene photoconductors, junctions, Schottky barrier and other photodiodes have been demonstrated [1,2]. Nevertheless, graphene based electro-optical devices do not match the state of the art of silicon photonics yet, as for instance in terms of modulation bandwidth. In fact there are a number of parameters/technological processes that have to be either understood and/or optimized. One of the main improvement concerns graphene contact resistance. A lot of work has been done on ohmic contact formation on graphene [9,10] and the optimum technology has to be included in the device fabrication. Robust and reliable integration with existing technologies, as for instance SOI based technology, is also a task in progress.

Graphene based phase modulators have been proposed too [6–8], but there is no experimental demonstration yet. In the present paper we aim at designing graphene based phased modulators. Figure 1 shows the structures we propose: single graphene layer phase modulator (Fig. 1(a)), and double graphene layer phase modulator (Fig. 1(b)).

 

Fig. 1 Schematic cross-section views of the single (a) and double (b) graphene layer modulators.

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In the single layer configuration a Graphene-Insulator-Silicon (GIS) capacitor is formed on a straight SOI ridge waveguide. In the double layer a Graphene-Insulator-Graphene (GIG) capacitor is formed on top of a straight SOI channel waveguide. In both structures graphene optical properties are modulated by applying a voltage across the capacitor. The single layer graphene phase modulator exploits the combination of index of refraction variation provided by graphene and by the plasma dispersion effect in silicon (Si) due to the carriers accumulated at the interfaces of the capacitor formed by Si, thin dielectric spacer, and graphene. Conversely in the case of the double graphene structure the accumulation of carriers on the graphene layers is the only responsible for the effective index variation in the Si waveguide.

In the first part of the paper we introduce the optical model of graphene. We used a temperature dependent model including the electron scattering parameter in order to account for the quality of the layer [11]. Next we discuss the electrical design of the proposed devices in order to obtain a bandwidth larger than 10 GHz. Finally we present the optical modulation performance. We will show that graphene based phase modulators is an efficient alternative to Si modulators. Modulation voltage-length product (V_πL) much lower than the typical value of 2Vcm of pn junction plasma dispersion effect in SOI waveguides [12] or 0.2Vcm of the SISCAP modulator [13] can be achieved.

2. Electro-optical models

In this section we briefly introduce the model we use to describe the optical properties of graphene and Si when the application of an electric field changes the free carrier density.

2.1 Electro-optical model of Graphene

Optical properties of graphene have been studied in several works and the dependence of graphene optical conductivity on inter- and intra-band transitions has been derived analytically at 0K as well as at 300K [14–17]. Recently, Chang et al [11] experimentally demonstrated that the complex optical surface conductivity of graphene in the near infrared may be fitted by the following closed formula:

When computing optical modes of structures encompassing graphene, two possible approaches can be followed. In the first one, graphene is treated as a real 2D layer, which imposes a discontinuity of the in-plane magnetic field: $\Delta {\overrightarrow{H}}_{\parallel }=\sigma {\overrightarrow{E}}_{\perp }$. Here, subscripts $\parallel$ and $\perp$ denote in-plane and out-of-plane field components, respectively, and σ is given by Eq. (1). In a different approach, graphene can be treated as an equivalent 3D layer having out-of-plane dielectric constant of graphite, and in-plane dielectric constant given by

Figure 2 shows the optical surface conductivity (Fig. 2(a)) and dielectric constant (Fig. 2(b)) versus Fermi level of a graphene mono-layer at room temperature for free-space wavelength λ = 1550nm (ηω = 0.8eV), as derived through Eq. (1) and (2) respectively.

 

Fig. 2 Graphene optical surface conductivity normalized to the universal conductivity σ₀ ≈6.09 Ω⁻¹ (a) and dielectric constant (b) versus Fermi level at T = 300K for an optical field with free-space wavelength λ = 1550nm (ηω = 0.8eV). In both the figures, the real part of the displayed quantities is on the left y-axis, and the imaginary part on the right y-axis.

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The real part of the dielectric constant (left axis of Fig. 2(b), blue curves), i.e. phase term, is essentially independent on the intra-band scattering rate. Whereas, the imaginary part of the dielectric constant (right axis of Fig. 2(b), red curves), i.e. the absorption term, may vary by orders of magnitude depending on the relaxation time, i.e. on the material quality. In particular, we observe that the imaginary part of the dielectric constant decreases significantly for Fermi levels |μ|>0.4eV. This fact can be explained as follows: when a photon impinges on graphene, its energy may be absorbed to provoke an inter-band transition of a free carrier. Whether an electron or a hole is involved in this process depends on the sign of the Fermi level. According to the Pauli’s blocking principle, this transition can only occur if |μ|<ηω/2, at λ = 1550nm, |μ|<0.4eV. For an ideally impurity free graphene sheet (τ→∞) at zero temperature this would reflect in an abrupt variation of absorption. At room temperature, a more gradual transmission from absorption to transparency can be expected. Finite values of the relaxation time further alter this picture, as significant absorption due to intra-band scattering interactions takes place.

Figure 2(b) also shows that the phase term, real part of the dielectric constant of graphene, can be changed when the Fermi level is varied. This can be done by means of the electric field effect [24,25]: if we consider a simple MOS-like structure, as for example in Fig. 1(a), the Fermi level of graphene can be modulated by applying a voltage across the capacitor. In fact, the external voltage causes the accumulation of charges at the armatures of the capacitor thus changing the carrier density on graphene and consequently the Fermi level as [24,25]:

2.2 Electro-optical model of Si

In the single layer geometry (Fig. 1(a)) carriers accumulate both at the graphene-insulator and at the silicon-insulator interfaces when a voltage is applied to the GIS capacitor. In order to accurately design the modulator, the effect of the charges on the refractive index of Si needs to be taken into account too. In the present paper, we performed electrical TCAD (Technology Computer Aided Design) simulations of the device shown in Fig. 1(a) in order to evaluate the carrier distribution at the silicon-insulator interface. Graphene is modeled as an equivalent metal with work function equal to 4.5eV [26], the insulator is a 10nm thick layer of Silicon Nitride (Si₃N₄, dielectric constant of 7.5 [27]), Si is p-type doped with hole concentration of 5∙10¹⁷cm⁻³. These values arise from electrical and optical design considerations that will be discussed in greater details below. Figure 3 shows an example of the numerically computed carrier density distribution versus applied voltage. The abscissa runs along the direction normal to the insulator layer, at the middle section of the GIS capacitor, as depicted in the inset.

 

Fig. 3 Hole distribution at the middle of the Silicon-Si3N4 interface at different gate voltage applied to the graphene-Si3N4-Silicon capacitor. Inset: simulated device cross-section.

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The effect of free carriers on the propagation constant of the optical mode is modeled through Soref’s formula at λ = 1550nm [28,29]:

3. Device design

In this section we discuss the design of both the single and double layer graphene modulator. We first comment on the choice of the insulator according to static operations. Later on, we investigate on Si doping, as well as on the optimal location and shape of the electric contacts in order to maximize the device analog bandwidth.

3.1 Insulating layer

Pure phase modulator should exhibit low propagation losses across the whole span of operating conditions. In this respect, use of Fermi levels |μ|>0.5eV is compulsory in order to avoid graphene absorption due to inter-band transitions. This requirement reflects on the choice of the insulating layer of the capacitor formed either by a single graphene sheet and Si, or by two graphene sheets.

Through Eq. (3) a graphene charge density n_s = 2∙10¹³cm⁻² is needed in order to shift the Fermi level to |μ| = 0.5eV. This corresponds to an electric field across the capacitor insulator:

3.2 Electrical bandwidth

In the previous section we envisaged Si₃N₄ as a suitable dielectric for the DC bias. Here we discuss the dynamic behavior of the modulators in order to determine the device geometry.

Figure 4 shows the equivalent electrical circuit of the proposed devices. Both the single and the double layer configuration can be modeled as a simple RC low pass filter.

 

Fig. 4 Equivalent electric circuits for the single (panel a, upper row) and double (panel b, lower row) graphene layer modulators. R_c^G, R_s^G, R_s^Si, C_ox^SiN, C_p^SiO2 are the graphene contact resistance, graphene series resistance, Si series resistance, Silicon Nitride capacitance and Silicon Oxide parasitic capacitance, respectively.

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In these equivalent circuits, the resistance is the sum of different contributions: the Si series resistance R_s^Si in the single layer configuration, the graphene series resistance R_s^G and contact resistance R_c^G in both the single and double layer structures. The capacitance is mainly determined by the Si₃N₄ dielectric C_ox^SiN. However, in the single layer case parasitic C_p^SiO2 due to the overlap of graphene on the waveguide cladding can increase the total capacitance.

3.2.1 Single Graphene layer modulation speed

We performed TCAD simulations of the equivalent MOS structure shown in Fig. 1(a). Typical design rules of standard silicon photonic processes were used for these simulations. In particular, we assumed a single mode TE ridge waveguide on standard 220nm SOI platform. The waveguide core is 480nm x160nm on top of a 60nm thick slab, over 2μm thick SiO₂ BOX (buried oxide). We assumed 10nm of Si₃N₄ between the Si core and the graphene layer. The Si waveguide is conveniently doped in order to reduce the R_s^Si. An equivalent p-type doping concentration of 5∙10¹⁷cm⁻³ was used. This is a typical value in pn junction Si modulators [31,32]. We assumed p-type doping because holes provide larger free carrier effect than electrons on the refractive index of Si (see Eq. (5). We also used a p + doping (10¹⁹cm⁻³) in order to electrically access the Si waveguide with negligible contact resistance. The distance between these highly doped regions and the waveguide core was set equal to 500nm as a tradeoff between series resistance and optical losses. Silica cladding surrounds the whole structure.

As mentioned above, in all the electrical simulations graphene was modeled as a metal with work function equal to 4.5eV, sheet resistance R_□^G and contact resistance R_c^G. These last parameters are object of many studies and investigations. We referred to typical results reported in literature. In particular, R_□^G = 100-500Ω/□ was reported when the carrier density on the graphene layer is in the order of 10¹²-10¹³cm⁻² (as it was discussed in section 3.1 this is our range of interest) [33,34]. As for the contact resistance R_c^G_, this still represents one of the major challenges in graphene technology. Values in the range 100-1000Ωμm have been reported, depending on the specific metal and process used to form the contact [9,10,35–38]. In this work we assumed R_□^G = 500Ω/□ and R_c^G = 1000Ωμm.

We assumed the electrode configuration of Fig. 1(a) with two metal electrodes on top of the graphene sheet and two metal electrodes on the Si slab on both sides of the waveguide core. In such configuration the two electrodes give rise to a parallel scheme allowing for a reduction of the series resistance contribution by a factor of two. We considered a 2μm metal width for each electrode and 1μm distance between the graphene electrodes and the waveguide core edge on both sides.

Figure 5 shows the numerically evaluated device small signal capacitance C and series resistance R per unit length at low frequency (1kHz) when a voltage is applied to the graphene electrodes.

 

Fig. 5 Small signal parameters per unit length at low frequency (1kHz) versus applied voltage. a) Capacitance: red curve overall capacitance including lateral parasitic capacitors, blue curve minimum capacitance due to the only Silicon Nitride gate. b) Series resistance: red curve overall resistance with graphene sheet resistance R_□^G = 500Ω/□ and R_c^G = 1000 Ωμm, blue curve Si series resistance.

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We considered negative voltages in order to obtain hole accumulation at the Si₃N₄-Si interface. At this stage we assumed V_DIRAC = 0V because this parameter will introduce only a shift of the curves without effects on the evaluated values. In Fig. 5(a) we observe lower capacitance at low voltages because of the carrier depletion at the Si₃N₄-Si interface due to the difference between the work functions of graphene and Si. This in turn causes an equivalent broadening of the electric field region (Si₃N₄ dielectric and Si depletion region), resulting in a lower capacitance. The overall capacitance (red curve) increases rapidly in the first 2V, then saturates at about 47pF/cm. This value is determined by the sum of the gate capacitor and the lateral parasitic capacitors formed by the overlaying graphene on top of the SiO₂ cladding at both sides of the waveguide core (as depicted in Fig. 4(a)). The total parasitic capacitance is C_p^SiO2 = 16.2pF/cm and it is voltage independent. The parasitic effects of the lateral capacitors can be mitigated by increasing the distance between the graphene sheet and the Si slab in the region outside the waveguide. This way, the overall capacitance could be reduced down to 31pF/cm (blue curve).

Figure 5(b) shows that the series resistance R has a weak dependence on the voltage because of the carrier modulation in the waveguide core. The major contribution to R is the Si series resistance mainly due to the slab doping. From Eq. (6) the operating voltage of the phase modulator will be V_op<-5V with 10nm of Si₃N₄. At −6V the contribution of Si is about 0.27Ωcm. Graphene contribution to the series resistance is mainly due to the contact resistance. In our case the overall R is about 0.37Ωcm at −6V. Lower contact resistance, for example 100Ωμm, can reduce the overall R down to the limit value determined by the Si series resistance.

With the extracted value we can estimate a worst case analog bandwidth of 9GHz at −6V mainly due to the parasitic capacitors. If the parasitic effect is reduced the analog bandwidth increases up to 14GHz, limited by the 1000Ωμm graphene contact resistance. With further improvements on lower contact resistance, for example R_c^G = 100Ωμm the analog bandwidth sets at 19GHz. Further optimizations can be the reduction of the Si series resistance by using thicker slabs, shortening the distance between the high doping region and the waveguide core or by introducing a middle level doping. These solutions can improve the analog bandwidth, but also give rise to larger optical losses.

3.4 Double Graphene layer modulation speed

In the double graphene layer modulator scheme, the RC bandwidth is limited by the graphene sheet and contact resistance and by the capacitance of the parallel-plate GIG capacitor.

The series resistance equals the sum of the top and bottom sheet and contact resistance. We refer again to Fig. 4 and assume R_□^G = 500Ω/□ and R_c^G = 1000 Ωμm. With metal contacts spaced 1μm from the edge of the waveguide core the overall graphene series resistance is about 0.35Ωcm. Assuming R_c^G = 100Ωμm the series resistance reduces to 0.17Ωcm.

The capacitance due to overlapping of the graphene layers can be the real limiting factor for the double-layer scheme modulator. If the graphene layers are carefully patterned so that they only overlap over the waveguide core as in the bottom row of Fig. 4, the capacitance is 31pF/cm, as discussed in the previous section. This gives rise to an analog bandwidth of 15GHz for a contact resistance of 1000Ωμm, and 30GHz when the contact resistance is 100Ωμm. When graphene patterning is less accurate, the overlap grows, leading to a larger capacitance. For example, a misalignment of 0.5μm would increase the gate area by a factor of 3. In such case the analog bandwidth would reduce down to about 5-10GHz depending on the contact resistance.

4. Optical modulation

Here we discuss the optical modulation properties of the phase modulator obtained with the geometrical and physical parameters discussed in the previous section. We focus on the fundamental TE mode. Similar considerations can be extended to the fundamental TM mode. Nevertheless, we consider TE polarization because of compatibility with the standard single mode TE silicon photonics.

All the results are expressed in terms of V-V_DIRAC without loss of generality. In fact, the flat-band condition will introduce a shift of the curves without affecting the operating electric field that depends only on the surface carrier concentration required for the desired Fermi level shift.

4.1 Single layer phase modulator

Figure 6 shows the numerically computed losses (Fig. 6(a)) and effective index change (Fig. 6(b)) of the fundamental TE mode of the single layer graphene phase modulator shown in Fig. 1(a) versus the applied voltage V-V_DIRAC at λ = 1550nm and T = 300K.

 

Fig. 6 a) TE fundamental mode optical losses of the single layer configuration of Fig. 1(a) at λ = 1550nm and T = 300K versus applied voltage at different graphene relaxation time: 12fs, 100fs, infinite. In the inset the single contributions due to Si and graphene. b) TE fundamental effective index change of the single layer configuration of Fig. 1(a) at λ = 1550nm and T = 300K versus applied voltage and single contributions due to Si and graphene (relaxation time does not affect the effective index).

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In Fig. 6(a) we show that the modulator exhibits high losses (up to 530dB/cm) at low voltage. As expected, losses decrease for V-V_DIRAC<-5V. In the inset of Fig. 6(a) we artificially isolated the single contribution due to Si and graphene to optical losses. As expected, a decrease of the applied voltage has opposite effects on Si and graphene: Si losses increase due to increasing carrier concentrations whereas the opposite occurs in graphene as the Fermi level shifts towards the region of forbidden inter-band transitions. This way, an optimum operating voltage is found as a tradeoff at about V-V_DIRAC = −6,5V. At this bias point the overall modulator losses depend on the graphene quality. From Fig. 6(a) we conclude that for relaxation time larger than 100fs modulator losses are mainly limited by the Si losses and set at about 33dB/cm for V-V_DIRAC = −6,5V. Nevertheless, for 10fs relaxation time optical losses increase up to 65dB/cm at the same bias.

In Fig. 6(b) we show the effect of Si and graphene on the TE mode effective index variation. In particular, the free carrier effect in Si exhibits a monotone variation, whereas graphene variation resembles the slope of the dielectric constant of Fig. 2(b): it increases for V-V_DIRAC>-3,6V (|μ|<0.4eV) and decreases for V-V_DIRAC<-3,6V. At the operating voltage we are interested in, namely V-V_DIRAC≈-6,5V, the effects of Si and graphene sum up, finally leading to a larger index modulation.

Figure 7 shows the extracted phase shift in multiples of π versus applied voltage when the modulator is biased at V-V_DIRAC = −6,5V.

 

Fig. 7 Single layer modulator phase shift versus applied voltage when biased at V-V_DIRAC = −6,5V, λ = 1550nm and T = 300K. Blue curve: Si free carrier phase shift. Black curve: graphene phase shift. Red curve: modulator overall phase shift.

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The effect of free carriers in Si improves the phase response of the device leading to an overall V_πL = 0.26Vcm with good linearity in the range −2π ÷ 2π. In addition, as shown in Fig. 6(a), amplitude modulation in the operating range around the bias point is very small allowing pure phase modulation.

4.2 Double layer phase modulator

Figure 8 shows the numerically computed losses (Fig. 8(a)) and effective index change (Fig. 8(b)) of the fundamental TE mode of the double layer graphene phase modulator shown in Fig. 1(b) versus the applied voltage V-V_DIRAC at λ = 1550nm and T = 300K.

 

Fig. 8 a) TE fundamental mode optical losses of the double layer configuration of Fig. 1(b) at λ = 1550nm and T = 300K versus applied voltage at different graphene relaxation time: 12fs, 100fs, infinite. b) Red curve: TE fundamental effective index variation of the double layer configuration of Fig. 1(b) at λ = 1550nm and T = 300K versus applied voltage. Blue curve: Single layer graphene contribution to phase modulation as extracted from Fig. 6(b).

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In Fig. 8(a) we show that graphene quality determines the modulator losses. At low voltage, modulator losses are independent of the relaxation time because inter-band transitions dominate. The total loss is in the order of 1370dB/cm. At higher voltages, depending on material quality, the optical losses decrease and saturate. In particular for τ = 12fs the minimum loss is about 86dB/cm at V-V_DIRAC = −7,2V, while for τ = 100fs the minimum loss is about 12dB/cm at V-V_DIRAC = −7,8V.

In Fig. 8(b) we show the TE mode effective index change of the double layer graphene modulator (red curve), as compared to the same effect obtained with a single layer graphene (blue curve, see also Fig. 6(b)). As expected the effect of two layers is that of enhancing the effective index modulation. Figure 9 shows the extracted phase shift in multiples of π versus applied voltage when the modulator is biased at V-V_DIRAC = −7,8V.

 

Fig. 9 Double layer modulator phase shift versus applied voltage when biased at V-V_DIRAC = −7,8V, λ = 1550nm and T = 300K

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The double layer phase modulator exhibit V_πL = 0.16Vcm with good linearity in the range −2π ÷ 2π with small contribution of amplitude modulation. The V_πL could be further improved by operating at lower biases because of the steeper index variation slope near V-V_DIRAC = −6V, as shown in Fig. 8(b). For example V_πL = 0.1Vcm could be obtained at V-V_DIRAC = −6V. Nevertheless, at those biases large amplitude modulation occurs as shown in Fig. 8(a), thus limiting pure phase operations.

5. Conclusion

In conclusion we presented the detailed design of phase modulators based on single and double graphene layer for TE modes in ridge (for the single layer graphene) and nanowire (for the double layer graphene) Si waveguides. The large electro optical contribution of graphene leads to an advantage in terms of modulation efficiency, size and insertion loss. In Table 1 we summarize the main efficiency-loss figure of merit (FOM) [39] of the proposed devices compared to other Si phase modulators reported in literature.

Table 1. Comparison of state of the art Si and proposed graphene on Si modulators

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Owing to the large variation of dielectric constant that is available in graphene, the proposed devices exhibit V_πL products comparable with the SISCAP modulator (single layer modulator) and even lower (double layer modulator). At the same time, since the larger is the carrier density on graphene the more transparent it becomes, graphene has the unique property of behaving exactly in the opposite way of Si as far as optical absorption is concerned. This in turn allows obtaining lower insertion losses in graphene modulators than in SISCAP. As a result, the overall figure of merit of the proposed modulators (FOM in the last column of Table 1) sets well below those of any other devices available to date. In order to provide a full comparison with state of the art devices we estimated the energy consumption of the proposed devices in a MZI intensity modulation configuration. The double layer graphene phase modulator could provide energy consumption as low as 0.2pJ/bit when the V-V_DIRAC = −6V with CMOS value of 1V peak to peak driving signal. This value sets among the lowest for MZI based intensity modulators.