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The integration of 2-D optoelectronic interfaces with silicon chips, employing what is known as smart-pixel technology, can overcome many of the foreseen limitations of conventional interconnects [1]. The solution is to provide free-space optical interconnects operating at the silicon on-chip clock-rate and with the numbers required to yield the necessary aggregate bandwidth. To investigate the application of this approach to parallel information processing we have been building an optoelectronic data sorting machine as a system demonstrator. The architecture of the optoelectronic sorter and the design of the components was described previously [2].
© 1998 IEEE
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