Abstract

Optical interconnection techniques have been suggested to reduce signal skew in clock distribution for silicon VLSI chips. One optical approach for clock distribution is to holographically map an optical signal from an off-chip source to several photoreceivers within small functional cells on a chip surface. Within each functional cell, the clock is distributed via short surface wires with negligible delays. In such a system, there are two sources of timing uncertainty: a static uncertainty due to fabrication-related variation of transistor parameters between identically drawn receivers on a chip and a timing jitter due to phase noise at each receiver.

© 1987 Optical Society of America