Abstract

Programmable optoelectronic multiprocessor (POEM) architecture is based on wafer-scale integration of optoelectronic processing elements (PEs) and free-space optical interconnects.¹ The strength of POEM machines comes from their efficient implementation of interconnections and the large degree of parallelism that is inherent in free-space optical interconnections. An important architectural feature of such a parallel computer is its interconnection network. An interconnection network is a system of optoelectronic PE switches and free-space optical links that interconnect processors in a parallel computing system. The complexity of the PE switch determines the tradeoff between electronic and optical interconnects. Previously, we have designed a POEM perfect-shuffle interconnection network using 22 PE switches and have compared its performance with a VLSI-based perfect shuffle.² In this paper we extend our comparison to include larger PE switches (e.g., 44,1616, etc.), as well as and 22 PE switches realized by using optical gates, as is done in symbolic substitution. The basis of our comparison include system speed, volume, footprint area, and power consumption. In addition, we determine the optimal PE switch size for given optoelectronic technology parameters.

© 1990 Optical Society of America