Abstract

In recent years the literature in optical computing has grown vastly and diversified widely. Many architectures have been proposed and many different devices fabricated, but remarkably few optical processors have been constructed. One reason for this is the lack of a close link between architectural considerations and device fabrication considerations. A tolerance design strategy can provide this link and enable comparative evaluation of different systems. In this paper a strategy is presented for the tolerance design of prototype optical computing circuits containing programmable logic arrays, full adders and threshold elements [1,2,3].

© 1989 Optical Society of America