Abstract
A novel memory optical test solution is proposed and experimentally
evaluated for at-speed DDR2-SDRAM test using a commercial automatic test
equipment (ATE). Combination of an optical signal splitting scheme and
SerDes (Serializer/De-Serializer) technique based on FPGA (Field
programmable gate array) allows the high-speed multi-parallel memory test
with reduced channel resources. Owing to the SerDes, optical fiber channels
are reduced by more than 87 percent and the number of optical modules
including transmitter/receiver dramatically decrease to 95 percent, compared
with a conventional optical test interface system. Furthermore, the proposed
system can optically expand the tester resource by 4 times using a 1$\,\times\,$4 optical splitting scheme. We evaluated the signal integrity of
28 layer PCB operating at 3.125 Gbps with three-dimension electromagnetic
simulation to obtain more reliable system for memory testing. Consequently,
for the first time to the best of our knowledge, we realized an optical
SerDes interconnect system for a memory test tester and demonstrated an
actual write/read function test of DDR2-SDRAM.
© 2009 IEEE
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