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Abstract
By using the flip-chip bonding technology, a high performances 3D-integrated silicon photonics receiver is demonstrated. The receiver consists of a high-speed germanium-silicon (Ge-Si) photodetector (PD) and a commercial linear transimpedance amplifiers (TIA). The overall 3 dB bandwidth of the receiver is around 38 GHz with appropriate gain. Based on this 3D-integrated receiver, the 56, 64, 90, 100 Gbit/s non-return-to-zero (NRZ) and 112, 128 Gbit/s four-level pulse amplitude (PAM-4) modulation clear openings of eye diagrams are experimentally obtained. The sensitivities of -10, -5.2 dBm and -6.6, -2.7 dBm were obtained for 112 Gbit/s NRZ and 160 Gbit/s PAM-4 at hard-decision forward err correction (HD-FEC,3.8 × 10−3) and KP4 forward err correction (KP4-FEC,2 × 10−4) threshold, respectively. Additionally, the lowest power consumption of this receiver is about 1.2 pJ/bit, which implies its huge potential for short-reach data center applications.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
The ever-increasing data generated by cloud computing, internet traffic, artificial intelligence and 5 G mobile communications, have been driving demand for high energy efficiency, high-speed and low-cost data center interconnect solutions [1]. Silicon photonics is an attractive technology to realize large scale photonics-electronics integration with high bandwidth, large volume, high energy efficiency, and complementary metal-oxide semiconductor (CMOS) compatibility, which might satisfy the growing requirements of data centers [2]. The photonics-electronics integration on a silicon chip has been shown to be feasible and powerful [3,4]. However, the mismatch of specialized and optimum process nodes, will lead to suboptimal performances of the photonics and electronics devices. Hybrid integration of separate photonic and electronic chips, allow for separate roadmaps and offer greater flexibility for performance optimization [5]. The typical hybrid integration technology of photonics and electronics chips are based on the wire bonding and flip-chip bonding process. Compared with wire bonding, the flip-chip bonding technology features higher density, and lower capacitive, resistive, and inductive parasitics, which is very beneficial to realize high bandwidth and large scale three-dimensional (3D) integration chiplets [6,7]. The 3D integration is a technique that the electronic integrated circuit (EIC) is mounted on top of the photonic integrated circuits (PICs) using copper pillars (Cu-Pi) or vice versa, which is promising to reduce size and cost while maximizing performances. A 3D-integrated silicon photonics transmitter operating at 100 Gbit/s is demonstrated with power efficiency of about 2 pJ/bit [8,9]. The 3D-integrated 112 Gbit/s four-level pulse amplitude (PAM-4) optical transmitter based on silicon photonic microring modulator, on-chip laser, and co-packaged 28-nm CMOS driver is also presented by Li and co-authors [6]. More recently, a 224 Gbit/s 3D-integrated CMOS-silicon photonics transmitter is experimentally demonstrated with a real power efficiency down to the sub pJ/bit regime [10]. At high-speed signal reception side, various silicon photonics photodetectors and receivers are also experimentally demonstrated [5,11–17]. Up to now, the highest operation rate reported for 3D-integrated silicon photonics receiver is 112 Gbit/s PAM-4 with a power consumption of 2.8 pJ/bit [18]. To further satisfy the practical application requirement, the limitations of both operating speed and power consumption should be mitigated.
In this work, by employing the flip-chip bonding technology, a 3D-integrated silicon photonics receiver which consists of a high-speed germanium-silicon (Ge-Si) photodetector (PD) and a commercial linear transimpedance amplifiers (TIA) is demonstrated. The optical receiver is packaged with standard singe mode fiber. When the TIA has a good balance between the bandwidth and gain, the overall 3 dB bandwidth of receiver is around 38 GHz. Based on this 3D-integrated receiver, the 100 Gbit/s non-return-to-zero (NRZ) and 128 Gbit/s PAM-4 modulation clear openings of eye diagrams are experimentally obtained. With the aid of off-line digital signal processing (DSP), the sensitivities of -10, -5.2 dBm and -6.6, -2.7 dBm were achieved for 112 Gbit/s NRZ and 160 Gbit/s PAM-4 at hard-decision forward err correction (HD-FEC), i.e., bit-error-rate (BER) of $3.8 \times {10^{\textrm{ - }3}}$ and KP4 forward error correction (KP4-FEC), i.e., BER of $2 \times {10^{\textrm{ - 4}}}$ threshold, respectively. The lowest power consumption is about 1.2 pJ/bit. This makes the flip-chip silicon photonics receiver very promising for realizing high-performance and low-cost 3D integration chiplets.
2. Design and fabrication of a 3D-integrated silicon photonics receiver
The 3D hybrid integration technique features low power consumption, high-density functionalities, and high-yield manufacturing. In this work, based on the separately electronic and photonic chips, the 3D-integrated receiver is implemented by flip-chip bonding, as shown in Fig. 1. The receiver consists of high-speed Ge-Si PD and commercial linear TIA. The PD with vertical NIP junction is fabricated in commercial 90 nm silicon photonics platform [16]. As shown in Fig. 1(a), the high-quality 500 nm thickness Ge film is epitaxially grown on the 0.22 µm-thick Si through a low-pressure chemical-vapor deposition (LPCVD) process, with its top 100 nm ion implanted by N + for ohmic contact. The width and length of Ge are about 4 µm and 20 µm, respectively. The concentrations of N + and P + are optimized to be around $2.8 \times {10^{18}}c{m^{ - 3}}$ and $1.3 \times {10^{18}}c{m^{ - 3}}$. As shown in Fig. 1(b), the light was coupled in via Si edge-coupler based on suspended spot size convert (SSC) structure with -3.0 dB/facet coupling loss. The single-end input and differential output TIA is a commercial electronic chip with typical 3 dB bandwidth of 35 GHz [19]. As shown in Fig. 1(c), the TIA chip was mounted onto the silicon photonics platform chip by Au-bump thermos-sonic bonding. The diameter and height of the Au bumps were approximately 50 µm and 20 µm, respectively. In the test process, the photonics chip is packaged with standard single mode fiber. The packaged optical losses of fiber are about 1.5 dB. The DC bonding wires are used to supply for PD and TIA.
Fig. 1. (a) Cross-sectional view of Ge-Si PD; (b) Optical microscope of the fabricated Ge-Si PD; (c) Photograph of 3D-integrated silicon photonics receiver.
3. Experimental results
3.1 Small-signal measurements
Firstly, the small-signal (S21 and S11) RF measurements was implemented to experimentally verify the 3 dB optoelectrical (OE) bandwidth of a single Ge-Si PD. The calibration of the high-speed RF trail was used to consider the contributions from GSG probes and coaxial cables. The small-signal measurement setup is depicted in [20]. The bandwidth test experiments were achieved by collecting the response of the S21 transmission parameter in the Lightwave Component Analyzer (LCA, Keysight N4373D) tool versus frequency. As shown in Fig. 2(a), the 3 dB bandwidth of Ge-Si PD is about 35 GHz under -2.2 V bias voltage. The typical internal responsivity is evaluated to be 0.85 A/W at 1310 nm. By fitting the S11 scattering parameter data to the small-signal RC-model, the intrinsic junction capacitance of 25 fF is obtained, which is beneficial to the matching of TIA. Then, the TIA is stacked on the Ge-Si PD chip by using flip-chip bonding technology. Finally, the overall OE performances of the 3D-integrated optical receiver with different RF power of LCA are investigated, as shown in Fig. 2(b). In the OE performance test process, the TIA is work in the automatic gain control (AGC) mode and input optical fiber power is about -3.5 dBm. Under -27 dBm RF power, the TIA is operated in high gain mode with 3 dB bandwidth of 18 GHz. Increasing the RF power to -9 and 0 dBm, the TIA achieves a good balance between the bandwidth and gain. The overall 3 dB bandwidth of receiver is around 38 GHz. Further increasing the RF power to 10 dBm, the gains of TIA is very small, but with a very high 3 dB bandwidth of 50 GHz for the receiver.
Fig. 2. (a) Measured small signal (S21) performance of the Ge-Si PD at -2.2 V bias. (b) Measured small signal (S21) performance of the 3D-integrated optical receiver (PD + TIA) under -27, -9, 0, and 10 dBm RF power at -2.9 V bias.
3.2 Eye diagram measurements
As shown in Fig. 3, the setup of high-speed eye diagrams and BER measurements are similar to [21]. The high-speed RF signal with word length of 215-1 pseudo random bit sequence (PRBS) data streams is generated by a 256 GS/s arbitrary waveform generator (AWG). After amplified by 60 GHz driver, the RF signal is sent to the thin film lithium niobite on insulator (TFLNOI) Mach-Zehnder modulator, which has a 3-dB bandwidth of 64 GHz after packaging. The modulated high-speed optical signal was input into vertical Ge-Si PD via packaged SSC waveguide with standard single mode fiber, then converted to current signals. Here, the input optical power is defined at the input of the optical fiber without deducting the SSC coupling loss. The single-ended current signals were linearly amplified to the electrical voltage signals in the TIA. The differential electrical signals are output by the GSSG probe. A supply voltage of 2.9 V was applied to the TIA. The overall power consumption of TIA is 190 mW. The output electrical data was measured with oscilloscope by two high-speed RF coaxial-cables. The TIA works in AGC mode. At transmitter side, the high-speed AWG output Vpp is set to be 800 and 300 mV for NRZ and PAM-4 eye diagrams test, respectively. The sampling oscilloscope was used to obtain the electrical eye diagrams. The high-speed electrical data streams were digitally captured by a real-time digital storage oscilloscope (DSO) with sampling rate of 256 GS/s (Keysight, UXR0704A), and then off-line DSP was carried out by computer for signal demodulation and BER calculation.
Fig. 3. Schematic of the experimental setup for the measurement of the eye diagrams and bit error rate. The black and red lines represent the optical and electrical connections, respectively. AWG, arbitrary waveform generator; PDFA, Praseodymium doped fiber amplifier; VOA, variable optical attenuator; PC, polarization controller; TFLN MZM, thin film lithium niobite Mach-Zehnder modulator.
Figure 4 shows the measured 56, 64, 90, and 100 Gbit/s NRZ clear opening eye diagrams of the differential electrical outputs of the 3D-integrated silicon photonics receiver at different input optical power. For the bit rate of 56 Gb/s NRZ signals, when the input optical power is up to 4 dBm, the differential electrical output amplitude can achieve 695 mV with signal-to-noise ratio (SNR) of 9.98 dB. Decreasing the optical power to 0 dBm, the SNR can improve to 10.72 dB, which might attribute to the reduction of PD and TIA nonlinear effect. But further reducing the power, the electrical amplitude and SNR degenerates quickly. For 100 Gbit/s NRZ eye diagram, the output amplitude can reach to 441 mV with SNR of 4 dB under 4 dBm input optical power. Even in the -2 dBm power, the output electrical amplitude still has 145 mV with SNR of 4.15 dB, which implies the high-speed and high-quality signal reception capability.
Fig. 4. Measured 56, 64, 90, and 100 Gb/s NRZ eye diagrams of the differential electrical outputs of the 3D-integrated silicon photonics receiver at different input optical power (X: 6 ps/div).
To further increasing the high-speed signal reception capability, the PAM-4 modulation format is investigated. The PAM-4 is also an efficient way to obtain higher bit rate with limited bandwidth. As we know that the PAM-4 transmission has at least 4.8 dB penalty in SNR compared to NRZ transmission, the TIA should operate in broad bandwidth and have a large output amplitude to obtain clear opening eye diagrams. Additionally, improving the overall linearity of transmitter is beneficial to obtain three equivalent eye openings for four-level electrical signals. The level separation mismatch ratio (RLM) is a metric for the linearity of the transmitter. The transmitter dispersion eye closure quaternary (TDECQ) is a significantly method of calculating the penalty for transmitters that have unequal sub-eyes. The TDECQs also depend on the input optical power of the receiver. So, the whole system design is vital to evaluate the performances of transmitter or receiver. The aim of marked TDECQ values in Fig. 5 is to exhibit the receiver capability under different optical power. In this work, the TDECQ was measured at a SD-FEC threshold of symbol error rate (SER) < 4.8E-4 (IEEE 802.3cd). The measured 56 and 64 Gbaud PAM-4 eye diagrams of the differential electrical outputs of the 3D-integrated silicon photonics receiver at different input optical power are shown in Fig. 5. The TDECQs penalty of the 56 Gbaud eye diagrams were 2.41, 1.67, and 1.56 dB for 1, -1, and -3 dBm input optical power, respectively. The RLM of obtained eye diagram were corresponding to 0.916, 0.981, and 0.985. For 64 Gbaud PAM-4 eye diagram, the differential output amplitude can achieve 477 mV with TDECQ penalty of 2.87 dB and RLM of 0.967 when the input optical power is 0 dBm. At higher input optical powers, the TDECQ penalty is mainly limited by the TIA linearity. Further decreasing the optical power to -1 and -3 dBm, the TDECQ and amplitude reduces simultaneously with better performances, as shown in Fig. 5.
Fig. 5. Measured 56 and 64 Gbaud PAM-4 eye diagrams of the differential electrical outputs of the 3D-integrated silicon photonics receiver at different input optical power (X: 6 ps/div).
3.3 Bit-error-rate measurements
To explore the sensitivity for our proposed receiver, the BER assessments were performed by operating the TIA in AGC mode. In the test process, pre-emphasis and post-compensation are implemented. Pre-emphasis is carried out in AWG to compensate for the bandwidth limitation of experimental equipment, modulator, and RF cable. Post-compensation is carried out by off-line DSP which is similar with our previous work [17]. In the DSP, adaptive 51-tap feed forward equalization (FFE) and adaptive maximum likelihood sequence estimation (MLSE) are utilized to realize channel estimation, inter-symbol interference (ISI) elimination, and faster than Nyquist transmission. The BER is finally calculated bit-by-bit. The optical input power of PD which is tuned through variable optical attenuator (VOA), can be concluded using the measured average photocurrent and the responsivity of PD. As shown in Fig. 6, the BER performances as a function of input optical power for 56 and 64 Gbit/s signal reception are obtained. With HD-FEC threshold, the sensitivities are -17.4 dBm and -16.5 dBm for 56 and 64 Gbit/s signal, respectively. However, for KP4-FEC threshold, the sensitivities are increased to -16.2 dBm and -15.1 dBm for 56 and 64 Gbit/s signal, respectively. Furth more, the sensitivities are measured to be -14.0, -12.7, -11.1, and -10 dBm for 80, 90, 100, and 112 Gbit/s NRZ signal reception under HD-FEC threshold, respectively. Additionally, the sensitivities are measured to be -12.2, -11.0, -8.3, and -5.2 dBm for 80, 90, 100, and 112 Gbit/s NRZ signal reception under KP4-FEC threshold, respectively.
Fig. 6. (a) Measured bit-error-rate (BRE) versus input optical power for 56 and 64 Gbit/s NRZ signal reception with HD-FEC and KP4-FEC condition. (b) Measured BER versus input optical power for 80, 90, 100 and 112 Gbit/s NRZ signal reception with HD-FEC and KP4-FEC condition.
Figure 7 shows the BER performances for the high-speed PAM-4 signal receptions. The sensitivities of -11.2, -9.8, -8.8, -6.6 dBm and -9.3, -7.4, -6.1, -2.7 dBm were achieved for 56, 64, 70, and 80 Gbaud PAM-4 at HD-FEC and KP4-FEC threshold, respectively. Additionally, the power consumption of the commercial linear TIA was 190 mW. Therefore, the energy efficiency for our 3D-integrated silicon photonics receiver is 1.2 pJ/bit at 80 Gbaud PAM-4 signal reception. These obtained results which include the experimental demonstration of 112 Gbit/s NRZ and 160 Gbit/s PAM-4 signal reception with high sensitivities exhibit the excellent performances of the 3D-integrated silicon photonics receiver.
Fig. 7. Measured bit-error-rate versus input optical power for 56, 64, 70, and 80 Gbaud PAM-4 signal reception with HD-FEC and KP4-FEC condition.
3.4 Comparison with state of the art
The characteristics of the representative silicon photonics receivers integrated with Ge-Si PDs and linear TIAs are summarized in Table 1. The 90, 100 Gbit/s NRZ [11,14], and 106 Gbit/s PAM-4 silicon photonics receivers [12] have been realized by wire-bonding technology. However, the wire inductance will limit the design of linear TIA and the final receiver performances. The flip-chip bonding has smaller parasitic inductance and capacitance and is beneficial to large scale multi-channel and high-speed integration. The reported 3D-integrated silicon photonics receiver is 112 Gbit/s PAM-4 with a power consumption of 2.8 pJ/bit [18]. In this work, by using the flip-chip bonding technology, a 3D-integrated receiver which consists of a high-speed Ge-Si PD and a commercial linear TIA is designed and demonstrated. Based on our previously reported optical receiver [22], to the best of our knowledge, the highest operation rate of 112 Gbit/s NRZ and 160 Gbit/s PAM4 with 1.7 and 1.2 pJ/bit power consumption are reported for the first time in this work. With the chip of PD and TIA bandwidths larger than 50 GHz [23–28], we believe that it is possible to realize single lane beyond 200 Gbit/s optical direct detection based on a 3D-integrated receiver.
Table 1. Comparison with State-of-the-Art Silicon Photonics Receivers
4. Discussion
As shown in Fig. 2(b), the overall OE bandwidths of the 3D-integrated optical receiver (PD + TIA) are investigated. However, in this work, the integrated-TIA is based on a commercially available product. The S21 optimization of PD and TIA is limited. By using the method of photonic-electronic co-design of silicon photonics, it is possible to optimize the S21 of PD and TIA to make the final S21 flatter [29,30]. In the future work, based on the self-designed TIA, we are considering to improve the S21 response of the 3D-integrated optical receiver. Another factor for the S21 response is the impedance match of the designed Ge-Si PD to commercial TIA. The single ended input impedance of commercial TIA is usually 50 Ω. So, the characteristic impedance of the PD GSG electrode is designed to be about 50 Ω before tape-out. This will allow the efficient power delivery and reduce the high frequency signal reflection.
Generally speaking, the SNR reduces with the increasing of speed for the same input optical power, as shown in Fig. 4. In the test process, at transmitter side, the high-speed optical signals are generated by self-packaged TFLNOI Mach-Zehnder modulator without automatic bias control (ABC). The absence of ABC would lead to the bias drift for long-time working situation, which affects the SNR of generated optical signal. So, the better SNR value for the 64 Gbit/s NRZ eye diagram is probably attributed to the degradation of working condition of TFLNOI modulator for 56 Gbit/s.
To further increase the receiver sensitivity, the Si/Ge-based avalanche photodetectors (APDs) are very attractive for low-power optical signal detection because of the potentially high internal gain [31–33]. The combination of Si/Ge APD and TIA might be an efficient way to detect high speed signal with high sensitivity and low power consumption. So far, a 56 Gbit/s NRZ hybrid BiCMOS-silicon photonics receiver with a waveguide-coupled Si/Ge APD has been demonstrated [34]. The sensitivity is as low as -18.6 dBm under the KP4-FEC threshold. More recently, the sensitivities of the receiver only with a lateral Si/Ge APD for 100 Gbit/s NRZ and PAM-4 signals are about -12.6 dBm and -11.3 dBm under the KP4-FEC threshold [35]. Once this high-performance Si/Ge APD integrated with 50 GHz bandwidth TIA by flip-chip bonding technology, the optical receiver would pave the way to realize higher speed and higher sensitivity data transmissions.
As we all know that, a typical optical transmission link consists of a transmitter (including laser, driver, DSP, and modulator) that converts high-speed electrical signals into optical domain, an optical fiber, and a receiver (including PD, TIA, and DSP) that converts the received high-speed optical signals back into electrical domain. The major source of power consumption in an optical link is the laser diode. Their power consumption is dominated by the amount of information that needs to be delivered to satisfy the BER requirements and receiver sensitivity conditions. Therefore, high-sensitivity optical receivers can help reduce the laser diode optical power, thus enabling low-power optical links. The power consumption of the whole optical link system should be comprehensively considered and designed. Here, we mainly focus on the realization of high-speed and low power consumption optical receiver. So, we only give the power consumption of the 3D-integrated silicon photonics receiver (PD + TIA). In the measurement process, the voltage supply to the commercial TIA is 2.9 V with about 190 mW power consumption. The Ge-Si PD is supplied by the TIA with 2.2 V voltage. The power consumption of the used commercial SHF driver (S804B) is about 2 W. Actually, the power consumption of DSP also needs to be considered for the optical receiver module. However, a typical optical receiver front-end is composed of a PD followed by a TIA and a cascade of main amplifiers. In this paper, the differential signal output of the receiver was captured by a real time digital storage oscilloscope (DSO) for further offline DSP. The DSP is executed off the chip by our algorithms with personal computer. So, the power consumption of the offline DSP is very hard to calculate. In the future, it is believed that the power consumption of DSP chip can be decreased to small value with the advanced CMOS and Bi-CMOS process. Therefore, the final receiver power to evaluate the energy efficiency is 190 mW, which excludes the power consumption of offline DSP, driver, PDFA, and laser [29,30].
5. Conclusion
By employing the advanced flip-chip bonding technology, a 3D-integrated silicon photonics receiver which consists of high-speed Ge-Si PD and commercial linear TIA is reported. The 3 dB bandwidth of the receiver is around 38 GHz with a good balance between the bandwidth and gain. Based on this receiver, the 56, 64, 90, and 100 Gbit/s NRZ and 56, 64 Gbaud PAM-4 modulation clear openings of eye diagrams are obtained. The eye diagram performances of SNR, amplitude, and TDECQs are also comprehensively investigated under different input optical power. The TDECQ penalty of 2.27 dB is realized for 128 Gbit/s PAM-4 signal reception. Additionally, the sensitivities of -10, -5.2 dBm and -6.6, -2.7 dBm were also achieved for 112 Gbit/s NRZ and 160 Gbit/s PAM-4 at HD-FEC and KP4-FEC threshold, respectively. The power consumption of 1.7 and 1.2 pJ/bit are calculated for operation rate of 112 Gbit/s and 160 Gbit/s signal reception. The experimentally demonstrated silicon photonics receiver exhibits the huge potential in realization of low-power, high-speed, and high-density 3D integration for data center and co-packaged optic (CPO) applications.
Funding
National Natural Science Foundation of China (62205255, U21A20454); Young Top-Notch Talent Cultivation Program of Hubei Province.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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