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Optica Publishing Group
  • Journal of Lightwave Technology
  • Vol. 32,
  • Issue 17,
  • pp. 3043-3060
  • (2014)

On the Design, Implementation, Analysis, and Prototyping of a 1- μs, Energy-Efficient, Carrier-Class Optical-Ethernet Switch Router

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Abstract

The integration of layer-2 carrier-class packet technologies with optical transport network is termed as packet-optical integration and is being deployed by service providers for migration from legacy SONET/SDH systems. We present a state-of-the-art carrier-class switch router that facilitates packet-optical integration, thereby achieving best of both the optical and packet worlds. The premise of this switch router is the use of carrier ethernet technology as a packet enabler for achieving statistical multiplexing at fine granularities, while maintaining rich operations, administration, maintenance, and provisioning features. To this end, we proposed the omnipresent ethernet concept that uses binary routing and source routing to support: 1) layer 2 and layer 3 switching and routing, 2) low latency of the order of 1–5 μs even for layer 3 processing, and 3) low-energy consumption. The omnipresent ethernet framework leads to a software defined networking solution, whereby a centralized controller admits services and configures nodes based on homogenous networking parameters. In this paper, we report a commercial implementation of a packet-optical network demonstrated by our designed, fabricated, developed carrier ethernet switch router (CESR). We discuss the architectural considerations, design, and implementation of both the hardware and the control software. A switch architecture achieving 1-μs port-to-port delay across layers 1, 2, and 2.5 based on an opportunistic principle of virtual output queuing is showcased. The novelty is a scalable 96-Gbps cross connect fabric implemented in a field programmable gate array using a two-stage buffer system. A multistate software defined control plane is also reported. An exact analysis of the switch architecture using a combinatorial G/G/1 model is developed. An energy audit of the CESR is showcased. A test bed in the lab replicating a field deployment is presented. An exhaustive set of test cases are developed to test our designed CESR. Results are shown for latency, throughput, service support, frame-size stability, power, and bit error rate, thus validating our design.

© 2014 IEEE

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