Abstract

During the past years, optical memories have emerged as the main way to enable fast access times and increased memory bandwidth in synergy with optical interconnections. The migration, however, to fully functional and practical optical RAMs and cache memories will require an additional yet essential step: Optical memories have to get organized into an optical memory subsystem for delivering seamless cooperation between storage and peripheral decoding units, exploiting also the wavelength dimension for efficient RAM architectural layouts. In this paper we demonstrate the first experimentally verified Wavelength Division Multiplexing (WDM) -enabled optical RAM Row subsystem comprising both the peripheral decoding circuitry and a 4-bit optical RAM Row for storing 20Gb/s 4-bit WDM-formatted optical data words. The proposed scheme comprises a single shared multi-λ Semiconductor Optical Amplifier Mach-Zehnder Interferometer (SOA-MZI) Access Gate (AG) for granting access-control to the complete RAM Row, a passive Column Decoder (CD) that directs the incoming WDM-formatted data words to the respective RAM cells that are in turn based on four broadband Indium Phosphide (InP) photonic integrated Flip-Flops (FFs). Our experimental verification firstly investigates the broadband capability of the elementary InP monolithic RAM cell at 5 Gb/s, revealing error-free Write functionality with <4.5 dB power penalty across the whole C-band confirming in this way the potential of efficient scaling to multi-cell WDM-enabled RAMs. Then, experimental validation of the complete 4-bit WDM-enabled optical RAM Row with 20 Gb/s WDM-formatted data words is performed, featuring simultaneous Access gating, decoding and storage operation for all four RAM cells, having a peak power penalty within the range of [4.6-5.6] dB for Write and [2.2-2.9] dB for Read functionalities, respectively, at a Bit Error Rate of 10⁻⁹.

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