Abstract

In this paper, we propose a receiver architecture capable of compensating for a time-varying signal distortion induced by the transmitter analog components. In the proposed architecture, the novel transmitter distortion compensating (TDC) block is implemented outside of the feedback control loop of the adaptive equalizer to suppress the feedback delay by optimizing the parameter used in the least mean square (LMS) algorithm. The proposed TDC block is designed for compensating for the DC offset, the IQ amplitude imbalance, the IQ orthogonality error, and the IQ timing skew. Our simulation results show that the proposed scheme significantly reduces the required signal-to-noise ratio penalty from the theoretical limit, which is imposed due to the transmitter components distortion. Furthermore, our theoretical analysis confirms that the delay induced in the feedback loop of the adaptive equalizer determines the upper bound of the LMS step size under the stable condition, hence allowing us to maximize the tracking speed of our receiver.

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