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Ultrafast all-optical NOR gate based on semiconductor optical amplifier and fiber delay interferometer

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Abstract

An ultrafast all-optical logic NOR gate based on a semiconductor optical amplifier (SOA) and a fiber delay interferometer (FDI) is presented. For high-speed input return-to-zero (RZ) signal, nonreturn-to-zero (NRZ) switching windows which satisfy Boolean NOR operation can be formed by properly choosing the delay time and the phase shift of FDI. 40Gb/s NOR operation has been demonstrated successfully with low control optical power. The factors that degrade the NOR operation have been discussed.

©2006 Optical Society of America

1. Introduction

All-optical signal processing would be a key technology in future high-speed optical communication networks in which all-optical logic operation is an elemental function. It can be widely used in all-optical demultiplexing, switching, buffering, regenerating, and computing etc. Nonlinear effects in semiconductor optical amplifier (SOA) have been widely investigated for realizing all-optical logic gates. A lot of schemes based on cross-gain modulation (XGM) have been reported, such as AND gates [1], NAND gate [2], NOR gates [3, 4], XOR gate [5] etc. Because of the slow carrier recovery process in the SOA, their output extinction ratio (ER) and pattern effects would be highly dependent on the operation bitrate. Recently, some kinds of logic gates have been successfully demonstrated at ultrafast operating speed, such as OR gate [6], XOR gates [7–10], and SOA-based switches, or the “AND” gates [11, 12]. In these schemes, interferometers based on cross-phase modulation (XPM) are employed to carry out delayed interference. Various type of interferometers have been investigated, such as Mach-Zehnder interferometers (MZIs) [7, 9], ultrafast nonlinear interferometers (UNIs)[8], delayed interferometers (DIs) [6, 10–12] etc.

In this letter, an ultrafast all-optical NOR gate based on the SOA-DI configuration, is proposed for the first time. The delayed interference is introduced by the fiber delay interferometer (FDI). By properly choosing the delay time and the phase shift of FDI, logic NOR operation can be realized at high speed with a SOA whose carrier recovery process is relatively slow. It should be noted that Ref. [6] has pointed out that NOR gate can be realized by cascading two sets of SOA-DI devices, while in our scheme one set of SOA-DI device can achieve NOR operation. A key difference between two schemes lies in the delay time of DI. The delay time must be relatively shorter than the bit period in Ref. [6], while in our scheme it must be equal to the operation bit period in order to effectively suppress the probe power during the bit period whose input data is “1” or “2”. The requirements on the recovery time of SOA are also different. In this letter, 40Gb/s operation for input return-to-zero (RZ) signal has been demonstrated successfully with low control optical power. Output nonreturn-to-zero (NRZ) signal is obtained. Note that the output RZ signal can be achieved by changing the continuous wave (CW) probe light into clock signal. Good consistency is observed between experiment and numerical simulation. Simulations at even higher operation speed have been taken out and a quality factor larger than 7 is found for the simulated 80Gb/s eye diagram. Factors that degrade the output performance of NOR operation have been discussed and the carrier recovery time of the SOA has been studied particularly.

2. Operation principle

The basic configuration of the ultrafast all-optical NOR logic gate is shown in Fig. 1(a). It consists of a SOA, a FDI, and a band pass filter (BPF). The time delay of the FDI is τ and the phase difference between two arms induced by the phase shifter is Φ0 . The BPF is used to extract the probe light and may not be necessary if the probe light is counter injected into the SOA. To illustrate the NOR operation, two input data streams are set to be “1001100” and “0100110” separately. The single bit period of these pulses is T. As shown in the lower curve of Fig. 1(c), the power combination of two data streams forms a new data stream “1101210” where “2” represents the power combination of two bit “1”s. The upper curve shown in Fig. 1(c) represents the simulated phase variation of the probe light modulated by data stream “1101210” through XPM in SOA. All the simulations throughout the letter are based on a comprehensive numerical model of a traveling wave SOA [14] under the operation conditions listed in Table 1 in section 4 (special words will be given if there is any exception). As shown in Fig. 1(c), during the “1” or “2” bit period (i.e. the 1st, 2nd , 4th, 5th, 6th period), phase variation of a certain profile is printed onto the probe light. Due to the fast carrier depletion and slow carrier recovery process of SOA, these profiles are quite similar to each other. Therefore, with the help of DI, the similarity of phase variation can be utilized so that the probe power in “1” or “2” bit periods can be suppressed through destructive interference. As shown in Fig. 1(d), Φ1(t) and Φ2(t) represent the phase variation in the upper and lower arms of FDI and satisfy the following relationship:

 figure: Fig. 1.

Fig. 1. Operation principle of the ultrafast all-optical NOR gate. (a) Basic configuration; (b) NOR truth table; (c) The phase variation (upper curve) modulated by the combined data stream (lower curve) in SOA; (d) Phase variations in the two arms of FDI (upper curves) and NRZ switching windows which satisfy Boolean NOR operation (lower curve).

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Φ2(t)=Φ1(tτ)+Φ0

In order to suppress the probe power during the “1” or “2” bit periods, Φ1(t) and Φ2(t) must satisfy

Φ2(t)=Φ1(tT)+δΦ+(2m+1)π,m=0,±1,±2,

Comparing Eq. (1) with Eq. (2), τ and Φ0 of the FDI must satisfy the following relations:

τ=T,Φ0=δΦ+(2m+1)π,m=0,±1,±2,

where δΦ is physically caused by the slow carrier recovery process of the SOA and will be positive if the recovery time of SOA is relatively slower than the operation bit period. The actual value of δΦ varies according to the operation condition of SOA. At the same time, the probe power in “0” bit periods is preserved due to the incomplete destructive interference or even constructive interference. Therefore, if properly choose the delay time and the phase shift of FDI so that Eq. (3) is satisfied, NRZ switching windows can be formed at the output of FDI when bit “0” appears in both data streams, as shown by the lower curve in Fig. 1(d). As a result, NOR result can be obtained (see the truth table in Fig. 1(b)) and the data format of the output signal is determined by the probe light. That is, the output signal will be NRZ format if the probe light is CW signal and RZ format if clock signal is used instead. Factors that lead to the degradation of the output performance of NOR operation will be discussed in part 4.

3. Experiment setup and results

The experimental setup for the ultrafast all-optical NOR gate is shown in Fig. 2. In this experiment, the wavelengths of three CW signals generated by LD1, LD2, LD3 were 1549.32nm(λ 1), 1563.9nm(λ 2) and 1555.75nm(λC) respectively. Two cascaded Mach-Zehnder Modulators (MZMs) were driven by data signal and clock signal respectively which were provided by the bit pattern generator (BPG). Two identical 40Gb/s data streams at different wavelength were generated at the output of the second MZM. The duty cycle of these RZ pulses was 33%. Two wavelengths were separated by the wavelength division multiplexer (WDM) and one of them was delayed one bit period by an optical delay line (ODL). Therefore, two data streams with different data pattern and wavelength were obtained at the output of the optical coulper2 (OC2). The average optical power measured at the input of SOA were -3.96dBm(λ 1), -3.69dBm(λ 2) and -2.67dBm(λC) respectively. The SOA is a strained multiple quantum-well device with an active region of 450 μm. The driving current of SOA is 100mA. Under this current the small signal gain@1550nm is 13dB and the input saturation power is -10dBm. The 90%~10% recovery time of SOA, defined as the time needed for the gain compression to recover from 90% to 10% of the initial compression, was measured separately to be 100ps under this operation condition. The final results were analyzed through Communication Signal Analyzer (CSA). The time delay τ of FDI was fixed to 25ps for satisfying Eq. (3). The phase shift Φ0 of the FDI was controlled by changing its working temperature. NOR result can be achieved by tuning the phase shift Φ0 carefully. Experimental and corresponding simulation results are presented in Fig. 3.

 figure: Fig. 2.

Fig. 2. Experimental Setup of the NOR gate

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 figure: Fig. 3.

Fig. 3. 40Gb/s experimental and simulated results. (a)Experimental results with fixed data pattern. Traces from the top to bottom are: data stream “00010011”; coupled two data streams of “00010011” and “00100110”; the output NOR signal in NRZ format. (c)Experimental eye diagram for 27-1 PRBS input data steams. (b)(d)Corresponding simulated results.

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Figure 3(a) shows the output NOR signal (bottom trace) observed by CSA with two input data streams which were fixed to be periodic “00010011” (top trace) and “00100110” respectively. The middle trace in Fig. 3(a) represents the combination of two data streams. Notice that NRZ format output signal was obtained since the probe light was CW signal. Sub-pulses are observed. The output ER was measured to be more than 10dB without considering the sub-pulses but reduced to 6dB when these pulses are taken into account. Figure 3(c) is the eye diagram of NOR operation result for 27-1 pseudo random binary sequence (PRBS) data streams. An open eye is observed. Figures 3(b) and (d) are corresponding simulated results. It should be noted that when calculating the interference, XGM were also taken into consideration for accuracy. Good consistency between simulation and experiment can be found including sub-pulses as well as the thick ground eyelid aroused by them. As will be discussed in part 4, sub-pulses are highly relevant to the modulated status of phase variation. The relative thin upper eyelid observed in both simulation and experiment may in a large part be the result of the following mathematical fact. The probability of two consecutive bit “1”s in NOR results is 1/16, comparing to 1/4 in original data streams where bit “1” and “0” have the same chance to appear.

4. Discussion

As mentioned above, the ideal modulated status of phase variation must be the one in which the profiles of phase variation induced by “1” or “2” pulses are identical to each other. In such case the ER of the NOR operation will be infinity since output logic “0”s are formed by completely destructive interference. Of course, enough amount of phase variation must be printed onto the probe light in order to obtain high optical signal to noise ratio (OSNR). For this reason, according to Ref. [11], the current of SOA should be increased correspondingly when the operation speed increases.

Sub-pulses observed both in simulation and experiment reveal the deviation from the ideal status and lead to the degradation of the output NOR signal. They are mainly induced by two effects. First, due to the power difference between bit “1” and “2”, phase variations induced by them would be different. The second effect is the nonlinear patterning (NLP) effect [13] of SOA, i.e. the phase variation induced by identical bits that come consecutively would decrease gradually. As shown by the upper curve in Fig. 1(c), the first effect can be observed by comparing the phase shifts introduced in the 4th and 5th bit period and the NLP effect can be verified by comparing the 4th and 6th bit period. The position and amount of sub-pulses vary according to the magnitude of two effects. This could explain the different sub-pulses observed between Fig. 3(a) and (b) and suggests that the roles of two effects played in experiment and simulation are not identical. In order to reduce the first effect, SOA must be operating in the saturation regime and according to Ref. [13], shortening the recovery time of SOA helps reducing the NLP effect. However, simulations show that too short recovery time of SOA would lead to oblique “1” level and degrade the final results. As can be seen from fig. 1(d), in order to get flat “1” level, the phase recovery process during the recovery time of SOA should be quasi-linear. Once the SOA recovers fully or near steady state, the process of phase recovery significantly diverts from linear region.

In order to investigate the effect of the SOA recovery time comprehensively, quality factor Q has been calculated and the relationship between Q factor and the 90%~10% recovery time (“recovery time” for short in the following discussion) of SOA has been studied. Following [15], the Q factor is defined as

Q=P1P0σ1+σ0

where P 1(P 0) and σ 1(σ 0) stand for the average power and standard deviation of the “1” (“0”) bits. In order to simulate different recovery time that come from different SOA devices, the recombination carrier lifetime τc [15] in Table 1 was set different values directly while other parameters were fixed. Note that the small signal gain G 0 in Table 1 will decrease simultaneously as tc increases for a fixed current and input power. It reduces to 6dB when τc is increased to obtain a 250ps recovery time. Figure 4 shows the calculated Q factor versus different recovery time when the NOR gate is operating at 40Gb/s (circle) and 80Gb/s (triangle) respectively. Optimum values of the recovery time are observed for fixed operation bitrates. Note that the optimum recovery time decreases when the operation bitarte increases from 40Gb/s to 80Gb/s. This is due to the fact that for a given SOA whose recovery time is fixed, the shorter the single bit duration time the better the SOA could sustain consecutive “0”s. The insets of Fig. 4 show the simulated eye diagrams corresponding to different operation conditions. The lower eye diagrams reveal certain extent of degradation with respect to the optimum condition (the upper eye diagram). As mentioned above, oblique "1" level appears when the recovery time becomes short, while on the opposite direction large noise in “1” level appears and can be explained as the result of aggravating NLP effect. The upper eye diagram shows the optimum situation in 80Gb/s simulations. Q larger than 7 is found and goes even better than that of 40Gb/s, which suggests that the NOR gate could be expected to operate at even higher speed than that has been demonstrated experimentally.

Tables Icon

Table 1. The operation conditions of SOA in simulations

 figure: Fig. 4.

Fig. 4. Q factor vs. 90%~10% recovery time when the NOR gate is operating at 40Gb/s (circle) and 80Gb/s (triangle). The insets: simulated eye diagrams corresponding to different operation conditions (pointed by arrows).

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5. Conclusion

An ultrafast all-optical NOR gate based on the SOA and FDI is proposed for the first time. For input RZ signal, with proper delayed interference introduced by the FDI at output of SOA, NOR switching windows could be formed at the slow recovery process of SOA at high operation bitrate. 40Gb/s NOR operation has been demonstrated successfully with low optical control power. The output signal was obtained in NRZ format. However, it can be turned into RZ format by changing the CW probe light into clock signal. Simulations show that higher operation speed can be expected. The factors that lead to the degradation of the NOR operation have been discussed. The discussion shows that the ideal modulated status of phase variation is the one in which the profiles of phase variations induced by “1” or “2” pulses are identical. The derivation from the ideal status leads to the degradation of the output performance and the recovery time of SOA which plays an important role is studied particularly.

Acknowledgments

The work was supported by the National Natural Science Foundation of China (Grant No. 60407001), the Science Fund for Distinguished Young Scholars of Hubei Province (Grant No. 2006ABB017) and the Program for New Century Excellent Talents in Ministry of Education of China (Grant No. NCET-04-0715).

References and links

1. X. Zhang, Y. Wang, J. Sun, D. Liu, and D. Huang, “All-optical AND gate at 10 Gbit/s based on cascaded single-port-couple SOAs,” Opt. Express 12, 361–366 (2004). [CrossRef]   [PubMed]  

2. S.H. Kim, J.H. Kim, B.G. Yu, Y.T. Byun, Y.M. Jeon, S. Lee, D.H. Woo, and S.H. Kim, “All-optical NAND gate using cross-gain modulation in semiconductor optical amplifiers,” Electronics Letters 41, 1027–1028(2005). [CrossRef]  

3. A. Hamie, A. Sharaiha, M. Guegan, and B. Pucel, “All-optical logic NOR gate using two-cascaded semiconductor optical amplifiers,” IEEE Photon. Technol. Lett. 14, 1439–1441(2002). [CrossRef]  

4. C. Zhao, X. Zhang, H. Liu, D. Liu, and D. Huang, “Tunable all-optical NOR gate at 10 Gb/s based on SOA fiber ring laser,“ Opt. Express 13, 2793–2798 (2005). [CrossRef]   [PubMed]  

5. J.H. Kim, Y.M. Jhon, Y.T. Byun, S. Lee, D.H. Woo, and S. H. Kim, “All-optical XOR gate using semiconductor optical amplifiers without additional input beam,” IEEE Photon. Technol. Lett. 14, 1436–1438(2002). [CrossRef]  

6. Q. Wang, H. Dong, G. Zhu, H. Sun, J. Jaques, A.B. Piccirilli, and H.K. Dutta, “All-optical logic OR gate using SOA and delayed interferometer,” Optics Communications 260, 81–86(2006). [CrossRef]  

7. R. P. Webb, R. J. Manning, G. D. Maxwell, and A. J. Poustie, “40 Gbit/s all-optical XOR gate based on hybrid-integrated Mach-Zehnder interferometer,” Electron. Lett. 39, 79–81(2003). [CrossRef]  

8. R. P. Webb, R. J. Manning, and R. Giller, “All-optical 40 Gb/s logic XOR gate with dual ultrafast nonlinear interferometers,“ Electron. Lett. 41, 49–50(2005). [CrossRef]  

9. Q. Wang, G. Zhu, H. Chen, J. Jaques, J. Leuthold, A. B. Piccirilli, and N. K. Dutta, “Study of all-optical XOR using Mach-Zehnder interferometer and differential scheme,” IEEE J. Quantum Electron. 40, 703–710(2004). [CrossRef]  

10. H. Sun, Q. Wang, H. Dong, Z. Chen, H.K. Dutta, J. Jaques, and A.B. Piccirilli, “All-optical logic xor gate at 80 Gb/s using SOA-MZI-DI,” IEEE J. Quantum Electron. 42, 747–751(2006). [CrossRef]  

11. Y. Ueno, S. Nakamura, and K. Tajima, “Nonlinear phase shifts induced by semiconductor optical amplifiers with control pulses at repetition frequencies in the 40-160-GHz range for use in ultrahigh-speed all-optical signal processing,” J. Opt. Soc. Am. B 19, 2573–2589 (2002). [CrossRef]  

12. M. Nielsen and J. Mørk, “Bandwidth enhancement of SOA-based switches using optical filtering: theory and experimental verification,” Opt. Express 14, 1260–1265 (2006). [CrossRef]   [PubMed]  

13. M. L Nielsen and J. Mørk, “Increasing the modulation bandwidth of semiconductor-optical-amplifier-based switches by using optical filtering,” J. Opt. Soc. Am. B 21, 1606–1619 (2004). [CrossRef]  

14. Z. Jiang, X. Zhang, D. Liu, and D. Huang, “Theoretical and experimental investigation on carrier recovery time in semiconductor optical amplifier”, in Semiconductor and Organic Optoelectronic Materials and Devices, Chung-En Zah, Yi Luo, and Shinji Tsuji, eds., Proc. SPIE 5624, 563–574(2004).

15. G. P. Agarwal, Fiber-Optic Communication Systems (Wiley, USA, 1997).

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Figures (4)

Fig. 1.
Fig. 1. Operation principle of the ultrafast all-optical NOR gate. (a) Basic configuration; (b) NOR truth table; (c) The phase variation (upper curve) modulated by the combined data stream (lower curve) in SOA; (d) Phase variations in the two arms of FDI (upper curves) and NRZ switching windows which satisfy Boolean NOR operation (lower curve).
Fig. 2.
Fig. 2. Experimental Setup of the NOR gate
Fig. 3.
Fig. 3. 40Gb/s experimental and simulated results. (a)Experimental results with fixed data pattern. Traces from the top to bottom are: data stream “00010011”; coupled two data streams of “00010011” and “00100110”; the output NOR signal in NRZ format. (c)Experimental eye diagram for 27-1 PRBS input data steams. (b)(d)Corresponding simulated results.
Fig. 4.
Fig. 4. Q factor vs. 90%~10% recovery time when the NOR gate is operating at 40Gb/s (circle) and 80Gb/s (triangle). The insets: simulated eye diagrams corresponding to different operation conditions (pointed by arrows).

Tables (1)

Tables Icon

Table 1. The operation conditions of SOA in simulations

Equations (4)

Equations on this page are rendered with MathJax. Learn more.

Φ 2 ( t ) = Φ 1 ( t τ ) + Φ 0
Φ 2 ( t ) = Φ 1 ( t T ) + δ Φ + ( 2 m + 1 ) π , m = 0 , ± 1 , ± 2 ,
τ = T , Φ 0 = δ Φ + ( 2 m + 1 ) π , m = 0 , ± 1 , ± 2 ,
Q = P 1 P 0 σ 1 + σ 0
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