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We developed a single-flux-quantum (SFQ) readout technology for superconducting single-photon detectors (SSPDs) to achieve low-jitter signal readout. By optimizing circuit parameters of the SFQ readout circuit, the input current sensitivity was improved below 10 μA, which is smaller than a typical critical current of SSPD. The experiment using a pulse-pattern generator as an input pulse source revealed that the measured jitter of the SFQ readout circuit is well below the system jitter of our measurement setup for the input current level above 15 μA. The measured jitter of the SSPD connected to the SFQ readout circuit was 37 ps full width at half maximum (FWHM) for an SSPD bias current of around 18 μA, which is a significant improvement on 67 ps FWHM jitter observed in conventional readout without an SFQ readout circuit.
©2012 Optical Society of America
1. Introduction
Superconducting single-photon detectors (SSPDs) made of niobium nitride (NbN) nanowire have attracted attention because of their high detection efficiency (DE) at near-infrared wavelengths, high counting rate, low dark count rate (DCR), wide detectable wavelength range and low timing jitter [1]. Of these features, the low timing jitter is especially important in many applications, such as quantum key distribution (QKD) systems [2–4], space-to-ground communications [5], as well as light detection and ranging (LIDAR) systems [6]. However, the intrinsic jitter of the SSPD is difficult to determine, because the measured jitter includes the jitter produced by the readout electronics.
Our past experiments reveal that the timing jitter of an SSPD depends on the bias current, which flows to the readout electronics during the resistive state of the nanowire. The timing jitter significantly increases as decreasing the bias current below 20 μA, while it is almost constant for a large bias current above 30 μA. In addition, a given amount of bias current gives rise to almost the same jitter, even for two different SSPDs with different IC’s. These imply that the measured jitter is mainly determined by the current sensitivity of the readout electronics rather than the intrinsic jitter. As a result, the timing jitter of an SSPD depends on its critical current (IC), because the bias current is set below the IC. On the other hand, a higher DE is attainable for an SSPD with a thinner NbN film and/or narrower wire, both of which decrease the IC of the SSPD, resulting in a larger jitter. Thus, readout electronics with a higher current sensitivity are highly desirable for achieving both a high DE and low jitter.
A single-flux-quantum (SFQ) logic circuit operating at cryogenic temperatures is a promising technology for signal readout from the SSPD [7–11]. The original purpose of utilizing the SFQ circuit was to reduce the number of output cables from a multi-element SSPD by processing the output signals in a cryogenic environment [8], but low-jitter operation of the SFQ circuit is also attractive for signal readout from the SSPD. We have already demonstrated SFQ readout operation from the SSPD [7, 9]; however, the advantage of employing the SFQ readout circuit to achieve low-jitter readout has not yet been demonstrated. This is mainly due to the lack of current sensitivity of a front-end circuit called the magnetically coupled DC/SFQ (MC-DC/SFQ) converter, because the timing jitter observed in the SFQ readout strongly depends on the input pulse amplitude and a lower amplitude results in a higher timing jitter.
In this letter, we report on the improvement of the current sensitivity and the timing jitter of the SFQ readout circuit. A careful re-optimization of circuit parameters in the MC-DC/SFQ converter significantly improves the input current sensitivity. The resulting SFQ readout circuit timing jitter is reduced well below the system jitter of our measurement setup. The timing jitter of the SSPD measured with the SFQ readout circuit is dramatically reduced compared to that measured by a conventional readout using a bias tee and a low-noise amplifier (LNA) operated at room temperature.
2. Circuit parameter optimization for low-jitter readout
Figure 1(a) shows the equivalent circuit of the MC-DC/SFQ converter. The operation of the MC-DC/SFQ converter is as follows. First, the Josephson junction J2 switches at the rising edge of an input pulse, generating an SFQ propagating to the right. At the same time, another SFQ is stored in the superconducting loop including the inductor L2, which generates a current circulating anti-clockwise in the L2 loop and prevents double-switching of J2 even at the peak level of the input pulse. At the falling edge of the input pulse, the stored SFQ in the L2 loop is canceled out by the switching of J1 and the circuit returns to the initial state. Thus, an input pulse is converted into a single SFQ pulse.
Fig. 1 (a) Equivalent circuit of MC-DC/SFQ converter. (b) Operating margin of MC-DC/SFQ converters with ICJ1 = 100 μA, 130 μA, and 140 μA.
In the previous design, the IC’s of J1 and J2 (ICJ1 and ICJ2) were set at 100 μA, which is the smallest value allowed in an SRL 2.5 kA/cm2 Nb standard process [12]. The area surrounded by the black line in Fig. 1(b) indicates the operating region experimentally obtained for the previous MC-DC/SFQ converter. The vertical and horizontal axes in Fig. 1(b) are the current amplitude of the input pulse (IP) and the dc bias current of the MC-DC/SFQ converter (IBDS), respectively.The operating region of IP decreases as IBDS increases, indicating that higher current sensitivity is attainable for higher IBDS. Here the current sensitivity is the lowest IP value in the operating IP region for a given IBDS. In the previous MC-DC/SFQ converter with ICJ1 = ICJ2 = 100 μA, the operating region of IP ends for an IBDS above 0.89 mA and the resulting maximum current sensitivity was as large as 14 μA. We found that the malfunction of IBDS above 0.89 mA results from the undesirable switching of J1 immediately after the switching of J2, which causes J2 to switch again generating two SFQ pulses at the rising edge of the input pulse. To avoid this malfunction, the ICJ1 must be increased as much as possible. The areas surrounded by the red line and the blue line in Fig. 1(b) respectively indicate the measured operating regions of the redesigned MC-DC/SFQ converters with the ICJ1’s of 130 μA and 140 μA, where all circuit parameters other than ICJ1 are kept constant. The maximum current sensitivity for an ICJ1 of 140 μA is less than 10 μA at an IBDS above 0.95 mA.
On the other hand, the lower margin of IBDS is restricted by missing errors on J1 switching at the falling edge of input pulses, which prevents the reset operation to the initial state. As shown in Fig. 1(b), the lower margin of IBDS increases with increasing ICJ1. We have never attempted to use an ICJ1 of 150 μA, but the circuit simulation revealed that the lower limit of IBDS for an ICJ1 of 150 μA exceeds 0.86 mA, resulting in too small an operating margin for IBDS. To maintain an appropriate operating margin while achieving a high current sensitivity, we determined the optimal ICJ1 value to be 140 μA.
3. Current sensitivity measurement
To check the input current sensitivities of the MC-DC/SFQ converters in detail, we measured the error rate (ER) of the SFQ readout circuit by using a pulse-pattern generator (PPG) and a pulse counter. The experimental setup is shown in Fig. 2 . The detailed design of the SFQ readout circuit other than the MC-DC/SFQ converter is described elsewhere [7, 9], but a brief review is given here. The SFQ readout circuit has four MC-DC/SFQ converters, one of which was used in this experiment. The data output from the PPG was input to the SFQ readout circuit and converted into the SFQ pulse by the MC-DC/SFQ converter. The generated SFQ pulses propagate from the MC-DC/SFQ converters to the voltage driver via Josephson transmission lines and confluence buffer (CB) gates, neither of which requires a clock pulse for operation [13]. The SFQ pulses are then converted into rectangular pulses with an amplitude of around 2.0 mV and a duration of around 0.8 ns by the voltage driver for detection by the room temperature electronics. The SFQ readout circuit was dipped into liquid helium using a test probe with two 1.2 m long coaxial cables for input and output RF signals. To drive the SFQ readout circuit, a total bias current of around 60 mA was supplied through four cables. The output pulses from the voltage driver circuit were amplified by an LNA with the gain of 52 dB and detected by the pulse counter. The return-zero pulse sequence of “111…” with the repetition frequency of 10 MHz was used for the measurement.
Fig. 2 Experimental setups for error rate and jitter measurement. Pulse counter used in the error rate measurement is replaced by TCSPC module in the jitter measurement. In both measurements, pulse-pattern generator is employed as a signal source.
Figure 3 shows the IP dependences of the measured ERs. If we define the input current sensitivity as the lowest IP value that gives the ERs below 10−6, the input current sensitivities are read as 13.8 μA, 10.4 μA and 8.2 μA for the ICJ1 of 100 μA, 130 μA and 140 μA, respectively. The ER curves are fitted well by error functions, suggesting an existence of thermal noise. The standard deviations (σ’s) evaluated from the fitting are 0.45 μA, 0.48 μA and 0.52 μA for the ICJ1 of 100 μA, 130 μA and 140 μA, which correspond to 2.64 μA, 2.81 μA and 3.05 μA taking the current gain of the input transformer (M/L2 = 66.2 pH/11.3 pH = 5.86) into account. At the temperature of around 4.2 K, the σ corresponds to the thermal noise current given by (4kBTB/R)1/2, where kB is the Boltzmann’s constant, R is shunt resistor of the J2, T is temperature, and B is the bandwidth over which the noise is measured. In the Josephson junctions, the B can be approximated by the plasma frequency fp = (IC/2πΦ0C)1/2, where Φ0 is flux quantum and C is junction capacitance. Maezawa et al. reported that the relation between specific capacitance CS and critical current density JC of Nb/AlOX/Nb junctions is given by 1/CS = 0.20-0.043log10JC [14]. Using this equation, the fp is calculated as 190 GHz for the JC of 2.5 kA/cm2, which gives the σ of 3.3 μA for T = 4.2 K and R = 3.7 Ω. This value roughly agrees with the experimentally obtained σ of 2.64~3.05 μA, supporting that the measured ER curves are quantitatively characterized by the thermal fluctuation model.
Fig. 3 Error rate curves for IP observed in SFQ readout circuit with ICJ1 = 100 μA, 130 μA and 140 μA.
4. Jitter measurement of SFQ readout circuit
We measured the timing jitter of the SFQ readout circuit by replacing the pulse counter to a time-correlated single photon counting (TCSPC) module with 1 ps time resolution. The complimentary data output of the PPG was input to the TCSPC module as a trigger. The time correlation between the trigger and the output from the SFQ readout circuit was recorded, creating a histogram of the pulse count. The timing jitter was defined as the full width at half maximum (FWHM) of the observed peak in the histogram. The histogram for the IP above 15 μA showed a Gaussian shape, while a tail structure appeared for the IP below 15 μA. This is due to a non-linear dependence of the J2 switching delay for the IP in the small IP range. This indicates that a Gaussian shape response of the SSPD does not affected by the SFQ readout if the bias current above 15 μA is applied to the SSPD.
The timing jitters for the MC-DC/SFQ converters with an ICJ1 of 130 μA and 140 μA were measured, where IBDS was set at the maximum value for each MC-DC/SFQ converter. Figure 4 shows the IP dependence of the timing jitter. The timing jitter decreases as IP increases and reaches the lowest value of around 30 ps for a sufficiently large IP. To determine the origin of this residual jitter of 30 ps, we eliminated the SFQ readout circuit and measured the system jitter produced by the PPG, the LNA and the discriminator in the TCSPC module. The result is shown in the inset in Fig. 4. The system jitter depends on the input level of the LNA (VINAMP). A VINAMP of 2.0 mV, which corresponds to the output level from the SFQ voltage driver, gives a timing jitter of around 30 ps. This value is almost comparable with the residual jitter of 30 ps observed in the SFQ readout circuit, suggesting that the timing jitter produced by the SFQ readout circuit is not measurable by our experimental setup for sufficiently large IP.
Fig. 4 IP dependence of timing jitter observed in SFQ readout circuit with ICJ1 = 130 μA and 140 μA.
On the other hand, a rapid increase of the timing jitter is observed for decreasing IP due to the lack of current sensitivity of the MC-DC/SFQ converter. The rapid increase of the timing jitter starts below an IP of around 15 μA for ICJ1 = 140 μA, and below 20 μA for ICJ1 = 130 μA. This conversely indicates that negligibly low-jitter readout is achievable for an IP above 15 μA by employing the SFQ readout circuit with ICJ1 = 140 μA. As a typical SSPD with an IC of less than 20 μA exhibits a timing jitter of more than 60 ps, the SFQ readout is attractive for signal readout from the SSPD for an IC of around 20 μA or less.
5. Jitter measurement of SSPD using SFQ readout circuit
We implemented the SFQ readout circuit with the SSPD on the same workspace in a 0.1 W Gifford-McMahon (GM) refrigerator. The experimental setup is shown in Fig. 5(a) . The SFQ readout circuit was connected to the SSPD via a 10 cm long RF cable with the bandwidth of up to 65 GHz. We used an SSPD with a detection area of 15 x 15 μm2 and an IC of around 18 μA. The fabrication of the SSPD and its implementation in the refrigerator, including the method of fiber coupling are described in detail elsewhere [15, 16]. The IC of 18 μA is a reasonable value for a given thickness and width of the NbN nanowire, indicating that the the NbN nanowire does not include significant constrictions, which causes an increase of the timing jitter [17]. The system DE was about 16% at DCR = 100. The DC bias current to the SSPD (ISSPD) was supplied via a 5 kΩ resister fabricated on the SFQ chip without any bias tees, reproducing the same DE curves as those observed in our conventional readout as shown in Fig. 5(b). A 1550 nm wavelength pulsed laser with a 100 fs pulse width and 80 MHz repetition rate was used as the photon source, where the average number of photons was fully attenuated to below one per pulse. The temperature of the workspace was kept at around 2.4 K during the measurement.
Fig. 5 Experimental setups for measuring timing jitter of SSPD. (a) Readout using SFQ circuit. (b) Conventional readout using bias tee and LNA operating at room temperature.
The measured histogram has a Gaussian shape for the measurement both with and without the SFQ readout circuit as reported in our previous report [7], while the histogram with the SFQ readout circuit deviated from a Gaussian shape for the ISSPD below 15 μA for the reason described in section 4. Figure 6 shows the ISSPD dependence of the FWHM jitter measured in the setup shown in Fig. 5(a) and 5(b). In our conventional readout without the SFQ circuit [18], the 50 Ω resistor is usually connected to the SSPD in parallel, and acts as an escape path for the ISSPD when the SSPD goes into a resistive state known as “latching.” The effect of the 50 Ω parallel shunt is clearly seen in Fig. 6. The upper limit of ISSPD is about 18 μA for the SSPD with the parallel shunt, and as large as 14.5 μA without the parallel shunt. During practical use of the SSPD, the 50 Ω shunt resistor is thus indispensable for achieving as high a DE as possible. However, the parallel shunt also makes the input current of the LNA half of ISSPD, causing an increase of the timing jitter. The resulting timing jitter with the parallel shunt is as low as 67 ps even at the maximum ISSPD of 18 μA. On the other hand, the timing jitters with the SFQ readout circuit are as low as 50 ps for an ISSPD above 15 μA. The timing jitter at an ISSPD of around 18 μA is 37 ps, which is significantly improved from the 67 ps measured for the conventional readout with the 50 Ω parallel shunt. Further, a timing jitter of 37 ps could not be achieved by the conventional readout without the 50 Ω shunt even if ISSPD could be increased to 18 μA. Therefore, the SFQ readout circuit offers a great advantage for achieving a low-jitter signal readout form the SSPD while keeping the DE as high as possible.
Fig. 6 ISSPD dependence of FWHM jitter of SSPD. The measured jitter is plotted for conventional readout with and without 50 Ω shunt resistor and for SFQ readout.
One may be concerned with the difference between the system jitter of 30 ps observed in the measurement using the PPG and the jitter of 37 ps observed in the measurement using the SSPD. If an intrinsic jitter produced by the SSPD is responsible for this difference, the intrinsic jitter is estimated as (372-302)1/2 = 22 ps. However, we are not confident that the 7-ps difference of the jitter is only on account of the intrinsic jitter of the SSPD, because the jitter measured by using the PPG is almost constant at 30 ps for an IP above 15 μA, while the jitter measured with the SSPD slowly decreases even for an ISSPD above 15 μA. This suggests that the jitter produced by the SFQ circuit depends on not only the input pulse amplitude but also its shape. According to an observation using a sampling oscilloscope, the rising edge of the output pulse from the SSPD is measured as around 250 ps, while that from the PPG is around 50 ps. More detailed measurement will be necessary to determine the intrinsic jitter of the SSPD, but it is beyond the scope of this letter.
6. Conclusion
In summary, we demonstrated low-jitter signal readout from the SSPD by optimizing circuit parameters in the SFQ readout circuit. By increasing the ICJ1 value in the MC-DC/SFQ converter, an input current sensitivity of 8.2 μA was achieved, which is a considerable improvement from the 13.8 μA obtained in the previous design. The measurement using a PPG showed that the SFQ readout circuit exhibits an unmeasurable jitter for an IP above 15 μA, which was well below the system jitter of 30 ps in our experimental setup. The SFQ readout circuit was implemented with the SSPD in a 0.1 W GM refrigerator and directly connected to the SSPD without a bias tee. The FWHM jitter of the SSPD measured with the SFQ readout circuit was 37 ps, which was much lower than the 67 ps observed in our conventional readout using a bias tee and LNA operated at room temperature. These results show that SFQ readout technology is very attractive for not only signal processing of the multi-element SSPD but also low-jitter signal readout from SSPDs.
Acknowledgments
The authors would like to thank M. Sasaki and M. Fujiwara of the Quantum Information and Communication Technology Group of NICT for their fruitful discussion.
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